CN109065455A - The preparation method of thin film transistor (TFT) and the thin film transistor (TFT) prepared using this method - Google Patents
The preparation method of thin film transistor (TFT) and the thin film transistor (TFT) prepared using this method Download PDFInfo
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- CN109065455A CN109065455A CN201810876708.1A CN201810876708A CN109065455A CN 109065455 A CN109065455 A CN 109065455A CN 201810876708 A CN201810876708 A CN 201810876708A CN 109065455 A CN109065455 A CN 109065455A
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- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 253
- 229910052751 metal Inorganic materials 0.000 claims abstract description 76
- 239000002184 metal Substances 0.000 claims abstract description 76
- 239000010408 film Substances 0.000 claims abstract description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 39
- 238000001312 dry etching Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 238000012545 processing Methods 0.000 claims abstract description 11
- 238000001039 wet etching Methods 0.000 claims abstract description 11
- 238000002161 passivation Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 238000009499 grossing Methods 0.000 claims description 4
- 238000009413 insulation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 description 22
- 230000008569 process Effects 0.000 description 16
- 239000000463 material Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 7
- 239000007788 liquid Substances 0.000 description 7
- 239000000460 chlorine Substances 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 5
- 229910052801 chlorine Inorganic materials 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 239000004411 aluminium Substances 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000005020 polyethylene terephthalate Substances 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of preparation method of thin film transistor (TFT) and the thin film transistor (TFT) using this method preparation, and preparation method on substrate comprising steps of form grid, gate insulating layer, semiconductor layer, ohmic contact layer and metal layer；Patterned photoresist layer is formed on the metal layer；First time wet etching is carried out, patterned metal layer is formed, patterned metal layer has the side of exposure；Processing is passivated to the side of metal layer exposure, to form passivating film on exposed side；First time dry etching is carried out, part ohmic contact layer is removed and semiconductor layer, passivating film avoids the side of metal layer from being etched；Second of wet etching is carried out, partial metal layers are removed, forms source-drain electrode data line layer, metal layer has surface to be exposed；Second of dry etching is carried out, part ohmic contact layer is removed, forms active layer；Go removing photoresistance layer, exposure source-drain electrode data line layer；Interlayer insulating film and pixel electrode are deposited, thin film transistor (TFT) is formed.
Description
Technical field
The present invention relates to the preparation method of field of liquid crystal more particularly to a kind of thin film transistor (TFT) and use this method
The thin film transistor (TFT) of preparation.
Background technique
Liquid crystal display is currently used flat-panel monitor, wherein Thin Film Transistor-LCD
(ThinFilmTransistorLiquidCrystalDisplay, abbreviation TFT-LCD) is the main product in liquid crystal display.
High-resolution and low-power consumption are the development trends of current TFT-LCD, these all propose the manufacturing process of TFT-LCD higher
It is required that.It wherein, is one of development trend as data line material using the lower metal material of resistivity, for example, existing TFT-
LCD uses the metal laminated production data line of aluminium/molybdenum, to reduce power consumption, needs to use instead aluminium/neodymium (AlNd) lamination, fine aluminium (Al)
Or the lower material of the resistivity such as fine copper (Cu) makes data line.For example, the data in current large-sized a-Si liquid crystal display panel
Line is all made of fine copper, can effectively reduce RC retardation ratio because its resistance is low, meets large scale, high refresh rate, high-resolution requirement, and phase
For other metals, cost is lower.
Currently, the process flow for preparing thin film transistor (TFT) usual in the field is first to deposit a-Si layers and source-drain electrode metal
Layer, then using wet etching twice and twice dry etching (2W2D) alternately by the way of to source-drain electrode metal layer and a-Si layers
It performs etching.The technique has both merits and demerits.It the advantage is that, one of light shield can be saved；Its shortcoming is that this kind of side
Method can generate some adverse effects to source-drain electrode, and the line width homogeneity of the source-drain electrode data line after etching not can guarantee, while source
Data line drain there are zigzag defect, has broken string at filament.The reason of causing disadvantages mentioned above be, first time dry etching a-
Etching gas used in Si is chlorine (Cl2), then Cl residual is had in etching process, which can be to source-drain electrode data
Line carries out over etching, and then leads to finally formed source-drain electrode data line there are disadvantages mentioned above.
Fig. 1 is the photo figure of the data line of the thin film transistor (TFT) prepared using existing process flow, can from Fig. 1
Out, the line width of the source-drain electrode data line after etching is inhomogenous, and source-drain electrode data line has disconnected at filament there are zigzag defect
Line.
Summary of the invention
The technical problem to be solved by the invention is to provide a kind of preparation method of thin film transistor (TFT) and use party's legal system
Standby thin film transistor (TFT) can guarantee that the line width of the data line of the source-drain electrode data line layer for the film crystal to be formed is uniform, not have
There is jagged defect, and is not in broken string at filament.
To solve the above-mentioned problems, the present invention provides a kind of preparation method of thin film transistor (TFT), include the following steps:
Before carrying out dry etching to semiconductor layer or ohmic contact layer, to the patterned metal layer being located on the ohmic contact layer
Exposed side is passivated processing, and exposed side is made to cover a passivating film.
In one embodiment, the preparation method includes the following steps: to form grid on a substrate；In the substrate and
Grid forms a gate insulating layer；Semiconductor layer, ohmic contact layer and metal layer are sequentially formed on the gate insulating layer；?
A patterned photoresist layer is formed on the metal layer；First time wet process is carried out to the metal layer using the photoresist layer as exposure mask
Etching, forms patterned metal layer, and the patterned metal layer has the side of exposure；To the patterned metal layer
Exposed side is passivated processing, to form a passivating film on exposed side；The is carried out by exposure mask of the photoresist layer
Dry etching, removes part ohmic contact layer and semiconductor layer, the passivating film avoid the patterned metal layer
Exposed side is etched；Part photoresist layer is removed, to expose the metal layer of partial graphical；Using photoresist layer as exposure mask into
Second of wet etching of row removes the metal layer of partial graphical, forms source-drain electrode data line layer, wherein described patterned
Metal layer has surface to be exposed；Second of dry etching is carried out using photoresist layer as exposure mask, removes part ohmic contact layer,
Form active layer；Go removing photoresistance layer, exposure source-drain electrode data line layer；Interlayer insulating film and pixel electrode are deposited, it is brilliant to form film
Body pipe.
In one embodiment, the photoresist layer includes first area and second area, and the thickness of the first area is greater than
The thickness of the second area, after first time dry etching, the photoresist layer of second area is completely removed.
In one embodiment, the Passivation Treatment includes oxidation processes, and the passivating film is oxidation film.
In one embodiment, the time of the Passivation Treatment is 30~80 seconds.
In one embodiment, after carrying out second of wet etch step, carry out second dry etch step it
Before, processing is passivated to the side of the patterned metal layer exposure, to form a passivating film on exposed side.
The present invention also provides a kind of thin film transistor (TFT) adopted and prepared with the aforedescribed process, the thin film transistor (TFT) includes a base
Plate, setting grid on the substrate are arranged in the substrate and gate insulating layer on the grid, are arranged in the grid
Active layer on the insulating layer of pole, the ohmic contact layer being arranged on the active layer and gate insulating layer, are arranged in described ohm
Source-drain electrode data line layer on contact layer, the interlayer insulating film being arranged in source-drain electrode data line layer and across interlayer insulating film
The pixel electrode that via hole is connected with the drain electrode of source-drain electrode data line layer, at least partly exposed side of the source-drain electrode data line layer
It is covered with passivation layer.
In one embodiment, in the source-drain electrode data line layer in addition to the source electrode side opposite with draining, the source-drain electrode
The side of other exposures of data line layer is all covered with passivation layer.
In one embodiment, the side of the exposure of the source-drain electrode data line layer whole is covered with passivation layer.
In one embodiment, the width of the data line of the source-drain electrode data line layer is uniform, edge-smoothing.
It is an advantage of the current invention that forming passivation layer before carrying out dry etching in the side of metal layer exposure, avoiding
In and after dry etching process, remaining chlorine can guarantee the source for the film crystal to be formed to metal layer over etching
The line width of the data line for the data line layer that drains is uniform, without jagged defect, and is not in broken string at filament.
Detailed description of the invention
Fig. 1 is the step schematic diagram of an embodiment of the preparation method of thin film transistor (TFT) of the present invention；
Fig. 2A~Fig. 2 M is the process flow chart of an embodiment of the preparation method of thin film transistor (TFT) of the present invention；
Fig. 3 is the structural schematic diagram of an embodiment of thin film transistor (TFT) of the present invention；
Fig. 4 is the structural schematic diagram of another embodiment of thin film transistor (TFT) of the present invention.
Specific embodiment
Preparation method to thin film transistor (TFT) provided by the invention and the film using this method preparation with reference to the accompanying drawing
The specific embodiment of transistor elaborates.It should be noted that the thickness of each layer and shape be not anti-in attached drawing of the present invention
Actual proportions are reflected, purpose is schematically illustrate the content of present invention.
The preparation method of thin film transistor (TFT) of the present invention includes the following steps: to semiconductor layer or ohmic contact layer progress
Before dry etching, processing is passivated to the side for the patterned metal layer exposure being located on the ohmic contact layer, is made sudden and violent
The side of dew covers a passivating film.The passivation layer can prevent remaining chlorine in dry etching from infiltrating through in metal layer, avoid residual
The chlorine stayed can guarantee the line width of the data line of the source-drain electrode data line layer for the film crystal to be formed to metal layer over etching
It is uniform, it without jagged defect, and is not in broken string at filament.
The preparation method of thin film transistor (TFT) of the present invention is specifically described below.
Fig. 1 is the step schematic diagram of an embodiment of the preparation method of thin film transistor (TFT) of the present invention.Fig. 2A~Fig. 2 M is this
The process flow chart of one embodiment of the preparation method of invention thin film transistor (TFT).
Step S10 and Fig. 2A are please referred to, forms grid 201 on a substrate 200.The material of the substrate 200 include but
It is not limited to one of glass, quartz, PET, silicon, sapphire or tin indium oxide, as long as there is high transmittance to light.?
It includes but is not limited to deposit a metal layer on the substrate 200, graphically that the method for grid 201 is formed on the substrate 200
The metal layer forms the grid 201.The method that metal sputtering can be used in the metal layer is formed.The material of the grid
Including but not limited to Al, Mo, Cu, Ag.
Step S11 and Fig. 2 B is please referred to, forms a gate insulating layer 202, the gate insulating layer on the grid 201
Cover the substrate 200 and the grid 201.The material of gate insulating layer 202 includes but is not limited to SiNx or SiOx, mainly
It is prepared and is formed by chemical vapor deposition process (Chemicalvapordeposition, CVD).
Step S12 and Fig. 2 C is please referred to, sequentially forms semiconductor layer 203, Ohmic contact on the gate insulating layer 202
Layer 204 and metal layer 205.Wherein, in the present embodiment, the semiconductor layer 203 covers the gate insulating layer 202, described
Ohmic contact layer 204 covers the semiconductor layer 203, and the metal layer 205 covers the ohmic contact layer 204.It is described partly to lead
Body layer 203 includes but is not limited to amorphous silicon membrane.Ohmic contact layer 204 includes but is not limited to n+ amorphous silicon membrane.The metal
Layer 205 includes but is not limited to nickel, chromium, molybdenum, aluminium, titanium, copper, tungsten or their alloy.Wherein, on the gate insulating layer 202
The method for sequentially forming semiconductor layer 203, ohmic contact layer 204 and metal layer 205 includes but is not limited to physical vapour deposition (PVD) etc.
Method
Step S13 and Fig. 2 D is please referred to, forms a patterned photoresist layer 206 on the metal layer 205.It illustrates
The method for forming the photoresist layer 206: a layer photoresist material is coated on the metal layer 205；And use intermediate tone mask
Version (Half-tone Mask) is exposed the Other substrate materials and then develops, and then forms patterned photoresist layer
206.Wherein, in the present embodiment, the photoresist layer 206 includes first area 2061 and second area 2062, firstth area
The thickness in domain 2061 is greater than the thickness of the second area 2062.
Step S14 and Fig. 2 E is please referred to, is that exposure mask is wet for the first time to the metal layer 205 progress with the photoresist layer 206
Method etching, forms patterned metal layer 207.The wet etching refers to performing etching using etching liquid, the etching liquid
For the etching liquid of this field routine.In this step, metal layer 205 not by the metal that photoresist layer 206 blocks be etched liquid removal,
It is retained by the metal that photoresist layer 206 blocks, and then forms patterned metal layer 207.Since the photoresist layer 206 setting exists
207 top of patterned metal layer, so, the side A of patterned metal layer 207 is not covered by photoresist layer 206,
Side A is exposed to outer.
Step S15 and Fig. 2 F is please referred to, processing is passivated to the side A of the patterned exposure of metal layer 207, with
A passivating film 2071 is formed on exposed side A.The passivating film 2071 can protect the exposure of patterned metal layer 207
Side A, so that it is avoided the influence by subsequent technique.The Passivation Treatment includes but is not limited to oxidation processes, for example, using
Oxygen gas plasma (O2Plasma) processing method carries out oxidation processes to the side A of the patterned exposure of metal layer 207,
The passivating film 2071 is oxidation film.For example, using oxygen if the material of the patterned metal layer 207 is Cu
Plasma pre-processes the side A of the patterned exposure of metal layer 207, and an oxidation is formed on exposed side A
Film CuO.The flow velocity of oxygen plasma described further is 200~2000sccm, and the time of the Passivation Treatment is 30~80 seconds,
Such as 40 seconds, 50 seconds, 60 seconds or 70 seconds.
Step S16 and Fig. 2 G is please referred to, first time dry etching is carried out using photoresist layer 206 as exposure mask, removes part Europe
Nurse contact layer 204 and semiconductor layer 203.The dry etching refers to the technology that film etching is carried out with plasma, is
The prior art.In etching process, the part that the ohmic contact layer 204 and semiconductor layer 203 are not blocked is removed, and institute
The side surface A for stating patterned metal layer 207 is passivated the covering of film 2071, and remaining chlorine is to passivating film 2071 in etch process
It does not work, and then can be avoided the side A of the patterned metal layer 207 in the secondary etching technics by over etching, from
And makes shape and the line width of the patterned metal layer 207 etc. and be not affected.
Step S17 and Fig. 2 H is please referred to, part photoresist layer 206 is removed, to expose the metal layer 207 of partial graphical.
In this step, the photoresist layer of second area 2062 is removed, to expose the metal layer 207 of 2062 lower section of second area.
Step S18 and Fig. 2 I is please referred to, second of wet etching is carried out using photoresist layer as exposure mask, removes partial graphical
Metal layer 207, formed source-drain electrode data line layer 208.The wet etching refers to performing etching using etching liquid, the quarter
Lose the etching liquid that liquid is this field routine.In this step, patterned metal layer 207 is etched, and removes partial graphical
Metal layer 207 forms source-drain electrode data line layer 208, and exposes the ohmic contact layer 204 between source electrode and drain electrode.
Further, after step S18, the patterned metal layer being etched has new side to be exposed, in order to avoid
New side is etched in the etch step of step S19, further includes a pair of of institute before step S19 after step S17
The step of side that metal layer newly exposes is passivated processing is stated, to form a passivating film 2072 on exposed side, please be join
Read Fig. 2 J.The forming method of the passivating film is identical as the forming method of passivating film in step S15, repeats no more.
Step S19 and Fig. 2 K is please referred to, second of dry etching is carried out using photoresist layer as exposure mask, removal part ohm connects
Contact layer 204 forms active layer 209.After second of wet etching, the part photoresist of 206 first area 2061 of photoresist layer into
One step is removed, so that the photoresist thickness of the first area 2061 of photoresist layer 206 is further reduced.In this step, with thickness
Photoresist layer 206 after reduction carries out second of dry etching as exposure mask, and removal is located at the Ohmic contact between source electrode and drain electrode
Layer 204 and the semiconductor layer exposed in step S17, form active layer 209.After this step, the ohmic contact layer
204 there is only between source electrode and active layer and drain electrode and active layer, and ohmic contact layer 204 can permit active layer and source electrode and leakage
Pole Ohmic contact.
Step S20 and Fig. 2 L is please referred to, removing photoresistance layer 206, exposure source-drain electrode data line layer 208 are gone.Wherein, described in removal
The method of photoresist layer 206 can adopt with the conventional methods in the field, for example, removing the photoresist layer using stripper.
Step S21 and Fig. 2 M is please referred to, deposits interlayer insulating film 210 and pixel electrode 211, and then form film crystal
Pipe.Wherein, pixel electrode 211 is connect by passing through the via hole of interlayer insulating film 210 with the drain electrode of source-drain electrode data line layer 208.
The method for depositing interlayer insulating film 210 and pixel electrode 211 can use method well known to those skilled in the art, such as splash
It penetrates.
The preparation method of thin film transistor (TFT) of the present invention is formed before carrying out dry etching in the side of exposed metal layer
Passivation layer avoids during dry etching, and metal layer can guarantee the source-drain electrode for the film crystal to be formed by over etching
The line width of the data line of data line layer is uniform, without jagged defect, edge-smoothing, and is not in broken string at filament.
The present invention also provides a kind of thin film transistor (TFT)s adopted and prepared with the aforedescribed process.Fig. 3 is thin film transistor (TFT) of the present invention
An embodiment structural schematic diagram., Fig. 4 is the structural schematic diagram of another embodiment of thin film transistor (TFT) of the present invention.It is described thin
Film transistor includes a substrate 300, the grid 301 being arranged on the substrate 300, is arranged in the substrate 300 and the grid
Gate insulating layer 302 on pole 301, the active layer 303 being arranged on the gate insulating layer 302 and it is arranged in the active layer
303 and gate insulating layer 302 on ohmic contact layer 304, the source-drain electrode data line layer on the ohmic contact layer 304 is set
305, the interlayer insulating film 306 in source-drain electrode data line layer 305 and via hole and source-drain electrode across interlayer insulating film 306 are set
The connected pixel electrode 307 of the drain electrode of data line layer 305.The side of the exposure of source-drain electrode data line layer 305 is covered with passivation
Layer 3051.The passivation layer 3051 can be oxide layer.
In the present embodiment, referring to Fig. 3, the lateral surface of the source-drain electrode data line layer 304 exposure has passivation layer
3051, wherein source electrode and the opposite side that drains do not have passivation layer.And in other embodiments, referring to Fig. 4, the source and drain
The lateral surface of all exposures of pole data line layer 305 all has passivation layer 3051.Further, the number of source-drain electrode data line layer 305
It is uniform according to the width of line, there is no zigzag defect, edge-smoothing, and there is no broken strings.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (9)
1. a kind of preparation method of thin film transistor (TFT), which comprises the steps of:
It is patterned on the ohmic contact layer to being located at before carrying out dry etching to semiconductor layer or ohmic contact layer
The side of metal layer exposure is passivated processing, and exposed side is made to cover a passivating film.
2. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that the preparation method includes as follows
Step:
Grid is formed on a substrate；
A gate insulating layer is formed on the substrate and grid；
Semiconductor layer, ohmic contact layer and metal layer are sequentially formed on the gate insulating layer；
A patterned photoresist layer is formed on the metal layer；
First time wet etching is carried out to the metal layer using the photoresist layer as exposure mask, forms patterned metal layer, it is described
Patterned metal layer has the side of exposure；
Processing is passivated to the side of the patterned metal layer exposure, to form a passivating film on exposed side；
First time dry etching is carried out by exposure mask of the photoresist layer, removes part ohmic contact layer and semiconductor layer, it is described blunt
Changing film avoids the side of the exposure of the patterned metal layer from being etched；
Part photoresist layer is removed, to expose the metal layer of partial graphical；
Second of wet etching is carried out using photoresist layer as exposure mask, removes the metal layer of partial graphical, forms source-drain electrode data
Line layer, wherein the patterned metal layer has surface to be exposed；
Second of dry etching is carried out using photoresist layer as exposure mask, removes part ohmic contact layer, forms active layer；
Go removing photoresistance layer, exposure source-drain electrode data line layer；
Interlayer insulating film and pixel electrode are deposited, thin film transistor (TFT) is formed.
3. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that the photoresist layer includes the firstth area
Domain and second area, the thickness of the first area is greater than the thickness of the second area, after first time dry etching, the
The photoresist layer in two regions is completely removed.
4. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that the Passivation Treatment includes oxidation
Processing, the passivating film are oxidation film.
5. the preparation method of thin film transistor (TFT) according to claim 1, which is characterized in that carrying out second of wet etching
After step, before carrying out second of dry etch step, the side of the patterned metal layer exposure is passivated
Processing, to form a passivating film on exposed side.
6. a kind of thin film transistor (TFT) prepared using method described in Claims 1 to 5 any one, which is characterized in that described
The grid that thin film transistor (TFT) includes a substrate, setting grid on the substrate, is arranged on the substrate and the grid
Insulating layer, setting active layer on the gate insulating layer, the ohm being arranged on the active layer and gate insulating layer connect
Contact layer, the source-drain electrode data line layer being arranged on the ohmic contact layer, the layer insulation being arranged in source-drain electrode data line layer
The pixel electrode that layer and the via hole across interlayer insulating film are connected with the drain electrode of source-drain electrode data line layer, the source-drain electrode data line
At least partly exposed side of layer is covered with passivation layer.
7. thin film transistor (TFT) according to claim 6, which is characterized in that except source electrode and leakage in the source-drain electrode data line layer
Outside extremely opposite side, the side of other exposures of the source-drain electrode data line layer is all covered with passivation layer.
8. thin film transistor (TFT) according to claim 6, which is characterized in that the exposure of the source-drain electrode data line layer whole
Side is covered with passivation layer.
9. thin film transistor (TFT) according to claim 6, which is characterized in that the width of the data line of the source-drain electrode data line layer
Spend uniform, edge-smoothing.
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| CN111326082A (en) * | 2020-04-14 | 2020-06-23 | Tcl华星光电技术有限公司 | Backboard unit, manufacturing method thereof and display device |
| CN111725064A (en) * | 2020-06-05 | 2020-09-29 | Tcl华星光电技术有限公司 | Method for manufacturing metal electrode |
| CN113206144A (en) * | 2021-04-25 | 2021-08-03 | 北海惠科光电技术有限公司 | Preparation method of thin film transistor, thin film transistor and display panel |
| US11526079B2 (en) | 2020-04-14 | 2022-12-13 | Tcl China Star Optoelectronics Technology Co., Ltd. | Backplane unit and its manufacturing method and display device |
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