TWI423394B - Method of manufacturing a thin film transistor substrate - Google Patents

Description

Method of manufacturing a thin film transistor substrate Background of the invention

1. Scope of invention

The present invention relates to a method of fabricating a thin film transistor (TFT) substrate. More particularly, the present invention relates to a method for simplifying the manufacturing process of a TFT substrate.

2. Description of related skills

In general, a liquid crystal display (LCD) device includes a TFT substrate, a color filter substrate, and a liquid crystal layer. The TFT substrate includes TFTs and pixel electrodes. The color filter substrate includes a color filter and a common electrode. The liquid crystal layer is interposed between the TFT substrate and the color filter substrate.

The process of manufacturing a TFT substrate is performed by a yellow lithography method using a photomask. Recently, in order to simplify the manufacturing process, a four-mask thin plate process using a four-mask has been developed.

In order to etch a data metal layer using a four-mask thin plate process, a first etch phase for forming a data line and a second etch phase for etching a channel region are performed.

Since a wet etching process is applied to the first and second etching stages in a conventional four-mask thin plate process, the width of one line becomes larger to reduce the width of one of the channels, and a process dispersion.

In order to solve the problems as described above, a manufacturing process has been developed to use a wet etching process in the first etching stage, and a dry etching process in The second etching stage. However, the simultaneous use of a dry etching process and a wet etching process is complicated in the manufacturing process and increases manufacturing time.

Summary of invention

The present invention provides a method of manufacturing a TFT substrate which uses only a dry etching process and which simplifies the manufacturing process.

In a typical embodiment, a method of fabricating a TFT substrate includes successively forming a gate insulating film and an active layer on a substrate, the substrate having a gate wiring including a gate line and a gate. The gate is connected to the gate line formed thereon to form a data metal layer on the active layer, the data metal layer comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer The second metal layer and the third metal layer are successively formed to form a first photoresist pattern on the data metal layer, the first photoresist pattern having a thinner thickness in the channel region than in the adjacent region, by using The first photoresist pattern dry etches the third metal layer while dry etching the second metal layer and the first metal layer by using the first photoresist pattern to form a data line by dry etching using the first photoresist pattern The active layer removes a portion of the first photoresist pattern to form a second photoresist pattern, whereby the channel region is removed, and a channel region of the data metal layer is dry etched by using the second photoresist pattern to form a Connected A source line and a data source separate from the drain.

The first metal layer includes molybdenum, the second metal layer includes aluminum, and the third metal layer includes molybdenum.

Boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) can be used to simultaneously dry-etch the first metal layer and the second metal layer by using the first photoresist pattern. Boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) may be mixed at a ratio of about 1:1 to 1:5.

The channel region of the data metal layer can be dry etched by dry etching using the second photoresist pattern by dry etching the third metal layer using the second photoresist pattern, and simultaneously dry etching the second metal by using the second photoresist pattern a layer and a first metal layer.

After forming the source and drain, a TFT is formed by removing the ohmic contact layer in the channel region using the second photoresist pattern.

A protective film is formed on the substrate having the TFT formed thereon. A pixel electrode electrically connected to the drain is formed on the protective film.

In another embodiment, a method of fabricating a TFT substrate includes successively forming a gate insulating film and an active layer on a substrate, the substrate having a gate wiring including a gate line and a gate. The gate is connected to the gate line formed thereon to form a data metal layer on the active layer, the data metal layer comprises a first metal layer, a second metal layer and a third metal layer, the first metal layer The second metal layer and the third metal layer are successively disposed to form a photoresist pattern on the data metal layer. The photoresist pattern has a thinner thickness in the channel region than in the adjacent region, and the photoresist pattern is dry. Etching the third metal layer, dry etching the second metal layer by using the photoresist pattern, and simultaneously dry etching the active layer and the first metal layer by using the photoresist pattern to form a data line, and by using the photoresist pattern The channel region of the data metal layer is dry etched to form a source connected to the data line and a drain separated from the source.

The first metal layer includes molybdenum, the second metal layer includes aluminum, and the third metal The layer includes molybdenum.

Sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) can be used to simultaneously dry-etch the first metal layer and the active layer by using a photoresist pattern. Sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) may be mixed at a ratio of about 1:5 to 1:7.

In another embodiment, a method of fabricating a TFT substrate includes successively forming a gate insulating film and an active layer on a substrate, the substrate having a gate wiring including a gate line and a gate. The gate is connected to the gate line formed thereon to form a data metal layer on the active layer, the data metal layer comprising a first metal layer, a second metal layer and a third metal which are successively disposed a layer forming a photoresist pattern on the data metal layer, the photoresist pattern having a thinner thickness in the channel region than in the adjacent region, by dry etching the third metal layer using the photoresist pattern, by using a photoresist pattern dry Etching the second metal layer, dry etching the first metal layer by using the photoresist pattern, and dry etching the active layer by using the photoresist pattern, wherein at least two dry etching processes are simultaneously performed to dry etch the third metal layer, a second metal layer, and a first metal layer and an active layer. This method does not include a wet etch.

According to the above, a first etching step is performed using a dry etching process to form a data line, and a second etching step forms a channel. Therefore, problems caused by the wet etching process are solved, and the manufacturing process can be simplified.

Simple illustration

The above and other aspects, features, and advantages of the present invention will be apparent from the description of the accompanying claims. A plan view of a portion of a typical thin film transistor (TFT) substrate; and FIGS. 2 to 11 are cross-sectional views showing a typical manufacturing process of a typical TFT substrate of FIG. 1 taken along line I-I' of FIG. 12 through 15 are cross-sectional views illustrating a typical dry etching process for a metal layer of a data line in accordance with other exemplary embodiments of the present invention.

Detailed description of the preferred embodiment

The invention will be fully described below with reference to the accompanying drawings, which also illustrate embodiments of the invention. The invention may be embodied in a number of different forms, but the invention is not intended to be limited to the embodiments. Rather, these embodiments are provided merely to provide a more complete and comprehensive disclosure of the disclosure. In the drawings, the dimensions and relative dimensions of the various layers and regions are exaggerated for clarity.

It must be understood that when a component or layer is referred to as "on", "connected to", or "coupled" to another component or layer, it may be directly above the component or layer, or Other components or layers are inserted between the two. Conversely, when an element is referred to as "directly on", "directly connected to", or "directly coupled" to another element or layer, there are no intervening elements or layers. Like reference numerals refer to like elements. As used herein, "and/or" includes any and all combinations of one or more of the listed items.

It should be understood that, although the first, second, third, etc. are used herein to describe various elements, components, regions, layers and/or segments, these elements, components, regions, layers and/or segments should not be Words are limited. These words are just used The "first" element, component, region, layer or segment described below may also be referred to as "a". 2" elements, components, regions, layers or segments without departing from the teachings of the present invention.

Relevant words in space, such as "below", "above" and similar words, are used herein to describe the relevance of one element or feature to another element or feature. . It must be understood that the relevant terms of the space are intended to emphasize the different orientations in which the device is being used or operated, not just the orientation indicated in the schema. For example, if the device in the drawings is reversed, the element "under" another element or feature will be "above" the other element or feature, so the suffix "... The following can be referred to as "above" and "below". When the device is oriented in another orientation (rotated 90 degrees or toward other orientations), the spatially related description terms used herein will be interpreted differently.

The words used herein are for the purpose of describing particular embodiments, and are not intended to limit the invention. Unless otherwise specified, the singular terms "a" and "the" are used in the plural. It is to be understood that the words "including" and / or "including", when used in the specification, are specifically referring to the presence of the features, the whole, the steps, the operation, the components, the components and/or the group, but The existence or addition of one or more other features, integers, steps, operations, components, components and/or groups are not excluded.

Embodiments of the invention are described with reference to the schematic cross-section of a preferred embodiment of the invention. Therefore, there may be due to, for example, manufacturing methods and/or tolerances. The change in the shape of the figure. As such, the embodiments of the invention should not be construed as being limited to the particular shapes of the embodiments illustrated herein. For example, a region shown or described as being flat typically has coarse and/or non-linear features. In addition, the sharp angles shown can be rounded. Thus, the regions illustrated in the figures are shown in schematic and are not intended to

Unless otherwise stated, all terms (including technical and scientific terms) used herein have the same meaning meaning meaning It will be further understood that the terms defined in the general use of the dictionary should be interpreted as having the same meaning as in the context of the related art and the present specification, and should not be idealized or unless explicitly defined herein. Excessive formal interpretation.

The invention is described more fully hereinafter with reference to the accompanying drawings in which: FIG.

1 is a plan view illustrating a portion of a typical thin film transistor (TFT) substrate fabricated in accordance with an exemplary embodiment of the present invention. Figs. 2 to 11 are cross-sectional views showing a typical manufacturing process of a typical TFT substrate of Fig. 1 taken along line I-I' of Fig. 1.

Referring to FIGS. 1 and 2, after forming a gate metal layer on a substrate 110, the gate metal layer is patterned by a yellow lithography method using a first exposure mask to form a gate. Line 122 and a gate wiring 120 connected to gate 124 of gate line 122. For example, a gate metal layer is formed on the substrate 110 via a sputtering method.

For example, the substrate 110 includes a transparent insulating substrate such as a glass substrate.

For example, the gate wiring 120 includes aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), tungsten (W), copper (Cu) or silver (Ag), and alloys thereof. At least one of them. For example, the gate wiring 120 includes two or more metal layers having different physical properties from each other. The gate wiring 120 has an Al/Mo double-layer structure in which an aluminum (Al) layer and a molybdenum (Mo) layer overlap each other for low resistance. While a typical embodiment of gate wiring 120 has been described, another exemplary embodiment of gate wiring 120 can include other materials.

Referring to Fig. 1, the brake wire 122 extends in a substantially horizontal direction such as the first direction. Gate 124 is connected to gate line 122. Gate 124 forms the gate end of a TFT. The TFT is a switching device and is disposed on each pixel P.

Referring to FIG. 3, a gate insulating film 130 and an active layer 140 are successively formed on the substrate 110, and the substrate 110 includes a gate wiring 120 formed thereon. The gate insulating film 130 and the active layer 140 may be formed by a plasma assisted chemical vapor deposition (PECVD) method.

The gate insulating film 130 protects the gate wiring 120 and insulates it from a data metal layer 150, and the data metal layer 150 is formed on the gate insulating film 130 or the like. For example, the gate insulating film 130 includes tantalum nitride (SiNx) and tantalum oxide (SiOx). The gate insulating film 130 may be formed through a chemical vapor deposition (CVD) process such that the gate insulating film 130 has a certain thickness.

The active layer 140 includes a channel layer 142 and an ohmic contact layer 144. For example, channel layer 142 includes amorphous germanium (a-Si). For example, the ohmic contact layer 144 includes amorphous germanium (n ⁺ a-Si) having a high n-type dopant.

Then, a data metal film 150 including a first metal film 151, a second metal film 152, and a third metal film 153 which are successively disposed is formed on the active layer 140. For example, the first metal layer 151 includes molybdenum (Mo), the second metal layer 152 includes aluminum (Al), and the third metal layer 153 includes molybdenum (Mo). Therefore, the data metal layer 150 includes a Mo/Al/MO three-layer structure for low resistance. The data metal layer 150 is formed on the active layer 140 by a method such as sputtering.

Referring to FIG. 4, after a photoresist film is formed on the data metal layer 150, the photoresist film is patterned by a yellow lithography method using a second exposure mask such as a slit mask or a halftone mask. The first photoresist pattern 160 is formed. The first photoresist pattern 160 includes a positive photoresist having an exposed region that is removed by a developer.

The first photoresist pattern 160 has a relatively thin thickness in the channel region and a portion thereof adjacent to the channel region. For example, the first photoresist pattern 160 corresponds to a thickness of the channel region in the range of about 5000 Å to 8000 Å.

Referring to FIG. 5, the third metal layer 153 at the uppermost layer of the data metal layer 150 is dry etched by using the first photoresist pattern 160 as an etch mask.

Sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) are mainly used for dry etching a third metal layer 153 including molybdenum (Mo). In a typical embodiment, sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) are mixed at a ratio of from about 1:0.5 to 1:1.5.

Referring to FIGS. 1 and 6, the second metal layer 152 and the first metal layer 151 are borrowed. The dry etching is simultaneously performed by using the first photoresist pattern 160 as an etching mask.

Boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are mainly used as an etching gas for dry etching a second metal layer including aluminum (Al) and a first metal layer 151 including molybdenum (Mo). In a typical embodiment, boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are mixed at a ratio of about 1:1 to 1:5. When the proportion of boron trichloride (BCl ₃ ) in the gas mixture is relatively low, only the second metal layer 152 including aluminum (Al) is dry etched. However, when the proportion of boron trichloride (BCl ₃ ) in the gas mixture is increased, only the second metal layer 152 including aluminum (Al) and the first metal layer 151 including molybdenum (Mo) may be simultaneously dry etched. .

If the third metal layer 153, the second metal layer 152 and the first metal layer 151 are respectively dry etched, the active layer 140 is in the process of dry etching due to the inefficiency of the photoresist still disposed in the channel region. It is penetrated in the passage area. Therefore, by simultaneously dry etching the second metal layer 152 and the first metal layer 151, a manufacturing process can be simplified and the margin of the process is increased. In addition to this, the penetration of the channel area can be avoided or substantially reduced.

After the first metal layer 151 and the second metal layer 152 are dry etched, the third metal layer 153 is dry etched by using the first photoresist pattern 160, and one is used for the data line 155 and the source/drain The metal pattern 156 is still there. Referring to FIG. 1, data line 155 can extend along a direction that is substantially perpendicular to the second direction of gate line 122, for example.

Referring to FIG. 7, the active layer 140 is dry etched by using the first photoresist pattern 160 as an etch mask.

Outline of remaining active layer 140 and for data line 155 and source/drain The outline of the metal pattern 156 is substantially uniform by dry etching the data metal layer 150 and the active layer 140 using the same first photoresist pattern 160.

Referring to Fig. 8, the first photoresist pattern 160 is dry etched to a predetermined thickness by an ashing process using an oxygen plasma to form a second photoresist pattern 162 including an opening portion corresponding to the channel region. Therefore, the metal pattern 156 for the source/drain corresponding to the channel region is exposed.

Referring to FIGS. 1 and 9, the channel region for the source/drain metal pattern 156 is dry etched by using the second photoresist pattern 162 as an etch mask.

The dry etching process using the second photoresist pattern 162 may be substantially the same as the dry etching process using the first photoresist pattern 160 as described above. For example, in the dry etching process using the second photoresist pattern 162, the third metal layer 153 may be first dry etched, and then the second metal layer 152 and the first metal layer 151 are simultaneously dry etched. In another exemplary embodiment, during the dry etching process using the second photoresist pattern 162, the third metal layer 153, the second metal layer 152, and the first metal layer 151 may be dry etched separately.

When the channel region for the metal pattern 156 for the source/drain is etched by a dry etching process using the second photoresist pattern 162, a source 157 and a drain 158 are formed. Source 157 is connected to data line 155 to define the source terminal of the TFT. The drain 158 is separated from the source 157 to define the drain end of the TFT.

Next, the ohmic contact layer 144 of the channel region is dry etched by using the second photoresist pattern 162 as an etch mask. Therefore, the channel layer 142 It is exposed between the drain 158 and the source 157, and a channel 159 of the TFT is formed.

As described above, by dry etching all of the first, second, and third metal layers 151, 152, and 153, for example, in wet etching, the problem of an increase in the width of the line can be solved, and the manufacturing process can be simplify.

Next, the second photoresist pattern 162 on the data line 155, the source 157 and the drain 158 is removed. For example, the second photoresist pattern 162 can be removed via a removal process using a removal solution. Therefore, the manufacture of a TFT is completed.

Referring to FIGS. 1 and 10, a protective film 170 is formed on the substrate 110, and the substrate includes a TFT formed thereon. The protective film 170 protects the TFT and the data line 155. The protective film 170 includes an insulating material such as tantalum nitride (SiNx) or tantalum oxide (SiOx) such that the protective film 170 isolates the TFT and the data line 155 from a conductive layer which may be successively formed on the protective film 170. The protective film 170 can be formed by a CVD process and has a thickness in the range of about 500 Å to 2000 Å.

Next, the protective film 170 is patterned by a yellow lithography method using a third exposure mask, and a contact hole 172 exposing a portion of the drain 158 is formed.

Referring to FIGS. 1 and 11, after forming a transparent conductive film (not shown) on the protective film 170, the transparent conductive film is patterned by a yellow lithography method using a fourth exposure mask to form a pixel electrode. 180 is on each pixel P.

The pixel electrode 180 is electrically connected to the drain 158 via a contact hole 172 formed through the protective film 170. For example, the pixel electrode 180 includes indium zinc oxide (IZO) or indium tin oxide (ITO).

12 to 15 are diagrams illustrating other typical embodiments in accordance with the present invention A cross-sectional view of a typical dry etch process for a metal layer of a data line. The process before forming the metal layer for the data lines is substantially the same as the process as shown in Figures 2 through 4. Therefore, any further description about the above process will be omitted.

Referring to FIG. 12, the third metal layer 153 is dry etched by using a photoresist pattern 160 having a relatively thinner channel region and its area corresponding to, for example, adjacent to the channel region. thickness of.

For example, a fluorine (F)-based gas and chlorine gas (Cl ₂ ) are used as an etching gas for dry etching a third metal layer 153 including molybdenum (Mo). For example, sulfur hexafluoride (SF ₆ ) is used as a fluorine (F)-based gas. In a typical embodiment, sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) are mixed at a ratio of from about 1:0.5 to about 1:1.5.

Referring to Fig. 13, the second metal layer 152 is dry etched by using the photoresist pattern 160 as an etch mask.

Boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are mainly used as an etching gas for dry etching a second metal layer 152 including aluminum (Al). In a typical embodiment, boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are mixed at a ratio of from about 1:8 to about 1:12 only to dry etch the second metal layer 152.

Referring to FIG. 14, the first metal layer 151 and the active layer 140 are simultaneously dry etched by using the photoresist pattern 160 as an etch mask.

For example, a fluorine (F)-based gas and chlorine gas (Cl ₂ ) are used as a first dry metal layer 151 including molybdenum (Mo) and an active layer 140 including a-Si and n ⁺ a-Si. Etching gas. For example, sulfur hexafluoride (SF ₆ ) is used as a fluorine (F)-based gas. In a typical embodiment, sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) are mixed at a ratio of from about 1:5 to about 1:7. If the ratio of chlorine (Cl ₂ ) in the gas mixture is relatively low, only the first metal layer 151 including molybdenum (Mo) is dry etched. However, when the ratio of chlorine (Cl ₂ ) in the gas mixture is increased, the first metal layer 151 and the active layer 140 may be simultaneously dry etched.

As described above, by simultaneously dry etching the active layer 140 and the first metal layer 151, a manufacturing process can be simplified, and the margin of the process is increased. Thus, the penetration of the channel region can be avoided or substantially reduced.

In addition, when the first metal layer 151 and the active layer 140 are simultaneously dry etched, the region of the photoresist pattern 160 corresponding to a channel region is turned on, so that the third metal layer 153 is simultaneously dry etched in the channel region.

In order to prevent the photoresist from remaining on the channel region, an ashing process can be additionally performed to completely remove the remaining photoresist in the channel region.

Referring to Fig. 15, the first metal layer 151 and the second metal layer 152 corresponding to the channel region are dry etched by using the photoresist pattern 160 as an etch mask.

The dry etching process for dry etching the first metal layer 151 and the second metal layer 152 corresponding to the channel region is substantially the same as in FIG. For example, the first metal layer 151 and the second metal layer 152 are dry etched by a dry etching process. In another embodiment, the first metal layer 151 and the second metal layer 152 are separately dry etched.

Then, when the ohmic contact layer 144 of the channel region is dry etched, the portion of the channel layer 142 between the source 157 and the drain 158 is exposed to form a TFT. Channel.

The manufacturing process of the above process is then substantially the same as that of Figs. 10 and 11. Therefore, further description will be omitted.

According to the above, by the dry etching, a data metal layer having a Mo/Al/Mo three-layer structure for low resistance, a problem such as an increase in the width of the line which occurs during the wet etching can be solved, and The manufacturing process can be simplified.

Furthermore, by simultaneously dry etching an aluminum layer and a lower molybdenum layer or simultaneously dry etching a lower molybdenum layer and an active layer, a manufacturing process can be simplified and the margin of the process is increased. Therefore, the penetration of a channel region is avoided or substantially reduced.

Although a few exemplary embodiments of the invention have been described, it is understood that the invention is not to be construed as Separated from the skill and advantages of the present invention.

110‧‧‧Substrate

120‧‧‧ gate wiring

122‧‧‧ gate line

124‧‧‧ gate

130‧‧‧gate insulating film

140‧‧‧Active layer

142‧‧‧Channel layer

144‧‧‧Ohm contact layer

150‧‧‧Data Metal Film

151‧‧‧First metal film

152‧‧‧Second metal film

153‧‧‧ Third metal film

154‧‧‧Channel formation area

155‧‧‧data line

156‧‧‧Metal pattern

157‧‧‧ source

158‧‧‧汲polar

159‧‧‧ channel

160‧‧‧First photoresist pattern

162‧‧‧second photoresist pattern

170‧‧‧Protective film

172‧‧‧Contact hole

180‧‧‧pixel electrode

1 is a plan view illustrating a portion of a typical thin film transistor (TFT) substrate fabricated in accordance with an exemplary embodiment of the present invention; and FIGS. 2 through 11 are illustrated along line I-I' of FIG. A cross-sectional view of a typical fabrication process of a typical TFT substrate of FIG. 1; and FIGS. 12 to 15 are cross sections illustrating a typical dry etching process for a metal layer of a data line in accordance with other exemplary embodiments of the present invention. Figure.

122‧‧‧ gate line

124‧‧‧ gate

155‧‧‧data line

157‧‧‧ source

158‧‧‧汲polar

159‧‧‧ channel

172‧‧‧Contact hole

172‧‧‧Contact hole

Claims (19)

A method for manufacturing a thin film transistor substrate, the method comprising: successively forming a gate insulating film and an active layer on a substrate, the substrate having a gate wiring including a gate line and a gate, wherein the gate wiring a gate is connected to the gate line formed thereon; a data metal layer is formed on the active layer, the data metal layer includes a first metal layer, a second metal layer and a third layer which are successively disposed a metal layer; forming a first photoresist pattern on the data metal layer, the first photoresist pattern having a thinner thickness in a channel region than in an adjacent region; dry etching by using the first photoresist pattern The third metal layer is simultaneously dry etched by using the first photoresist pattern to form a data line; dry etching the activity by using the first photoresist pattern a layer; removing a portion of the first photoresist pattern to form a second photoresist pattern, whereby the channel region is removed; and dry etching the data metal layer by using the second photoresist pattern Channel area, forming a A source electrode connected to the data line and the source and a drain separated. The method of claim 1, wherein the first metal layer comprises molybdenum, the second metal layer comprises aluminum, and the third metal layer comprises molybdenum. The method of claim 2, wherein boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are used to simultaneously dry-etch the second metal layer by using the first photoresist pattern and The first metal layer. The method of claim 3, wherein boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are mixed at a ratio of from 1:1 to 1:5. The method of claim 1, wherein the channel region of the data metal layer is dry etched by using the second photoresist pattern comprises: dry etching the third metal by using the second photoresist pattern a layer; and simultaneously dry etching the second metal layer and the first metal layer by using the second photoresist pattern. The method of claim 1, wherein the active layer comprises a channel layer having an amorphous germanium, and an ohmic contact layer having an amorphous germanium doped with ions, and the method further comprises forming the source After the pole and the drain, the ohmic contact layer in the channel region is removed by using the second photoresist pattern to form a thin film transistor. The method of claim 6, further comprising: forming a protective film on the substrate having the thin film transistor formed thereon; and forming a pixel electrode on the protective film, the pixel electrode being electrically connected To the bungee. A method for manufacturing a thin film transistor substrate, the method comprising: successively forming a gate insulating film and an active layer on a substrate, the substrate having a gate wiring including a gate line and a gate, wherein the gate wiring a gate is connected to the gate line formed thereon; a data metal layer is formed on the active layer, the data metal layer includes a first metal layer, a second metal layer and a third layer which are successively disposed a metal layer; forming a photoresist pattern on the data metal layer, the pattern having a thinner thickness in a channel region than in an adjacent region; dry etching the third metal layer by using the photoresist pattern; Drying the second metal layer using the photoresist pattern; simultaneously dry etching the first metal layer and the active layer to form a data line by using the photoresist pattern; and using the photoresist pattern dry type Etching the channel region of the data metal layer to form a source connected to the data line and a drain separated from the source; wherein fluorine (F) gas and chlorine (Cl ₂ ) are used for Using the photoresist pattern simultaneously Dry etching the first metal layer and the active layer. The method of claim 8, wherein the first metal layer comprises molybdenum, the second metal layer comprises aluminum, and the third metal layer comprises molybdenum. The method of claim 8, wherein the fluorine (F)-based gas comprises sulfur hexafluoride (SF ₆ ) gas. The method of claim 10, wherein sulfur hexafluoride (SF ₆ ) and chlorine (Cl ₂ ) are mixed at a ratio of from 1:5 to 1:7. The method of claim 8, wherein in the process of simultaneously dry etching the first metal layer and the active layer by using the photoresist pattern, the third metal layer corresponds to the channel In the area of the area It is simultaneously dry etched. The method of claim 8, wherein the active layer comprises a channel layer having an amorphous germanium, and an ohmic contact layer having an amorphous germanium doped with ions, and the method further comprises forming the source After the pole and the drain, the ohmic contact layer in the channel region is removed by using the photoresist pattern to form a thin film transistor. The method of claim 13, further comprising: forming a protective film on the substrate having the thin film transistor; and forming a pixel electrode on the protective film, the pixel electrode being electrically connected to The bungee. A method for manufacturing a thin film transistor substrate, the method comprising: successively forming a gate insulating film and an active layer on a substrate, the substrate having a gate wiring including a gate line and a gate, wherein the gate wiring a gate is connected to the gate line formed thereon; a data metal layer is formed on the active layer, the data metal layer includes a first metal layer, a second metal layer and a third layer which are successively disposed a metal layer; forming a photoresist pattern on the data metal layer, the pattern having a thinner thickness in a channel region than in an adjacent region; dry etching the third metal layer by using the photoresist pattern; Drying the second metal layer using the photoresist pattern; dry etching the first metal layer by using the photoresist pattern; and dry etching the active layer by using the photoresist pattern; wherein the photoresist pattern is used by using the photoresist pattern Dry etching the at least two dry etching processes of the third metal layer, the second metal layer, the first metal layer and the active layer are simultaneously performed; wherein fluorine (F) gas and chlorine gas (Cl ₂ ) are used By using Photoresist pattern simultaneously dry-etching the first metal layer and the active layer. The method of claim 15, wherein the method does not include a wet etching process. The method of claim 15, wherein the first metal layer comprises molybdenum, the second metal layer comprises aluminum, and the third metal layer comprises molybdenum. The method of claim 15, wherein dry etching the second metal layer and dry etching the first metal layer are performed simultaneously. The method of claim 15, wherein dry etching the first metal layer and dry etching the active layer are performed simultaneously.