KR20070019454A - Method for fabricating thin film transistor substrate - Google Patents

Abstract

A method of manufacturing a thin film transistor substrate is provided. A method of manufacturing a thin film transistor substrate includes forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode on a substrate, forming a protective film on the thin film transistor, and forming a thin film transistor on the protective film. Forming a photoresist pattern defining a contact hole, wherein the photoresist pattern includes a first region positioned in the pixel region and a second region disposed in the pixel region, the second region being thinner than the first region, and contacting the protective layer using the photoresist pattern as an etching mask. Forming a hole, selectively removing the second region of the photoresist pattern, depositing a conductive oxide on the entire surface of the resultant, forming a pixel electrode electrically connected to the drain electrode through the contact hole; The photoresist pattern from which the second region is removed and the conductive acid present on the photoresist pattern A film comprising the step of removing by a photoresist stripper, and before and / or after the deposition of the conductive oxide comprising the step of heat-treating a second region of the removed photoresist pattern.

Thin film transistor, lift off method, liquid crystal display device

Description

Method for fabricating thin film transistor substrate

1 is a cross-sectional view of a thin film transistor substrate manufactured by a method according to embodiments of the present invention,

2 to 10a and 11 are cross-sectional views of the process step of the manufacturing method of the thin film transistor substrate according to an embodiment of the present invention,

10B is a SEM photograph of a photoresist pattern heat treated by the method according to an embodiment of the present invention.

12 and 13A are cross-sectional views of a manufacturing method of a method of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present invention.

13B is a SEM photograph of a photoresist pattern heat treated by a method according to another embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

10: insulating substrate 20: gate electrode

30: gate insulating film 44: semiconductor layer

55, 56: ohmic contact 65: source electrode

66: drain electrode 70: protective film

80: pixel electrode 100: photoresist pattern

The present invention relates to a method for manufacturing a thin film transistor substrate, and more particularly, to a method for manufacturing a thin film transistor substrate including a lift-off method.

In the modern society, the role of semiconductor integrated circuits, semiconductor devices, semiconductor devices, and the like is becoming increasingly important and widely used in various industrial fields. In particular, as the information society has accelerated, the electronic display field has been continuously developed, and a new function electronic display device capable of performing various functions required by the information society has been developed.

Conventionally, such a field of electronic display is a cathode ray tube (cathode ray tube). However, since cathode ray tubes have limitations in heavy weight, large volume, and high power consumption, flat panel display devices such as liquid crystal displays, organic electroluminescent displays, and plasma display panels are used. Has been spotlighted as a replacement for cathode ray tubes. Dual liquid crystal display devices have been applied to various fields such as monitors, notebook computers, televisions, mobile phones, etc. because they are thin and light.

The liquid crystal display device includes a thin film transistor substrate on which a thin film transistor array is formed, a color filter substrate including a color filter, and a liquid crystal layer interposed between the two substrates. The liquid crystal display implements an image by controlling the amount of transmitted light by rearranging liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrodes formed on the two substrates.

As a method of manufacturing the thin film transistor substrate, a mask process using a photoresist pattern is used to finely pattern a gate wiring or a data wiring. However, such a mask process increases the process time and increases the cost of the product, and thus, researches for reducing the number of processes using the mask in various ways have been continued.

As an example for reducing the number of mask processes, a process of patterning the semiconductor layer and the data wiring using one mask has been developed from a process of patterning the semiconductor layer with one mask and patterning the data wiring with another mask. Further, a process of patterning a passivation film and a pixel electrode using one mask has been developed from a process of patterning a passivation film on a thin film transistor with one mask and patterning the pixel electrode with another mask.

In the process of patterning the protective film and the pixel electrode with one mask, a lift-off method is usually used. In the lift-off method, a photoresist positioned under the region to be removed in the patterning step is removed using a photoresist stripper or the like to simultaneously remove a material present thereon. However, since the top portion of the photoresist is covered with a material which has not yet been removed, the side where the photoresist stripper comes into contact with the photoresist is only at the side. Therefore, the removal of the photoresist pattern takes a long time, and a defect occurs that leaves the photoresist residue even after the lift-off process is completed.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of manufacturing a thin film transistor substrate in which the process is simplified and the photoresist residual defect is improved.

Technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

According to one or more exemplary embodiments, a method of manufacturing a thin film transistor substrate includes forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode on the substrate; Forming a protective film on the passivation layer; a photoresist including a first region positioned in the thin film transistor region and a second region disposed in the pixel region and thinner than the first region, and defining a contact hole; Forming a pattern, forming the contact hole in the passivation layer using the photoresist pattern as an etching mask, selectively removing the second region of the photoresist pattern, and front surface of the resultant Depositing a conductive oxide on the substrate and electrically connecting the drain electrode to the drain electrode through the contact hole. Forming a pixel electrode to be connected; and removing the photoresist pattern from which the second region is removed and the conductive oxide film on the photoresist pattern using a photoresist stripper, wherein the conductive oxide is deposited. Heat-treating the photoresist pattern from which the second region has been removed before and / or after.

Specific details of other embodiments are included in the detailed description and the drawings.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on", it means that there is no intervening device or layer in the middle, and like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

The spatially relative terms " below ", " beneath ", " lower ", " above ", " upper " It may be used to easily describe the correlation of a device or components with other devices or components. Spatially relative terms are to be understood as including terms in different directions of the device in use or operation in addition to the directions shown in the figures. For example, when flipping a device shown in the figure, a device described as "below or beneath" of another device may be placed "above" of another device. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may be oriented in other directions as well, in which case spatially relative terms may be interpreted according to orientation.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements in the mentioned components, steps, operations and / or elements. Or does not exclude additions.

Embodiments described herein will be described with reference to cross-sectional views, which are ideal schematic diagrams of the invention. Accordingly, shapes of the exemplary views may be modified by manufacturing techniques and / or tolerances. Accordingly, the embodiments of the present invention are not limited to the specific forms shown, but also include variations in forms generated by the manufacturing process. Accordingly, the regions illustrated in the figures have schematic attributes, and the shape of the regions illustrated in the figures is intended to illustrate a particular form of region of the device, and is not intended to limit the scope of the invention.

Unless otherwise defined, all terms used in the present specification (including technical and scientific terms) may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

As used herein, the term "thin film transistor substrate" refers to a substrate including at least one thin film transistor, and does not exclude a case where another structure is interposed between the thin film transistor and the substrate or another structure is formed thereon. .

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment will be described with reference to the accompanying drawings. First, the structure of a thin film transistor substrate according to an embodiment of the present invention will be described. 1 is a cross-sectional view of a thin film transistor substrate manufactured by a method according to an embodiment of the present invention.

Referring to FIG. 1, a gate electrode 20 is formed on an insulating substrate 10 made of a transparent material such as glass. A gate line (not shown) is connected to the gate electrode 20 to transmit a gate signal applied from the outside. If necessary, a storage electrode (not shown) may be formed on the same layer as the gate electrode 20 or may be independently connected to the gate line. In the following description, the gate electrode 20, the gate line, the sustain electrode, and the like are collectively referred to as " gate wiring " for the sake of convenience.

The gate wiring 20 may be made of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), or an alloy thereof. It may also have a multilayer film structure including two conductive films (not shown) having different physical properties. In this case, one conductive film is formed of a refractory metal such as molybdenum, chromium, titanium, tantalum or an alloy thereof, and the other conductive film is aluminum, silver, copper or an alloy thereof having a low specific resistance so as to reduce signal delay or voltage drop. It can be formed as. In addition, a conductive film made of the above-mentioned refractory metal may be formed above and below the conductive film containing aluminum, silver, copper, or the like, but is not limited thereto. One example is molybdenum / aluminum / molybdenum triple layer.

A gate insulating film 30 made of silicon nitride (SiNx) or the like is formed on the gate wiring 20. The gate insulating layer 30 is formed on the entire surface of the substrate 10 to cover the gate wiring 20, and electrically insulates the gate wiring 20 from the upper semiconductor layer 44.

A semiconductor layer 44 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 30 of the gate wiring 20, and an n + hydrogenated amorphous doped with a high concentration of n-type impurities is formed on the semiconductor layer 44. Resistive contact layers 55 and 56 made of a material such as silicon are formed, respectively. The semiconductor layer 40 forms a channel portion of the thin film transistor, and the ohmic contacts 55 and 56 reduce contact resistance between the lower semiconductor layer 44 and the upper source electrode 65 and the drain electrode 66. Do it.

The source electrode 65 and the drain electrode 66 separated from the source electrode 65 are formed on the ohmic contact layers 55 and 56, respectively. The source electrode 65 is connected to a data line (not shown) that transmits a data signal, and the drain electrode 66 is connected to the pixel electrode 80. When the storage electrode is formed, a conductor pattern (not shown) facing the storage electrode may be formed on the same layer as the source electrode 65 and the drain electrode 66 as necessary. In the following, when the source electrode 65, the drain electrode 66, the data line, the conductor pattern, etc. are collectively referred to as "data wiring" for convenience, reference numerals of the source electrode 65 and the drain electrode 66 are referred to. As a reference, the reference sign of the data wiring is replaced. The ohmic contacts 55 and 56 under the data lines 65 and 66 are formed in substantially the same pattern as the data lines 65 and 66, except that the semiconductor 44 has a channel portion connected thereto. It has a pattern substantially the same as the data lines 65 and 66 and the ohmic contacts 55 and 56.

The data wirings 65 and 66 may be formed of aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), or the like as the gate wiring 20. It may be made of an alloy or the like, and may have a single film or a multilayer film structure.

The source electrode 55 and the drain electrode 56 form a thin film transistor together with the gate electrode 20 and the semiconductor layer 44.

Above the data lines 65 and 66, a passivation layer 70 is formed to cover the entire surface of the insulating substrate 10. The passivation layer 70 may be formed of, for example, an organic material having excellent planarization characteristics and having photosensitivity, a low dielectric constant insulating material, or silicon nitride (SiNx), which is an inorganic material. In the passivation layer 70, a contact hole 76 exposing the drain electrode is formed.

The pixel electrode 80, which is electrically connected to the drain electrode 66 and positioned in the pixel, is formed on the passivation layer 70 through the contact hole 76. The pixel electrode 80 to which the data voltage is applied generates an electric field together with the common electrode of the upper substrate to determine the arrangement of liquid crystal molecules of the liquid crystal layer between the pixel electrode 80 and the common electrode. The pixel electrode may be made of a conductive oxide such as ITO or IZO.

Hereinafter, a method of manufacturing the thin film transistor as described above will be described in detail with reference to FIGS. 2 to 11. 2 to 10A and 11 are cross-sectional views of steps in a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention.

Referring to FIG. 2, first, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), or the like may be sputtered on an insulating substrate made of glass or the like. A gate conductive layer made of tantalum (Ta) or an alloy thereof is deposited and patterned to form a gate wiring 20 including a gate electrode 20 and a gate line, a storage electrode, and the like.

Referring to FIG. 3, silicon nitride, hydrogenated amorphous silicon, and n + hydrogenated amorphous silicon doped with high concentration of n-type impurities on the substrate on which the gate wiring 20 is formed are, for example, chemical vapor deposition (Chemical Vapor Deposition); Continuous deposition using CVD to form the gate insulating film 30, the intrinsic amorphous silicon layer 40, and the doped amorphous silicon layer 50. At this time, the thickness of each layer is, for example, to have a range of 1,500 kPa to 5,000 kPa, 500 kPa to 2,000 kPa, 300 kPa to 600 kPa, respectively.

Subsequently, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), and tantalum (Ta) are formed on the doped amorphous silicon layer 50 using sputtering or the like. Or a data conductive layer 60 made of an alloy thereof.

Next, a photoresist film is applied on the data conductive layer 60 and soft baked at a temperature of about 100 ° C. Subsequently, the photoresist pattern 100 defining the data wiring and the semiconductor layer pattern is formed by exposure and development. In this case, the region 100a corresponding to the channel portion of the thin film transistor is thinner than the other region where the data line is formed. A mask including a slit pattern or a semipermeable membrane may be used to adjust the thickness of the photoresist pattern 100 as described above. Subsequently, the photoresist pattern 100 is cured by hard baking at a temperature of about 120 ° C.

Referring to FIG. 4, the data conductive layer 60 is etched using the photoresist pattern 100 as a mask. The etching of the data conductive layer 60 may be performed by wet etching using an etchant. In this step, a data line, a conductor pattern, and the like are formed, and the data conductive layer 64 which is not yet separated but connected to the channel portion of the thin film transistor is left.

Referring to FIG. 5, the doped amorphous silicon layer 50 and the amorphous silicon layer 40 are etched using the photoresist pattern 100 as a mask. The etching in this step is performed by dry etching using an etching gas, and may be continuously performed. At this time, the photoresist pattern 100 is also partially removed by the entire surface, and the height thereof is lowered. Since the photoresist pattern region 100a corresponding to the channel portion of the thin film transistor is thinner than other regions, all of the photoresist pattern 100 may be removed. Can be. For example, when the etch selectivity of the photoresist pattern 100 and the amorphous silicon layer 40 is the same, the amorphous silicon layer 40 and the doped amorphous silicon layer 50 are larger than the photoresist pattern region 100a corresponding to the channel portion. If the thickness is the same or smaller than the photoresist pattern region 100a may be completely removed in the etching process. If the photoresist pattern region 100a remains after the etching is completed, the photoresist pattern region 100a is completely removed through an etch back. In this step, the data conductive layer 64 of the channel portion is exposed, and the doped amorphous silicon layer 54 has the same pattern as the data conductive layer 64. In addition, the semiconductor layer 44 pattern is completed.

Referring to FIG. 6, the data conductive layer 64 present in the channel region is etched using the photoresist pattern 100 ′ as a mask. The etching may be performed by wet etching. As a result, the source electrode 65 and the drain electrode 66 are separated from each other, and the data wirings 65 and 66 patterns are completed.

Referring to FIG. 7, the doped amorphous silicon layer 50 in the channel region is etched using the photoresist pattern 100 ′ as a mask. The etching may be performed by dry etching. In this case, overetching is preferably performed to completely remove the doped amorphous silicon layer 50 in the channel region, and in this process, the lower semiconductor layer 44 may be partially etched to become thinner. As a result, the channel region is separated, and the ohmic contact layers 55 and 56 having substantially the same pattern as the upper data wirings 65 and 66 are completed.

Referring to FIG. 8, a protective film is formed by depositing silicon nitride or the like on the data lines 65 and 66. Next, a photoresist film is applied over the protective film and soft baked at a temperature of about 100 ° C. Subsequently, the photoresist pattern 110 defining a contact hole is formed by exposing and developing. In this case, the thickness of the pixel region is adjusted to be thinner than that of the thin film transistor region of the photoresist pattern 110. The thickness control of the photoresist pattern 110 may be performed by using a mask including a slit pattern or a semi-transmissive layer. Subsequently, the photoresist pattern 110 is cured by hard baking at a temperature of about 120 ° C.

9, the protective layer 70 is etched using the photoresist pattern 110 as a mask to form a contact hole 76 exposing the drain electrode 66. The etching here may be a dry etching. Next, the photoresist pattern 110 is etched back to remove the thin portion covering the pixel region. As a result, as shown in FIG. 9, the photoresist pattern 111 remains only on the thin film transistor. In this case, the thickness of the photoresist pattern 111 is also thinner than that of the photoresist pattern 110.

Referring to FIG. 10A, the photoresist pattern 111 is heat treated for about 10 to 30 minutes at a temperature higher than that of the hard bake, for example, 130 to 200 ° C. As a result, the photoresist pattern 111a is wrinkled as shown in FIG. 10A and the surface area is widened. 10B is a SEM photograph after the photoresist pattern 111 is heat-treated in the same manner as described above. Looking at the central surface of Figure 10b it can be seen that the photoresist pattern is wrinkled. The photoresist pattern in which the surface area is wrinkled while the surface is wrinkled in this manner facilitates the lift-off process described later.

Referring to FIG. 11, a conductive oxide such as ITO or IZO is deposited on the entire surface of the insulating substrate 10 on which the photoresist pattern 111a is formed. As a result, a pixel electrode 80 is formed by a conductive oxide such as ITO or IZO covering the pixel area and electrically connected to the drain electrode 66 through the contact hole 76. On the other hand, the conductive oxide film 81 still remains on the photoresist pattern 111a.

Subsequently, the photoresist pattern 111a and the conductive oxide film 81 present thereon are removed by a lift off process. That is, when the photoresist stripper including, for example, an amine, glycol, or the like is brought into contact with the photoresist pattern 111a by a spray method or a dip method, the photoresist stripper dissolves the photoresist pattern 111a to protect the protective film 70. The photoresist pattern 111a is peeled from the film. At this time, the conductive oxide film 81 present on the photoresist pattern 111a is also removed.

The removal rate of the photoresist pattern 111a and the conductive oxide film 81 thereon is related to the contact time and the contact area with the photoresist stripper. That is, the longer the contact time and the larger the contact area, the faster and complete the removal. However, since the photoresist pattern 111a is covered with the conductive oxide film 81, the contact area with the photoresist stripper is limited to the side portion, and the rate of melting therefrom is slow, so that the overall process time is long, and the photoresist pattern 111a is ) May not be completely removed and residual defects may occur.

In order to prevent such defects and to increase the removal rate of the photoresist pattern 111a, the surface area of the photoresist pattern is increased by the heat treatment process described with reference to FIG. 10A. Therefore, the side contact area with the photoresist stripper becomes wider, and the dissolution rate of the photoresist pattern 111a from the side surface is increased. In addition, since the contact area between the photoresist pattern 111a and the conductive oxide film 81 has a wider surface area, the photoresist pattern 111a may be dissolved more quickly as the strip proceeds inward. Therefore, the removal rate of the photoresist pattern 111a and the conductive oxide film 81 on the upper side becomes high.

As a result of the lift-off process as described above, a thin film transistor substrate free of residue of the photoresist pattern as shown in FIG. 1 may be manufactured.

Subsequently, a method of manufacturing a thin film transistor substrate according to another embodiment of the present invention will be described. 12 and 13A are cross-sectional views illustrating a process of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present invention.

In the method of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present invention, the protective layer 70 is etched using the photoresist pattern 110 as a mask to form a contact hole 76 exposing the drain electrode 66 and to form a photoresist pattern. The step of etching back the 110 to leave the photoresist pattern 111 only on the thin film transistor is the same as the embodiment of the present invention. Referring to FIG. 12, a conductive oxide such as ITO or IZO is deposited on the entire surface of the insulating substrate 10 on which the photoresist pattern 111 is formed. As a result, a pixel electrode 80 is formed by a conductive oxide such as ITO or IZO covering the pixel area and electrically connected to the drain electrode 66 through the contact hole 76. On the other hand, the conductive oxide film 81 still remains on the photoresist pattern 111.

Referring to FIG. 13A, the photoresist pattern 111 is then heat treated for about 10 to 30 minutes at a temperature higher than that of the hard bake, for example, 130 to 200 ° C. As a result, the photoresist pattern 111b is wrinkled as shown in FIG. 13B and the surface area is widened. 13B is an SEM photograph after heat treatment of the photoresist pattern in the same manner as described above. It can be seen that the photoresist pattern is severely wrinkled on the central surface of FIG. 13B. Referring back to FIG. 13A, not only the photoresist pattern 111b but also the conductive oxide film 81 on the upper side is corrugated by heat, and the degree of corrugation is different because the degree of expansion due to heat is different from that of the photoresist. Therefore, the conductive oxide film 81 is excited without being brought into close contact with the photoresist pattern 111b, and a cavity is formed therebetween.

Then, the lift off process is performed in the same manner as in the embodiment of the present invention. At this time, the photoresist stripper further increases the contact area with the photoresist pattern 111b in the cavity formed between the photoresist pattern 111b and the conductive oxide film 81, thereby removing the photoresist pattern 111b and the conductive oxide film 81. This rises further. Thus, a thin film transistor free from photoresist pattern residue as shown in FIG. 1 can be manufactured more quickly.

Meanwhile, in the embodiments of the present invention, the photoresist pattern is heat-treated before or after the deposition of the conductive oxide, but it is also possible to perform the heat treatment before and after the deposition of the conductive oxide, respectively. In this case, since the contact area with the photoresist stripper further increases by going through two heat treatment steps, it is possible to manufacture the thin film transistor from which residues are removed more reliably.

In addition, although the data wiring, the ohmic contact layer and the semiconductor layer are formed using one photoresist pattern having two or more different thicknesses in the embodiments of the present invention, they are formed by a lift process or the ohmic contact with the data wire. The same applies to the case where the layer and the semiconductor layer are formed using different masks, but are not limited thereto.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the present invention is not limited to the above embodiments but may be manufactured in various forms, and having ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

As described above, according to the method of manufacturing the thin film transistor substrate according to the exemplary embodiment of the present invention, since the photoresist and the conductive oxide film on the upper side are quickly lifted off, the manufacturing method is simple and the photoresist residual defect can be suppressed. Can be. Therefore, manufacturing efficiency can be improved.

Claims (6)

Forming a thin film transistor including a gate electrode, a semiconductor layer, a source electrode, and a drain electrode on the substrate; Forming a protective film on the thin film transistor; Forming a photoresist pattern on the passivation layer, the photoresist pattern including a first region positioned in the thin film transistor region and a second region positioned in a pixel region and having a thickness thinner than the first region, and defining a contact hole; Forming the contact hole in the passivation layer using the photoresist pattern as an etching mask; Selectively removing the second region of the photoresist pattern; Depositing a conductive oxide on the entire surface of the resultant to form a pixel electrode electrically connected to the drain electrode through the contact hole; And And removing the photoresist pattern from which the second region is removed and the conductive oxide film existing on the photoresist pattern using a photoresist stripper. Heat-treating the photoresist pattern from which the second region is removed before and / or after depositing the conductive oxide. According to claim 1, The forming of the photoresist pattern includes a baking step, and the heat treatment of the photoresist pattern from which the second region is removed is a heat treatment at a higher temperature than in the baking step. According to claim 1, The heat treatment of the photoresist pattern from which the second region is removed is performed at 130 to 200 ° C. The method of claim 3, wherein The heat treatment of the photoresist pattern from which the second region is removed is performed for 10 to 30 minutes. According to claim 1, The forming of the photoresist pattern includes exposing using a mask including a slit pattern or a semi-transmissive film. According to claim 1, Selectively removing the second region is performed by etching back to the thin film transistor substrate.

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