JP2007189120A - Tft substrate and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of reducing the number of manufacturing processes of a TFT substrate, shortening manufacture processing time, thereby largely reducing a manufacturing cost, and improving a manufacture yield, and the TFT substrate. <P>SOLUTION: The TFT substrate includes a gate wire and a gate insulation film, a first silicon layer and a second silicon layer, a source-drain wire and a source-drain electrode, and a pixel electrode electrically connected with the source-drain electrode and consisting of a transparent conductive film. At least one of the source-drain wire and the source-drain electrode is made of a metallic film on the transparent conductive film. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

    The present invention relates to a TFT substrate used in a liquid crystal display device and an organic EL light emitting device, and a method for manufacturing the same. Further, the present invention relates to a liquid crystal display device and an organic EL display device using the TFT substrate.

  LCDs (liquid crystal display devices) and organic EL display devices are widely used for reasons such as display performance and energy saving. In particular, display devices such as mobile phones, PDAs, personal computers, laptop computers, and televisions have become almost mainstream.

  In these display devices, a TFT (thin film transistor) substrate is generally used.

For example, a liquid crystal display device is configured to fill a display material such as liquid crystal between a TFT substrate and a counter substrate, and to selectively apply a voltage to the display material for each pixel. Here, the TFT substrate generally refers to a substrate on which a TFT (thin film transistor) made of a semiconductor thin film (also called a semiconductor film) or the like is disposed.

  Generally, this TFT substrate is often called a “TFT array substrate” because thin film transistors are arranged in an array. Therefore, the TFT substrate in the present invention includes this TFT array substrate.

  Note that a TFT array substrate used in a liquid crystal display device or the like is a substrate in which a set of TFTs and one pixel of a screen of a liquid crystal display device (referred to as 1UNIT) is arranged vertically and horizontally on a glass substrate. On the glass substrate, the gate wirings are arranged at regular intervals in the vertical direction, for example, and the source or drain wirings are arranged at regular intervals in the horizontal direction. On the other hand, the gate electrode, the source electrode, and the drain electrode are respectively provided in the UNIT constituting each pixel.

Conventional manufacturing method of TFT substrate As a manufacturing method of this TFT substrate, there are usually a five-mask process using five masks, a four-mask process in which the number of masks is reduced to four using halftone exposure, Etc. are known.

  However, since such a TFT substrate manufacturing method uses five or four masks, the manufacturing process tends to have a large number of steps. It is known that even in the case of a four-mask process, 35 steps (processes) and in the case of a five-mask process, a process exceeding 40 steps (processes) is required. As the number of processes increases as described above, the manufacturing yield may be reduced. In addition, since the number of processes is large, the process tends to be complicated, and the possibility of excessive manufacturing costs cannot be ignored.

A state of manufacturing a TFT substrate by a method using five conventional masks using five masks will be described. This manufacturing process will be described with reference to FIG.

  (1) First, metal Al is deposited on the glass substrate 210 by sputtering, and then the gate electrode 212 is provided by etching into a desired shape. A schematic cross-sectional view showing this state is shown in FIG. In order to set the shape of the gate electrode 212, a first mask is required.

  Thereafter, a gate insulating film 213 to be a SiN film (silicon nitride film) and an α-Si: H (i) film 214 are sequentially stacked.

(2) Next, after depositing a SiN film (silicon nitride film) as a channel protective layer, this SiN film is dry-etched into a desired shape using CH 2 _F gas to form a channel protective layer 215. This channel protective layer 215 is called an etch stopper. A schematic cross-sectional view after the channel protective layer 215 is formed is shown in FIG. In order to determine the shape of the channel protective layer 215, a second mask is necessary.

  (3) Next, an α-Si: H (i) film 216 is deposited. Further, a Cr / Al bilayer film is deposited thereon by vacuum evaporation or sputtering.

Thereafter, the Cr / Al bilayer film is etched to form a source electrode 217a and a drain electrode 217b having desired shapes. This etching is performed by photoetching using H ₃ PO ₄ —CH ₃ COOH—HNO ₃ for Al. Cr is performed by photoetching using a ceric ammonium nitrate aqueous solution.

Additionally, alpha-Si: H film (216 and 214) in combination of wet etching using a dry etching and hydrazine hydrate solution _{(NH 2 -NH 2 · H 2} 0) using CHF gas etching, a desired An α-Si: H (i) film 216 and an α-Si: H (i) film 214 having a shape are obtained.

  A schematic cross-sectional view showing the results of these etchings is shown in FIG. 10 (3). The shape of this etching (source electrode 217a, drain electrode 217b, α-Si: H (i) film 216 and α-Si: In order to define H (i) the pattern of the film 214, a third mask is necessary.

  (4) Next, before forming the transparent electrode 219, an interlayer insulating film 218 is deposited. Then, a through hole 218a for electrically connecting the source electrode 217a and the transparent electrode 219 described below is formed by etching. This formation requires a fourth mask. FIG. 10 (4) shows a schematic cross-sectional view showing a state where the through hole 218a is opened in the interlayer insulating film 218.

  (5) Next, an amorphous transparent conductive film mainly composed of indium oxide and zinc oxide is deposited on the upper surface on which the pattern of the source electrode 217a and the drain electrode 217b is formed by a sputtering method. This amorphous transparent conductive film is subjected to photo-etching using an aqueous solution of 20% by weight of oxalic acid as an etchant and patterned into a shape that is electrically connected to the source electrode 217a. Thereby, the transparent electrode 219 is formed. This is shown in FIG. 10 (5). In order to define the shape of the transparent electrode 219, a fifth mask is necessary. An example of a manufacturing process of a TFT substrate using five masks is as described above.

As an improvement to the manufacturing method prior art TFT substrate by three mask process, reduce the number of masks (e.g., three), it is considered to manufacture the TFT substrate in a simpler process. Based on this idea, various manufacturing methods using three masks have been proposed.

  However, many of the currently proposed three-mask processes are difficult to put into practical use. For example, the following Patent Document 1, Patent Document 2, Patent Document 3, Patent Document 4, Patent Document 5, Patent Document 6, and Patent Document 7 describe a manufacturing method using such a three-mask process. However, the three-mask process described in these documents must still be said to be a very complicated manufacturing process such as the addition of an anodizing step for the gate insulating film. Therefore, there is almost no merit to use the currently known three-mask process for practical use.

Japanese Patent Laid-Open No. 2004-317685 JP 2004-319655 A JP-A-2005-017669 JP 2005-019664 A JP 2005-049667 A JP 2005-106881 A JP 2005-108912 A

  As described above, a method capable of manufacturing a TFT substrate by a simpler process is strongly desired. In particular, if the number of masks is reduced, the number of processes is reduced, and a TFT substrate can be formed by a simpler process.

  The present invention has been made in view of the above problems, and a method for reducing the number of steps of manufacturing a TFT substrate, shortening the manufacturing processing time, thereby greatly reducing the manufacturing cost, and improving the manufacturing yield. And a TFT substrate thereof.

  (1) In order to solve the above problems, the present invention provides a gate wiring and a gate insulating film, a first silicon layer and a second silicon layer, a source / drain wiring, a source / drain electrode, and the source / drain electrode. And a pixel electrode made of a transparent conductive film, wherein at least one of the source / drain wiring or the source / drain electrode is a metal on the transparent conductive film. A TFT substrate comprising a film.

  With such a configuration, the shape of the transparent conductive film and the source / drain wiring or the source / drain electrode can be made common, and can be formed with a common mask. As a result, the number of masks to be used can be reduced.

  (2) Further, according to the present invention, the gate wiring and the gate insulating film, the first silicon layer and the second silicon layer, the source / drain wiring and the source / drain electrode, and the source / drain electrode electrically And a pixel electrode made of a transparent conductive film, wherein at least one of the source / drain wiring or the source / drain electrode is laminated in the order of the transparent conductive film and a metal film. A TFT substrate comprising the laminated film formed.

  With such a configuration, the shape of the transparent conductive film and the source / drain wiring or the source / drain electrode can be made common, and can be formed with a common mask. As a result, the number of masks to be used can be reduced.

  (3) Further, according to the present invention, the gate wiring and the gate insulating film, the first silicon layer and the second silicon layer, the source / drain wiring and the source / drain electrode, and the source / drain electrode electrically A TFT substrate having a pixel electrode made of a transparent conductive film, wherein at least one of the source / drain wiring or the source / drain electrode is a first metal film, the transparent conductive film, A TFT substrate comprising a laminated film laminated in the order of a second metal film.

  With such a configuration, the shape of the transparent conductive film and the source / drain wiring or the source / drain electrode can be made common, and can be formed with a common mask. As a result, the number of masks to be used can be reduced.

  (4) Further, the present invention is characterized in that a potential difference between the metal film or the first metal film and the transparent conductive film when placed in an alkaline electrolyte is 0.3 V or less. The TFT substrate according to any one of (1) to (3) above.

  With such a configuration, a battery reaction between the metal film or the first metal film and the transparent conductive film can be suppressed.

  (5) The present invention is also characterized in that the pixel electrode made of the transparent conductive film is resistant to the etchant for the first metal film and the second metal film (3) TFT substrate described in the above.

  With such a configuration, dissolution of the pixel electrode due to the etching process of the second metal film can be suppressed when the pixel electrode is formed.

  Here, the resistance of the pixel electrode means that the pixel electrode is “substantially not etched” or “the etching rate is extremely slow”. “Etching rate is remarkably slow” means the ratio between the etching rate of the second metal film and the etching rate of the transparent conductive film 24 as the pixel electrode, “etching rate of the second metal film” / “pixel electrode” The etching rate of the transparent conductive film 24 ”= 10 or more. Preferably, “the etching rate of the second metal film” / “the etching rate of the transparent conductive film 24 as the pixel electrode” = 15 or more, more preferably 20 or more.

  (6) In the present invention, the transparent conductive film contains indium oxide, zinc oxide, and tin oxide, and the total composition ratio of zinc oxide and tin oxide in the transparent conductive film is 20 wt. % Or more of the TFT substrate according to any one of the above (1) to (5).

  With such a configuration, the transparent conductive film can be etched with oxalic acid, but not etched with phosphoric acid / acetic acid / nitric acid based etching solution.

  (7) Further, in the present invention, the transparent conductive film contains indium oxide, zinc oxide, and tin oxide, and the composition ratio of zinc oxide in the transparent conductive film is 10 to 40 wt% of the total weight. The composition ratio of tin oxide in the film is 10 to 40 wt% of the total weight, in the TFT substrate according to any one of (1) to (5) above.

  With such a configuration, it is possible to maintain resistance to phosphoric acid / acetic acid / nitric acid based etching solution and to prevent increase in specific resistance.

  (8) Further, according to the present invention, a metal film, a gate insulating film, a first silicon layer, a second silicon layer, a first metal film, and a first resist are formed on a substrate. A step of forming a film in this order, a step of forming the first resist into a resist pattern 1a using a first mask using a halftone exposure technique, and a gate using the first resist Forming a wiring portion and a gate electrode portion; re-forming the first resist into a 1b resist pattern; and using the first resist of the 1b resist pattern to form the gate Removing the first metal film, the second silicon film, and the first silicon film on the wiring; and using the first resist of the resist pattern of 1b, the gate electrode portion And the second on the gate insulating film A step of forming a laminated region comprising a recon layer, the first silicon layer, and the first metal film, a step of insulating the gate wiring and the gate electrode, a transparent conductive film, A step of forming the second metal film and the second resist in this order, and a step of forming the second resist into the 2a resist pattern by the halftone exposure technique using the second mask. And removing the transparent conductive film, the second metal film, the second silicon layer, and the first silicon layer by using the second resist of the 2a resist pattern, Forming an electrode portion and a source / drain wiring portion, and further forming a channel portion on the stacked region; re-forming the second resist into a second resist pattern; Removing the source / drain wiring electrode film at the position of the pixel electrode portion using the second resist of the resist pattern, forming a pixel electrode portion, an insulating protective film, a third resist, , In this order, a step of forming the resist in a third resist pattern using a third mask, and the pixel electrode using the third resist of the third resist pattern A method of forming a TFT substrate according to any one of (1) to (5), further comprising: forming a portion, a source / drain wiring extraction portion, and a gate wiring extraction portion. is there.

  With such a configuration, a TFT substrate can be formed with three masks.

  (9) Further, in the present invention, the transparent conductive film contains indium oxide, zinc oxide, and tin oxide, and the total composition ratio of zinc oxide and tin oxide in the transparent conductive film is 20 wt. It is% or more, It is a manufacturing method of the TFT substrate as described in said (8) characterized by the above-mentioned.

  With such a configuration, the transparent conductive film can be etched with oxalic acid, but not etched with phosphoric acid / acetic acid / nitric acid based etching solution.

  (10) Further, in the present invention, the transparent conductive film contains indium oxide, zinc oxide, and tin oxide, and the composition ratio of zinc oxide in the transparent conductive film is 10 to 40 wt% of the total weight. The composition ratio of tin oxide in the film is 10 to 40 wt% of the total weight, and the manufacturing method of a TFT substrate according to (8) above, wherein

  With such a configuration, it is possible to maintain resistance to phosphoric acid / acetic acid / nitric acid based etching solution and to prevent increase in specific resistance.

  (11) By using the resist of the resist pattern of the 2a, removing the transparent conductive film, the source / drain wiring electrode film, the second silicon layer, and the first silicon layer, In the step of forming the transparent electrode portion and the source / drain wiring portion, and further forming the channel portion on the region, the removal is performed using dry etching using CHF gas and wet etching using hydrazine aqueous solution. The method for manufacturing a TFT substrate according to (8) above, which includes a selective etching process according to (8).

  By such treatment, the source / drain wiring, the source / drain electrode, and the pixel electrode can be formed simultaneously. As a result, the number of masks used for forming the channel portion can be reduced.

  As described above, according to the present invention, the number of masks used for manufacturing is reduced to three, so that the number of manufacturing steps can be reduced, the processing time can be shortened, and the manufacturing yield can be improved. Furthermore, according to the present invention, since the number of steps is reduced, it is expected that the manufacturing cost is reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  In this embodiment, a manufacturing operation of a TFT substrate will be described using three masks.

(A) Processing using the first mask
Metal Film First, a thin metal film having a thickness of 250 nm and 50 nm was formed on a light-transmitting glass substrate 10 by using a high frequency sputtering method in the order of Al and Ti. In this way, a metal film 12 composed of two layers of Al and Ti is formed on the glass substrate 10.

  In addition, Mo, Cr, etc. can be used as metals other than Ti. This metal film 12 becomes a gate wiring.

  By the way, it is conceivable to use a metal thin film such as Ag or Cu or an alloy thin film as the gate wiring. However, since it may be difficult to form an oxide film, it is preferable to use an Al system as in this embodiment.

  Al may be pure Al, but metals such as Nd, Ce, Mo, W, Nb may be added. Ce, W, Nb, etc. are also suitable for suppressing the battery reaction with the transparent conductive film. The addition amount can be selected as appropriate, but is preferably 0.1 to 2.0 wt%.

The gate insulating film and then the glow discharge CVD method to a thickness of 300nm is deposited a gate insulating film 14 is a silicon nitride (SiNx) film. As the discharge gas, a mixed gas of SiH ₄ —NH ₃ —N ₂ was used.

Next, an α-Si: H (i) film 16 is deposited to a thickness of 350 nm, following the first silicon layer and the second silicon layer . The α-Si: H (i) film 16 corresponds to a preferred example of the first silicon layer in the claims.

  At this time, as the discharge gas, the α-Si: H (i) film 16 uses a SiH4-N2-based mixed gas.

Subsequently, an α-Si: H (n) film 18 is deposited with a film thickness of 300 nm using a SiH ₄ —H ₂ —PH ₃ -based mixed gas. The α-Si: H (n) film 18 corresponds to a preferred example of the second silicon layer in the claims.

Barrier metal Next, a barrier metal 20 made of Ti is deposited thereon by a 50 nm-thickness sputtering method. This barrier metal 20 corresponds to a preferred example of the first metal film in the claims.

Resist Next, a first resist film 22 was formed.

  Six layers are provided on the glass substrate by the above processing. This is shown in FIG.

Halftone exposure Then , the first resist film 22 is formed in a desired resist pattern by halftone exposure. The state after the formation is shown in FIG. This pattern is referred to as a 1a resist pattern.

Formation Next, the barrier metal 20 is etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution. In this embodiment, a Ti film is used as the barrier metal 20, but a Mo film or a Cr film may be used.

Further, the α-Si: H films 16 and 18 are etched by using both dry etching using CHF gas and wet etching using hydrazine (NH ₂ —NH ₂ .H ₂ O) aqueous solution. As a result, the α-SiH (i) film 16 is formed in a desired pattern, and the α-Si: H (n) film 18 is also formed in a desired pattern.

  Subsequently, the gate insulating film 14 is etched by dry etching using CHF gas. The metal film 12 was etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution. As described above, the metal film 12 is a Ti / Al laminated film, but a Cr / Al laminated film or a Mo / Al laminated film may be used.

  In this way, the first etching is finished. A cross-sectional view showing the state after the first etching is finished is shown in FIG.

  Thereafter, the resist pattern of the first resist 22 is re-formed into a 1b resist pattern by ashing. A cross-sectional view showing the state after the re-formation is shown in FIG. In FIG. 2A, the first resist 22a and the first resist 22b existed. However, in FIG. 2B, it will be understood that only the first resist 22a remains.

  Thereafter, each layer on the metal film 12 which is a Ti / Al film which is a gate wiring is etched. Specifically, the barrier metal (Ti film) 20, the α-Si: H (n) film 18, and the α-Si: H (i) film 16 are etched by the above-described method.

  As a result, at the positions of the gate electrode and the gate insulating film, the α-Si: H (i) film 14, the α-Si: H (n) film 16, and the barrier metal (Ti film) 20 are formed thereon. A silicon island was formed.

  This silicon island corresponds to a preferred example of the “laminated region” in the claims.

  A cross-sectional view showing this state is shown in FIG. As shown in FIG. 2 (3), each layer remains at the position (left part in the figure) where the gate electrode and the gate insulating film are provided, forming a silicon island. On the other hand, at the position where the gate wiring is provided (right part in the figure), each layer of the upper machine is etched and the gate insulating film 14 is exposed.

  Next, the first resist 22a is removed. A sectional view showing this state is shown in FIG.

  Next, the metal film (Al / Ti laminated film) 12 as the gate wiring was insulated with a desired oxide insulating film by an anodic oxidation method. A sectional view showing this state is shown in FIG. As shown in this figure, the edge of the metal film 12 is insulated. A plan perspective view is shown in FIG. In these drawings, the ratio between the vertical direction and the horizontal direction is different from the actual one for easy understanding.

(B) Treatment using second mask Next, an indium oxide-zinc oxide-tin oxide transparent conductive film 24 was deposited as a transparent conductive film to a thickness of 120 nm by sputtering. Subsequently, Ti / Al / Ti films were formed to a thickness of 50 nm, 200 nm, and 150 nm, respectively, and source / drain wiring electrodes 26 were formed. Subsequently, a second resist film 28 was formed. This is shown in FIG. 4 (1).

  The source / drain wiring electrode 26 corresponds to a preferred example of the second metal film in the claims.

  Here, a desired 2a resist pattern was formed by halftone exposure using the second mask. This is shown in FIG. 4 (2). As shown in this figure, the second resists 28a, 28b, and 28c represent the 2a resist pattern.

The source / drain wiring electrode 26 and the transparent conductive film 24 in the portion other than the pixel electrode portion and the source / drain wiring portion were etched by the resist pattern 2a. The source / drain wiring electrode 26 is a Ti / Al / Ti laminated film as described above.

  Similarly, the source / drain wiring electrodes 26 of the silicon island other than the source / drain electrode portions, the transparent conductive film 24, the α-Si: H (n) film 18, and the α-Si: H (i ) The film 16 was etched. As a result, a channel portion was formed.

  These etchings were performed by the method described above. In particular, the transparent conductive film 24 was etched with an aqueous oxalic acid solution. The result of this etching is shown in the sectional view of FIG.

  Then, after that, the resist pattern was re-formed by ashing and re-formed into the 2b resist pattern. This is shown in FIG. 5 (2). As shown in this figure, it will be understood that the portion of the second resist 28b located in the pixel electrode portion has been removed and the second resist 28b has become smaller. As a result, the 2b resist pattern is formed on the second resist 28.

  Next, the source / drain wiring electrode 26 (Ti / Al / Ti film) located in the pixel electrode portion is etched using a phosphoric acid / acetic acid / nitric acid / water (9: 8: 1: 2 volume ratio) etching solution. Thereby, a transparent pixel electrode is formed. The state after this etching is shown in the sectional view of FIG. As shown in FIG. 5 (3), only the transparent conductive film 24 exists on the glass substrate 10 at the position of the pixel electrode.

  Finally, the result of removing the second resist 28 is shown in FIG. A plan perspective view of this state is shown in FIG. FIG. 5 (4) is a cross-sectional view in which the cross sections of the A-A ', B-B', and C-C 'portions in FIG. 6 are arranged.

(C) Treatment Using Third Mask Next, an insulating protective film 30 that is a silicon nitride (SiNx) film is deposited to a thickness of 300 nm by glow discharge CVD. As the discharge gas, a mixed gas of SiH ₄ —NH ₃ —N ₂ was used. Further, a resist was applied as a third resist. A cross-sectional view of this state is shown in FIG.

  Next, a third resist 32 was formed using a third mask to form a predetermined resist pattern. This is shown in the sectional view of FIG.

  Then, the transparent pixel electrode portion X, the source / drain wiring pad portion Y, and the gate wiring pad portion Z were exposed by dry etching using CHF gas (see FIG. 7 (3)).

  Finally, the third resist was removed to obtain a desired TFT substrate. This is shown in the sectional view of FIG. Further, this plan perspective view is shown in FIG. In FIG. 8, the insulating protective film 32 is indicated by hatching. As shown in FIG. 8, the portions other than the transparent pixel electrode portion X, the source / drain wiring pad portion Y, and the gate wiring pad portion Z are covered with an insulating protective film 32. FIG. 7 (4) is a cross-sectional view in which the cross sections of the D-D ', E-E', and F-F 'portions in FIG. 8 are arranged.

(D) Consideration about etching Here, the indium oxide-zinc oxide-tin oxide based transparent conductive film 24 used as the transparent conductive film 24 in this embodiment can be etched with oxalic acid, but phosphoric acid / acetic acid / nitric acid based etching. In the case of the liquid, the etching rate is slow and the etching is not performed.

  Moreover, this transparent conductive film can exhibit selective etching property by controlling the content of zinc oxide-tin oxide. The content of zinc oxide-tin oxide is required to be 20% by weight or more based on the total weight, and the remainder may be indium oxide. The zinc oxide content is preferably 10 to 40% by weight based on the total weight, and the tin oxide content is preferably 10 to 40% by weight based on the total weight. This is because if it is less than 10% by weight, the resistance to the phosphoric acid / acetic acid / nitric acid etching solution may be lost. On the other hand, if it is 40% by weight or more, the specific resistance may increase.

  Preferably, a configuration in which zinc oxide is 10 to 30% by weight, tin oxide is 15 to 30% by weight, and the remainder is indium oxide is suitable.

  By adopting such a composition, even when a laminated film is formed with Al in an alkaline electrolyte, the electrolytic corrosion reaction is suppressed, and thinning or disconnection of the Al wiring can be avoided. Al is preferably an alloy with Ce, W, Nb or the like rather than pure aluminum. In the alloy with these, the battery reaction is further suppressed.

  In the present embodiment, the transparent conductive film 24 having the above composition is adopted, but any material may be used as long as it does not cause a battery reaction with the metal film 12 in the alkaline electrolyte.

  When a certain kind of transparent conductive film is used, a battery reaction occurs when the metal film 12 made of Al and the transparent conductive film 24 are laminated (electrically connected) in an alkaline electrolyte. Al (metal film 12) may be dissolved.

  This is a reaction in which, when Al is dissolved, electrons are released and dissolved, and an oxide electrode (ITO or the like) is reduced by these electrons. Therefore, whether or not this reaction occurs is determined by measuring a standard electrode potential in an alkaline solution.

  For example, the standard electrode potentials of Al and Al—Nd alloys have been found to be −0.895 V and −0.848 V, respectively, when measured in a 2.83 wt% aqueous solution of tetramethylammonium hydroxide. . On the other hand, ITO is known to be -0.238V and IZO (registered trademark) is known to be -0.427V, and each difference acts as an electromotive force to dissolve Al.

  Therefore, if the standard electrode potential of the oxide transparent conductive film is measured, an indicator of the battery reaction can be obtained.

  An explanatory diagram of this measurement technique is shown in FIG. As shown in FIG. 9, in order to obtain the standard electrode potential for judging the presence or absence of the battery reaction, the electromotive force between the Ag / AgCl standard electrode 104 and the sample electrode 102 as the measurement object is measured. As shown in FIG. 9, an etching solution or a stripping solution is put in a predetermined container 100, and the temperature is maintained at 30 ° C. to 40 ° C. by hot water bathing. In order to maintain this temperature range, hot water of 30 ° C. to 40 ° C. is circulated through the wall of the container 100 as shown in the figure.

  Then, the sample electrode 102 and the Ag / AgCl standard electrode 104 are immersed in the container 100, and the electromotive force between them is measured with a potentiostat.

  According to the study by the inventors of the present application, it was found that if the difference between the standard electrode potential of the oxide transparent conductive film and the standard electrode potential of Al is 0.3 V or less, the battery reaction can be substantially suppressed. .

(E)
In this embodiment, an oxide conductive protective layer may be provided on the source / drain wiring in consideration of the durability of a desired TFT substrate. In that case, an oxide conductive film having a composition that does not cause a battery reaction may be selected for the purpose of suppressing the above-described battery reaction.

(F) Description of Selective Etching in this Embodiment In this embodiment, when etching the second metal film on the pixel electrode made of the transparent conductive film 24, the pixel is used for etching the second metal film. Resistance is required because the electrode does not dissolve.

  The second metal film means the source / drain wiring electrode 26 in the present embodiment as described above.

  Here, the term “tolerant” means that the pixel electrode is “substantially not etched” or “the etching rate is extremely slow”. The etching rate is remarkably slow that the ratio of the etching rate of the second metal film to the etching rate of the transparent conductive film 24 that is the pixel electrode, “etching rate of the second metal film” / “transparent conductivity that is the pixel electrode” The etching rate of the film 24 ”= 10 or more.

  Preferably, “the etching rate of the second metal film” / “the etching rate of the transparent conductive film 24 as the pixel electrode” = 15 or more, more preferably 20 or more.

  As a method for imparting such resistance, the material itself is soluble in an etching solution such as oxalic acid, but a mixed acid of phosphoric acid, acetic acid and nitric acid, which is an etching solution for the second metal film, cerium ammonium nitrate hydro A material resistant to an aqueous oxide solution may be selected.

  Examples of these materials include transparent conductive films made of indium oxide-zinc oxide-tin oxide. In this case, the composition may be selected as appropriate, but the total weight of zinc oxide and tin oxide may be 10 wt% or more and less than 50 wt%, preferably 15 to 50 wt% based on the total weight.

  Specifically, indium oxide 60 wt%-zinc oxide 20 wt%-tin oxide 20 wt%, indium oxide 80 wt%-zinc oxide 10 wt%-tin oxide 10 wt%, etc. are preferable when transparency, conductivity, and the like are added. .

  In addition, a technique of changing the etching resistance by changing the crystallinity can be used.

  For example, in an indium oxide-tin oxide system, an amorphous film is formed immediately after film formation, and crystallization is performed by performing crystallization treatment (heating treatment) before etching the upper second metal film. The film can be resistant to etching.

It is sectional drawing which shows the operation | movement centering on the process using a 1st mask. It is sectional drawing which shows the operation | movement centering on the process using a 1st mask. It is a top perspective view of Drawing 2 (5). It is sectional drawing which shows the operation | movement centering on the process using a 2nd mask. It is sectional drawing which shows the operation | movement centering on the process using a 2nd mask. It is a top perspective view of Drawing 4 (4). It is sectional drawing which shows the operation | movement centering on the process using a 3rd mask. It is a top perspective view of Drawing 7 (4). It is explanatory drawing of the measurement of a standard electrode potential. It is a cross-sectional schematic diagram for demonstrating the conventional method using five masks.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Glass substrate 12 Metal film 14 Gate insulating film 16 α-Si: H (i) film 18 α-Si: H (n) film 20 Barrier metal 22 First resist 24 Transparent conductive film 26 Source / drain wiring electrode 28 First 2 resist 30 insulating protective film 32 third resist 100 container 102 sample electrode 104 Ag / AgCl standard electrode 210 transparent substrate 212 gate electrode 213 gate insulating film 214 α-Si: H (i) film 215 channel protective layer 216 α- Si: H (n) film 217a Source electrode 217b Drain electrode 218 Interlayer insulating film 218a Through hole 219 Transparent electrode

Claims (11)

A gate wiring and a gate insulating film;
A first silicon layer and a second silicon layer;
Source / drain wiring and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode and made of a transparent conductive film;
A TFT substrate comprising:
A TFT substrate, wherein at least one of the source / drain wiring or the source / drain electrode is made of a metal film on the transparent conductive film. A gate wiring and a gate insulating film;
A first silicon layer and a second silicon layer;
Source / drain wiring and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode and made of a transparent conductive film;
A TFT substrate comprising:
A TFT substrate, wherein at least one of the source / drain wiring or the source / drain electrode is composed of a laminated film in which the transparent conductive film and a metal film are laminated in this order. A gate wiring and a gate insulating film;
A first silicon layer and a second silicon layer;
Source / drain wiring and source / drain electrodes;
A pixel electrode electrically connected to the source / drain electrode and made of a transparent conductive film;
A TFT substrate comprising:
At least one of the source / drain wiring or the source / drain electrode is composed of a laminated film in which a first metal film, the transparent conductive film, and a second metal film are laminated in this order. TFT substrate.   4. The potential difference between the metal film or the first metal film and the transparent conductive film when placed in an alkaline electrolyte is 0.3 V or less. The TFT substrate described.   4. The TFT substrate according to claim 3, wherein the pixel electrode made of the transparent conductive film is resistant to an etching solution for the first metal film and the second metal film. The transparent conductive film contains indium oxide, zinc oxide, tin oxide,
6. The TFT substrate according to claim 1, wherein the total composition ratio of zinc oxide and tin oxide in the transparent conductive film is 20 wt% or more based on the total weight. The transparent conductive film contains indium oxide, zinc oxide, tin oxide,
The composition ratio of zinc oxide in the transparent conductive film is 10 to 40 wt% of the total weight,
6. The TFT substrate according to claim 1, wherein the composition ratio of tin oxide in the transparent conductive film is 10 to 40 wt% of the total weight. Forming a metal film, a gate insulating film, a first silicon layer, a second silicon layer, a first metal film, and a first resist in this order on a substrate;
Using the first mask to form the first resist into the 1a resist pattern using a halftone exposure technique;
Forming a gate wiring portion and a gate electrode portion using the first resist;
After the first resist is re-formed into a 1b resist pattern, a first metal film on the gate wiring and a second silicon film are formed using the first resist of the 1b resist pattern. And removing the first silicon film;
Using the first resist of the 1b resist pattern, the gate electrode portion, the second silicon layer on the gate insulating film, the first silicon layer, and the first metal film And forming a laminated region consisting of:
Insulating the gate wiring and the gate electrode;
Forming a transparent conductive film, a second metal film, and a second resist in this order;
Forming the second resist into the 2a resist pattern by a halftone exposure technique using a second mask;
By using the second resist of the 2a resist pattern, the transparent conductive film, the second metal film, the second silicon layer, and the first silicon layer are removed to remove the transparent electrode portion. And forming a source / drain wiring portion, and further forming a channel portion on the stacked region;
After the second resist is re-formed into the 2b resist pattern, the source / drain wiring electrode film at the position of the pixel electrode portion is removed using the second resist of the 2b resist pattern. Forming a pixel electrode portion;
Forming an insulating protective film and a third resist in this order;
Forming the resist in a third resist pattern using a third mask;
Forming the pixel electrode portion, the source / drain wiring extraction portion, and the gate wiring extraction portion using the third resist of the third resist pattern;
The method for producing a TFT substrate according to claim 1, wherein: The transparent conductive film contains indium oxide, zinc oxide, tin oxide,
Total composition ratio of the zinc oxide and tin oxide in the transparent conductive film, manufacturing method for the TFT substrate of claim 8, characterized in that at 20 wt% or more based on the total weight. The transparent conductive film contains indium oxide, zinc oxide, tin oxide,
The composition ratio of zinc oxide in the transparent conductive film is 10 to 40 wt% of the total weight,
The method for producing a TFT substrate according to claim 8, wherein the composition ratio of tin oxide in the transparent conductive film is 10 to 40 wt% of the total weight. Using the resist of the 2a resist pattern, the transparent conductive film, the source / drain wiring electrode film, the second silicon layer, and the first silicon layer are removed to remove the transparent electrode portion and the source. In the step of forming the drain wiring portion and further forming the channel portion on the region,
9. The method of manufacturing a TFT substrate according to claim 8, wherein the removal includes a selective etching process using a combination of dry etching using CHF gas and wet etching using a hydrazine aqueous solution.