JP2007173489A - Tft substrate and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT substrate and a method of manufacturing the same, wherein the substrate is capable of being improved in quality, such as operating stability, and markedly being reduced in manufacturing cost by decreasing the number of manufacturing processes. <P>SOLUTION: The TFT substrate 1 is equipped with a glass substrate 10, a gate electrode 23 which is formed on the glass substrate 10 and whose upper surface is covered with a gate insulating film 30 and side is insulated with (an anodized part 26) by anodization, a gate wiring 24, an n-type oxide semiconductor layer 40 as a first oxide layer which is formed on the gate insulating film 30 on the gate electrode 23, and an oxide conductor layer 50 as a second oxide layer formed above the n-type oxide semiconductor layer 40, as one separated from it by a channel unit 46. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a TFT substrate and a manufacturing method of the TFT substrate, and in particular, includes an oxide semiconductor (n-type oxide semiconductor layer) as an active layer of a TFT (thin film transistor), and a second oxide layer (oxide conductor layer). ) Relates to a TFT substrate and a manufacturing method of the TFT substrate that can reduce the manufacturing process and reduce the manufacturing cost by serving as the source wiring, the drain wiring, the source electrode, the drain electrode, and the pixel electrode.

  LCDs (liquid crystal display devices) and organic EL display devices are widely used for reasons such as display performance and energy saving. In particular, it has become almost mainstream as a display device for mobile phones, PDAs (personal personal digital assistants), personal computers, laptop computers, televisions, and the like. In these display devices, a TFT substrate is generally used.

  For example, a liquid crystal display device is configured to fill a display material such as liquid crystal between a TFT substrate and a counter substrate, and to selectively apply a voltage to the display material for each pixel. Here, the TFT substrate refers to a substrate on which a TFT (thin film transistor) made of a semiconductor thin film (also referred to as a semiconductor film) is disposed. In general, a TFT substrate is also called a “TFT array substrate” because TFTs are arranged in an array.

  Note that in a TFT substrate used for a liquid crystal display device or the like, a set of TFTs and one pixel of a screen of the liquid crystal display device (this is called one unit) is arranged vertically and horizontally on a glass substrate. In the TFT substrate, gate wirings are arranged at regular intervals in the vertical direction on a glass substrate, and source wirings or drain wirings are arranged at regular intervals in the horizontal direction. Further, a gate electrode, a source electrode, and a drain electrode are provided in each of the units constituting each pixel.

<Conventional manufacturing method of TFT substrate>
As a manufacturing method of this TFT substrate, there are generally known a five-mask process using five masks, a four-mask process in which the number of masks is reduced to four using halftone exposure, and the like.
By the way, since such a TFT substrate manufacturing method uses five or four masks, the manufacturing process tends to have a large number of steps. For example, even in the case of a four-mask process, it is known that a process exceeding 35 steps (processes) and in the case of a five-mask process requires more than 40 steps (processes). If the number of processes increases in this way, the manufacturing yield may be reduced. In addition, if the number of processes is large, the process tends to be complicated, and the manufacturing cost may increase.

(Manufacturing method using five masks)
19A and 19B are schematic views for explaining a conventional TFT substrate manufacturing method. FIG. 19A is a cross-sectional view in which a gate electrode is formed, and FIG. 19B is a cross-sectional view in which an etch stopper is formed. (C) is a sectional view in which a source electrode and a drain electrode are formed, (d) is a sectional view in which an interlayer insulating film is formed, and (e) is a sectional view in which a transparent electrode is formed.
In FIG. 2A, a gate electrode 212 is formed on a glass substrate 210 using a first mask (not shown). That is, first, a metal (for example, Al) is deposited on the glass substrate 210 by sputtering, and after that, a resist is formed by photolithography using a first mask and etched into a desired shape. An electrode 212 is formed and the resist is ashed.

  Next, as shown in FIG. 2B, a gate insulating film 213 to be a SiN film (silicon nitride film) and an α-Si: H (i) film 214 are formed on the glass substrate 210 and the gate electrode 212. Laminate in order. Subsequently, a SiN film (silicon nitride film) serving as a channel protective layer is deposited, and a resist is formed by photolithography using a second mask (not shown), and the SiN film is formed using CHF gas. Dry etching is performed into a desired shape, an etch stopper 215 is formed, and the resist is ashed.

Next, as shown in FIG. 3C, an α-Si: H (n) film 216 is deposited on the α-Si: H (i) film 214 and the etch stopper 215, and further, Cr is formed thereon. A / Al bilayer film is deposited by vacuum evaporation or sputtering. Subsequently, a resist is formed by photolithography using a third mask (not shown), and the Cr / Al bilayer film is etched to form a source electrode 217a and a drain electrode 217b having desired shapes. This etching is performed by photoetching using H ₃ PO ₄ —CH ₃ COOH—HNO ₃ for Al, and by photoetching using an aqueous solution of ceric ammonium nitrate for Cr. Done. Further, the α-Si: H film (216 and 214) is etched by using both dry etching using CHF gas and wet etching using an aqueous hydrazine solution (NH ₂ NH ₂ .H ₂ 0). The α-Si: H (n) film 216 and the α-Si: H (i) film 214 having the following shapes are formed, and the resist is ashed.

  Next, as shown in FIG. 4D, before forming the transparent electrode 219, an interlayer insulating film 218 is deposited on the gate insulating film 213, the etch stopper 215, the source electrode 217a and the drain electrode 217b. Subsequently, a resist is formed by photolithography using a fourth mask (not shown), the interlayer insulating film 218 is etched, and the source electrode 217a is electrically connected to the transparent electrode 219 described below. Through-holes 218a are formed and the resist is ashed.

Next, as shown in FIG. 4E, the amorphous transparent conductive material mainly composed of indium oxide and zinc oxide is formed on the interlayer insulating film 218 in the region where the pattern of the source electrode 217a and the drain electrode 217b is formed. A film is deposited by sputtering. Subsequently, a resist is formed by photolithography using a fifth mask (not shown), photo-etching is performed using an amorphous transparent conductive film as an etchant with an aqueous solution of 4% by weight of oxalic acid, and the source electrode 217a. And patterning into a shape that is electrically connected to the resist, and ashing the resist. Thereby, the transparent electrode 219 is formed.
Thus, according to the manufacturing method of the TFT substrate according to this conventional example, five masks are required.

(Manufacturing method using three masks)
As a technique for improving the conventional technique, various techniques for manufacturing a TFT substrate by a method in which the number of masks is reduced (for example, from 5 to 3) and the manufacturing process is further reduced have been proposed. For example, Patent Documents 1 to 7 listed below describe a method for manufacturing a TFT substrate using three masks.
Japanese Patent Laid-Open No. 2004-317685 JP 2004-319655 A JP-A-2005-017669 JP 2005-019664 A JP 2005-049667 A JP 2005-106881 A JP 2005-108912 A

However, the method of manufacturing a TFT substrate using the three masks described in Patent Documents 1 to 7 has a problem that it is a very complicated manufacturing process and is a technique that is difficult to put into practical use. .
Further, in an actual production line, improvement of quality, that is, yield is extremely important, and there has been a demand for a practical technique that can improve quality and productivity.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and improves the quality of operation stability and the like, and reduces the number of manufacturing steps, thereby making it possible to significantly reduce the manufacturing cost. It aims at the proposal of the manufacturing method of a board | substrate.

In order to achieve the above object, a TFT substrate of the present invention includes a substrate, a gate electrode formed on the substrate, an upper surface covered with a gate insulating film, and an insulating surface formed by anodizing a side surface. A gate wiring; a first oxide layer formed on the gate insulating film on the gate electrode; and a second oxide formed on the first oxide layer and separated by a channel portion. And a layer.
In this case, at least the gate electrode / wiring thin film, the gate insulating film, and the first oxide layer are generally formed on the substrate, and impurities are mixed into the interface between the gate insulating film and the first oxide layer. Therefore, the quality of the first oxide layer serving as the active layer is improved, and the operational stability can be improved.

In the TFT substrate of the present invention, the second oxide layer also serves as at least a pixel electrode.
If it does in this way, the number of masks used at the time of manufacturing can be reduced, and a manufacturing process can be reduced, thereby improving production efficiency and reducing the cost of manufacturing. In addition, since the second oxide layer usually has a structure that also serves as a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode, the source wiring, the drain wiring, the source electrode, the drain electrode, and the pixel electrode are efficiently used. Can be manufactured well.

In the TFT substrate of the present invention, the upper side of the TFT substrate is covered with a protective insulating film, and the protective insulating film is located at a position corresponding to each pixel electrode, source / drain wiring pad, and gate wiring pad. The configuration has an opening.
In this case, since the upper portion of the first oxide layer in the channel portion is protected by the protective insulating film, it can operate stably over a long period of time. In addition, since the TFT substrate itself has a structure including a protective insulating film, a TFT substrate capable of easily manufacturing display means and light emitting means using liquid crystal or organic EL material can be provided.
The source / drain wiring pads refer to source wiring pads or drain wiring pads.

In the TFT substrate of the present invention, the first oxide layer is an n-type oxide semiconductor layer, and the second oxide layer is an oxide conductor layer.
As described above, by using an oxide semiconductor layer as an active layer of a TFT, the oxide semiconductor layer is stable even when a current flows, and is useful for an organic electroluminescence device that operates by current control. Further, the channel portion, the source electrode, and the drain electrode can be easily formed.
In addition, since the material of the first oxide layer and the second oxide layer is usually a metal oxide having semiconductor characteristics and a metal oxide having conductivity, the first oxide layer and the second oxide layer These oxide layers can also be referred to as a first metal oxide layer and a second metal oxide layer, respectively.

In the TFT substrate of the present invention, the first oxide layer is formed at a predetermined position corresponding to the channel portion.
In this case, since the first oxide layer is usually formed only at a predetermined position, it is possible to eliminate the concern that the gate wirings interfere with each other (crosstalk).

In the TFT substrate of the present invention, the energy gap of the second oxide layer is 3.0 eV or more.
In this way, by setting the energy gap to 3.0 eV or more, malfunction due to light can be prevented. In general, the energy gap may be 3.0 eV or more, preferably 3.2 eV or more, and more preferably 3.4 eV or more. Thus, by increasing the energy gap, malfunction due to light can be prevented more reliably.

The TFT substrate of the present invention has a configuration in which an auxiliary conductive layer is formed on at least one of a source wiring, a drain wiring, a source electrode, a drain electrode, and a pixel electrode.
If it does in this way, the electrical resistance of each wiring and an electrode can be reduced, reliability can be improved, and the fall of energy efficiency can be controlled.

In the TFT substrate of the present invention, the auxiliary conductive layer has a metal oxide layer for the auxiliary conductive layer for protecting the auxiliary conductive layer on the upper side.
In this way, corrosion of the auxiliary conductive layer can be prevented and durability can be improved.

In order to achieve the above object, a method for manufacturing a TFT substrate of the present invention includes a gate electrode and a thin film for wiring that becomes a gate wiring, a gate insulating film, a first oxide layer, A step of sequentially laminating the first resist, a step of forming the first resist into a predetermined shape by halftone exposure using the first halftone mask, the gate electrode / wiring thin film, and the gate Etching the insulating film and the first oxide layer to form the gate electrode and the gate wiring; re-forming the first resist into a predetermined shape; and the step above the gate wiring. A process of etching one oxide layer, a process of oxidizing the gate electrode and the gate wiring by anodic oxidation, and a process of sequentially stacking a second oxide layer, an auxiliary conductive layer, and a second resist. Using the second halftone mask, the step of forming the second resist into a predetermined shape by halftone exposure, and etching the auxiliary conductive layer and the second oxide layer to form a source electrode and a drain A step of forming an electrode, a source wiring, a drain wiring, a pixel electrode, and a channel portion; a step of re-forming the second resist into a predetermined shape; and an auxiliary conductive layer on the pixel electrode are selectively etched. A step of exposing the pixel electrode, a step of sequentially laminating a protective insulating film and a third resist, and a third mask to etch the protective insulating film to form source / drain wiring pads, A step of exposing the gate wiring pad and the pixel electrode.
As described above, the present invention is also effective as a method for manufacturing a TFT substrate. Usually, a gate electrode / wiring thin film, a gate insulating film, a first oxide layer, and a first resist are collectively formed on the substrate. Since no impurities are mixed into the interface between the gate insulating film and the first oxide layer, the quality of the first oxide layer serving as the active layer is improved, and the operational stability can be improved. In addition, the number of masks used in manufacturing can be reduced and the number of manufacturing processes can be reduced, so that the production efficiency can be improved and the manufacturing cost can be reduced. Furthermore, since the first oxide layer is usually formed only at a predetermined position (above the gate electrode), it is possible to eliminate the concern that the gate wirings interfere with each other (crosstalk). In addition, the electrical resistance of each wiring or electrode can be reduced by the auxiliary conductive layer, reliability can be improved, and reduction in energy efficiency can be suppressed. Furthermore, since the TFT substrate itself is provided with a protective insulating film, it is possible to provide a TFT substrate capable of easily manufacturing display means and light emitting means using liquid crystal or organic EL material.

In addition, the TFT substrate manufacturing method of the present invention includes a gate electrode and a thin film for wiring to be a gate wiring, a gate insulating film, a first oxide layer, a second oxide layer on the substrate, and A step of sequentially laminating the first resist, a step of forming the first resist into a predetermined shape by halftone exposure using the first halftone mask, the gate electrode / wiring thin film, and gate insulation Etching the film, the first oxide layer, and the second oxide layer to form the gate electrode and the gate wiring; re-forming the first resist into a predetermined shape; and the gate A step of etching the second oxide layer and the first oxide layer above the wiring, a step of oxidizing the gate electrode and the gate wiring by anodic oxidation, a third oxide layer, an auxiliary conductive layer, and The second A step of sequentially stacking the strike, a step of forming the second resist in a predetermined shape by halftone exposure using a second halftone mask, the auxiliary conductive layer, the third oxide layer, and the second Etching the two oxide layers to form a source electrode, a drain electrode, a source wiring, a drain wiring and a pixel electrode, and a channel part; and a process of re-forming the second resist into a predetermined shape; The step of selectively etching the auxiliary conductive layer on the pixel electrode to expose the pixel electrode, the step of sequentially stacking the protective insulating film and the third resist, and the protection using the third mask And a step of exposing the source / drain wiring pad, the gate wiring pad and the pixel electrode by etching the insulating film.
In this way, since impurities are not mixed into the interface between the lower surface and the upper surface of the first oxide layer, the quality of the first oxide layer serving as the active layer is further improved, and durability and operational stability are further improved. Can be made.

Moreover, the manufacturing method of the TFT substrate of the present invention is a method in which a metal oxide layer for an auxiliary conductive layer for protecting the auxiliary conductive layer is formed on the auxiliary conductive layer.
In this way, corrosion of the auxiliary conductive layer can be prevented and durability can be improved.

  According to the TFT substrate and the manufacturing method of the TFT substrate in the present invention, since impurities are not mixed in the interface between the gate insulating film and the first oxide layer, the quality of the first oxide layer serving as the active layer is improved, Operational stability can be improved. In addition, the number of masks used in manufacturing can be reduced and the number of manufacturing processes can be reduced, so that the production efficiency can be improved and the manufacturing cost can be reduced. Furthermore, since the first oxide layer is usually formed only at a predetermined position (above the gate electrode), it is possible to eliminate the concern that the gate wirings interfere with each other (crosstalk).

[First Embodiment in Manufacturing Method of TFT Substrate]
FIG. 1 is a schematic flowchart for explaining a method of manufacturing a TFT substrate according to the first embodiment of the present invention.
In the figure, first, a gate electrode / wiring thin film 20, a gate insulating film 30, an n-type oxide semiconductor layer 40 as a first oxide layer, and a first resist 41 are sequentially laminated on a substrate 10 ( Step S 1) Next, the gate electrode 23 and the gate wiring 24 are formed using the first halftone mask 42 (Step S 2). Subsequently, the first resist 41 is re-formed, and the upper part of the gate wiring 24 is formed. The n-type oxide semiconductor layer 40 is etched, and the gate electrode 23 and the gate wiring 24 are oxidized by anodic oxidation (step S3).
Next, processing using the first halftone mask 42 will be described with reference to the drawings.

(Process using the first halftone mask)
FIG. 2 is a schematic view for explaining the process using the first halftone mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and (a) shows the glass substrate before the process. Cross-sectional view, (b) is a gate electrode / wiring thin film formation / gate insulating film formation / n-type oxide semiconductor layer formation / first resist-coated cross-section view, and (c) is a halftone exposure. / Developed cross-sectional view.
In FIG. 1A, first, a translucent glass substrate 10 is prepared.
In addition, the plate-shaped member used as the base material of TFT substrate 1 is not limited to the said glass substrate 10, For example, resin-made plate-shaped members, a sheet-like member, etc. may be sufficient.

Next, as shown in FIG. 2B, on the glass substrate 10, the gate electrode / wiring thin film 20, the gate insulating film 30, and the first oxide layer n are formed as the gate electrode 23 and the gate wiring 24. The type oxide semiconductor layer 40 and the first resist 41 are sequentially stacked (step S1).
That is, Al (aluminum) -Nd (neodymium) is laminated on the glass substrate 10 by using a high frequency sputtering method, and a gate electrode / wiring thin film (a gate electrode and a gate wiring) made of a metal thin film having a film thickness of about 300 nm. Thin film) 20 is formed.

Nd mixed with Al is mixed to suppress generation of hillocks (hemispherical protrusions). The metal that suppresses hillocks is not limited to Nd, and may be, for example, a lanthanoid element such as Ce (cerium) or a high melting point metal such as W (tungsten), Nb (niobium), or Mo (molybdenum). .
For the purpose of reducing the contact resistance in the gate wiring pad 25, for example, Ni (nickel), W, Mo, Nb, Ti (titanium), Cr (chromium), etc. can be used instead of Al. In general, Al is used when it is low enough not to be concerned. In addition, after forming the gate electrode 23, the resistance value of Al may be lowered by heat treatment.

Subsequently, a gate insulating film 30 that is a silicon nitride (for example, SiN _X film) is deposited on the gate electrode / wiring thin film 20 by a glow discharge CVD (chemical vapor deposition) method to a thickness of about 300 nm. At this time, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as a discharge gas.
Note that a film such as SiN _X O _Y or an oxide insulating film can be used as the gate insulating film 30. As the oxide insulating film, Ai ₂ O ₃ , Y ₂ O ₃ , Hf ₂ O ₃ , an oxide of a lanthanoid element, TiO ₂ , a mixture thereof, a laminated film, a superlattice thin film, or the like can be used. The gate insulating film 30 is advantageously a thin film having high insulating properties and high dielectric constant.

Next, an indium oxide-zinc oxide-gallium oxide (In ₂ O ₃ : ZnO: Ga ₂ O ₃ = about 90: 3: 7 wt%) target is used as the first oxide layer on the gate insulating film 30. Then, an n-type film having a thickness of about 100 nm is formed by a high-frequency sputtering method under a condition that oxygen is about 10%, argon is about 90%, and the substrate temperature does not exceed about 200 ° C. (that is, the n-type oxide semiconductor layer 40 is not crystallized). An oxide semiconductor layer (active layer) 40 is formed. Subsequently, a first resist 41 is stacked on the n-type oxide semiconductor layer 40 (step S1).
In addition, the material of the n-type oxide semiconductor layer 40 is not limited to the indium oxide-zinc oxide-gallium oxide. For example, any metal oxide having a carrier concentration of less than 10 ⁺¹⁶ / cm ³ can be used. It is. The mobility of the metal oxide is 0.1 cm ² / V · sec or more, preferably 1 cm ² / V · sec or more, more preferably 10 cm ² / V · sec or more.

Further, the n-type oxide semiconductor layer 40 is preferably crystallized by heating before the oxide conductor layer 50 is selectively etched so as to be resistant to an aqueous oxalic acid solution or a mixed acid composed of phosphoric acid, acetic acid and nitric acid. . For example, when the material of the n-type oxide semiconductor layer 40 is indium oxide-zinc oxide, the content of zinc oxide may be controlled to about 1 to 6% by weight. In this case, when heated to lower the resistance value of Al such as the gate electrode / wiring thin film 20, it crystallizes and becomes resistant to an aqueous oxalic acid solution or a mixed acid composed of phosphoric acid, acetic acid and nitric acid. Furthermore, the content of zinc oxide is preferably about 2 to 5% by weight. The material mixed with indium oxide is not limited to the above zinc oxide, and for example, an insulating metal oxide can be mixed.
The n-type oxide semiconductor layer 40 is not limited to indium oxide-zinc oxide. That is, if it is a metal oxide film that becomes resistant to an aqueous oxalic acid solution or a mixed acid composed of phosphoric acid, acetic acid and nitric acid when crystallized by heating, and has semiconductor characteristics, it is an n-type oxide. It can be used as the semiconductor layer 40.

  Next, as shown in FIG. 3C, the first resist 41 is formed into a predetermined shape by the first halftone mask 42 and halftone exposure (step S2). The first resist 41 covers the gate electrode 23 and the gate wiring 24, and the halftone mask portion 421 forms a portion covering the gate wiring 24 in a thinner shape than the other portions.

FIG. 3 is a schematic view for explaining a process using a first halftone mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention. FIG. 1 shows a cross-sectional view where the resist is re-formed, (b) shows a cross-sectional view after the second etching / first resist is peeled off, and (c) shows a cross-sectional view where the gate wiring / electrode is anodized. .
In FIG. 6A, first, as the first etching, the first resist 41 (see FIG. 2C) is used to etch the n-type oxide semiconductor layer 40 with an aqueous oxalic acid solution. The gate insulating film 30 is etched by a reactive ion etching method (dry etching) using CHF (CF ₄ , CHF ₃ gas, etc.), followed by a mixed acid composed of phosphoric acid, acetic acid, and nitric acid, to form a gate electrode / wiring thin film 20 is etched. The gate electrode 23 and the gate wiring 24 are formed by the etching (step S2). Subsequently, the resist on the gate wiring 24 that is thinly formed by halftone exposure in the first resist 41 is ashed to re-form the first resist 41 (step S3 in FIG. 1).

  Next, as shown in FIG. 4B, as the second etching, the re-formed first resist 41 and oxalic acid aqueous solution are used to etch the n-type oxide semiconductor layer 40 above the gate wiring 24. Subsequently, the re-formed first resist 41 is ashed.

Next, as shown in FIG. 3C, the gate electrode 23 and the gate wiring 24 are anodized (step S3). That is, the gate electrode 23 and the gate wiring 24 whose upper surface is covered with the gate insulating film 30 and whose side surfaces are exposed in FIG. 4B are oxidized to the predetermined depth on the side surfaces, thereby forming an anodized portion 26 having insulating properties. Is done. Thereby, the gate electrode 23 and the gate wiring 24 are insulated from the oxide conductor layer 50. Since the gate electrode 23 and the gate wiring 24 are formed with the anodized portion 26, the lateral width is reduced accordingly (see FIG. 5C). The gate electrode 23 shown in FIG. 3C shows the AA cross section in FIG. 4, and the gate wiring 24 shows the BB cross section.
In the present embodiment, the gate electrode / wiring thin film 20, the gate insulating film 30, the n-type oxide semiconductor layer 40 as the first oxide layer, and the first resist 41 are collectively formed on the substrate 10. Therefore, impurities are not mixed into the interface between the gate insulating film 30 and the n-type oxide semiconductor layer 40, the quality of the n-type oxide semiconductor layer 40 serving as an active layer is improved, and the operational stability of the TFT substrate 1 is improved. be able to.

Next, as shown in FIG. 1, an oxide conductor layer 50 as a second oxide layer, a metal layer 60 as an auxiliary conductive layer, and a second resist 61 are sequentially stacked (step S4). The second halftone mask 62 is used to form the source electrode 53, the drain electrode 54, the source wiring 55, the drain wiring 56 and the pixel electrode 57, and the channel portion 46 (step S5). The resist 61 is re-formed, and the metal layer 60 on the pixel electrode 57 is selectively etched to expose the pixel electrode 57 (step S6).
Next, processing using the second halftone mask 62 will be described with reference to the drawings.

(Process using second halftone mask)
FIG. 5 is a schematic view for explaining a process using a second halftone mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention. FIG. Film / metal layer film formation / metal oxide layer film formation / second resist-coated cross-sectional view, (b) shows a half-tone exposed / developed cross-sectional view.
In FIG. 2A, first, indium oxide-zinc oxide-tin oxide (In ₂ O ₃ : ZnO: SnO ₂ ) is formed on the glass substrate 10 and the exposed n-type oxide semiconductor layer 40 and the gate insulating film 30. = About 60:20:20 wt%) Oxide semiconductor having a thickness of about 120 nm under conditions where oxygen is about 1%, argon is about 99%, and the oxide conductor layer 50 is not crystallized by high-frequency sputtering using a target. Layer 50 is formed. The energy gap of the oxide conductor layer 50 was about 3.2 eV.

Here, the indium oxide-tin oxide-zinc oxide (In ₂ O ₃ : SnO ₂ : ZnO = about 60:20:20 wt%) thin film used as the oxide conductor layer 50 of this embodiment is heated at 350 ° C. But it does not crystallize. It is better not to crystallize the oxide conductor layer 50, which enables etching with an aqueous oxalic acid solution. Further, the composition of the oxide conductor layer 50 is not etched by a mixed acid of phosphoric acid, acetic acid and nitric acid even if it is not crystallized. That is, the oxide conductor layer 50 is resistant to a liquid (mixed acid) that etches the metal layer 60 on the pixel electrode 57, and does not affect the crystallized n-type oxide semiconductor layer 40. It has selective etching characteristics such that it can be etched with an etching solution (aqueous oxalic acid solution). Accordingly, even when the metal oxide layer 68 and the metal layer 60 on the pixel electrode 57 are etched in the fourth etching described later, the pixel electrode 57 is not etched and the pixel electrode 57 can be exposed.
Further, when the oxide conductor layer 50 is made of ITO (indium tin oxide), if a film in which Al or the like is laminated is present in the electrolyte, the phenomenon that the Al film is corroded by the battery reaction (electrolytic reaction). Although this occurs, in the indium oxide-zinc oxide-tin oxide based oxide conductor layer 50 in the present embodiment, the above-mentioned electrolytic corrosion reaction was not observed.

Preferably, when an indium oxide-zinc oxide-tin oxide system is used for the oxide conductor layer 50, zinc oxide is about 6 to 30% by weight, tin oxide is about 5 to 30% by weight, and the remainder is indium oxide. Good. More preferably, zinc oxide is about 10 to 25% by weight, tin oxide is about 8 to 25% by weight, and the remainder is indium oxide. The reason for this is that when the oxide oxide layer 50 is formed when the oxide conductor layer 50 is formed when the zinc oxide is less than about 6 wt% or the tin oxide is less than 5 wt%, When the n-type oxide semiconductor layer 40 is heat-treated, the oxide conductor layer 50 may be crystallized. By this crystallization, the oxide conductor layer 50 can be etched with an aqueous oxalic acid solution and does not become a film that is resistant to a mixed acid composed of phosphoric acid, acetic acid, and nitric acid. This is because the etching process using the silicon oxide may not function. In addition, when the zinc oxide exceeds about 30% by weight or the tin oxide exceeds about 30% by weight, the resistance value of the obtained oxide conductor layer 50 increases, or etching can be performed with an aqueous oxalic acid solution. In addition, the film may not be resistant to a mixed acid composed of phosphoric acid, acetic acid and nitric acid.
The n-type oxide semiconductor layer 40 is not limited to the indium oxide-zinc oxide-tin oxide system. For example, the n-type oxide semiconductor layer 40 can be etched with an aqueous oxalic acid solution, and is mixed with a mixed acid composed of phosphoric acid, acetic acid, and nitric acid. Any transparent conductive film that is resistant and does not cause an electrolytic corrosion reaction can be used.

  Next, a metal layer (Mo / Al / Mo) 60 serving as an auxiliary conductive layer is formed on the oxide conductor layer 50 to about 300 nm (the Mo / Al / Mo layer has a thickness of about 50 nm / 200 nm / 50 nm, respectively). Form a film. That is, first, a Mo / Al / Mo layer is formed on the oxide conductor layer 50 at room temperature. The metal layer 60 is not limited to the Mo / Al / Mo laminated film, and for example, a metal thin film such as Ti / Al / Ti may be used. Further, a single layer or multilayer laminated film of metals or alloys such as Al, Mo, Ag, Cu, Ti, and Cr may be used.

In the present embodiment, the metal oxide layer 68 is formed on the metal layer 60 as a metal oxide layer for the auxiliary conductive layer that protects the metal layer 60 and has conductivity. This metal oxide layer 68 is formed on the metal layer 60 by using an indium oxide-zinc oxide (In ₂ O ₃ : ZnO = about 90:10 wt%) target by high-frequency sputtering to have about 1% oxygen and about argon. It is formed to a thickness of about 50 nm under the condition of 99%.
Although the metal oxide layer 68 may not be formed, the metal oxide layer 68 is usually formed because of the effects of preventing corrosion of the metal layer 60 and improving durability. In this embodiment, a film was formed using an indium oxide-zinc oxide (In ₂ O ₃ : ZnO = about 90:10 wt%) target, but various types can be used as long as they are soluble in a mixed acid composed of phosphoric acid, acetic acid and nitric acid. A transparent conductive film can be used. Moreover, when laminating | stacking with Al etc., it is good to use the transparent conductive film with a small electrolytic corrosion reaction. For example, in the zinc oxide-tin oxide system, the zinc oxide content is preferably about 70 to 95% by weight. More preferably, the zinc oxide content is about 80 to 90% by weight. This is because if the zinc oxide content is less than about 70% by weight, it may not dissolve in the mixed acid composed of phosphoric acid, acetic acid and nitric acid, and if it exceeds about 95% by weight, the etching rate due to the mixed acid composed of phosphoric acid, acetic acid and nitric acid. This is because there is a case where the speed is too fast to be controlled. Further, the metal oxide layer 68 is an auxiliary conductive layer, that is, the auxiliary conductive layer of this embodiment includes a metal layer 60 and a metal oxide layer 68 formed on the metal layer 60.
Subsequently, the second resist 61 is stacked on the metal oxide layer 68 (step S4).

  Next, as shown in FIG. 2B, the second resist 61 is formed in a predetermined shape by the second halftone mask 62 and halftone exposure (step S5 in FIG. 1). The second resist 61 covers the source electrode 53, the drain electrode 54, the source wiring 55, the drain wiring 56, and the pixel electrode 57, and the other part covers the pixel electrode 57 by the halftone mask portion 621. It is formed in a shape thinner than this part.

FIG. 6 is a schematic view for explaining a process using a second halftone mask of the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and FIG. Sectional drawing (b) is a sectional view of the second resist formed again.
In FIG. 5A, first, as the third etching, the metal oxide layer 68 and the metal layer 60 are etched using the second resist 61 and a mixed acid composed of phosphoric acid, acetic acid and nitric acid, and then The oxide conductor layer 50 is selectively etched using the second resist 61 and an aqueous oxalic acid solution. Thus, the desired drain electrode 54, channel portion 46, source electrode 53, source wiring 55, drain wiring 56 and pixel electrode 57 are formed, and the source electrode auxiliary electrode 531 comprising the metal oxide layer 68 and the metal layer 60 is formed. The drain electrode auxiliary electrode 541, the source wiring auxiliary wiring 551, and the drain wiring auxiliary wiring 561 are formed (step S5 in FIG. 1). By the etching, a channel portion 46 is formed in the n-type oxide semiconductor layer 40 above the gate electrode 23. Thereby, the TFT substrate 1 is called a channel etching type.

Note that the n-type oxide semiconductor layer 40 is heated and crystallized (for example, at 200 ° C. or higher and 350 ° C. or lower) before etching with the oxalic acid aqueous solution. That is, the indium oxide-zinc oxide-gallium oxide (In ₂ O ₃ : ZnO: Ga ₂ O ₃ = about 90: 3: 7 wt%) used as the n-type oxide semiconductor layer 40 of this embodiment is in an amorphous state ( In the non-crystallized state, etching is performed with an aqueous oxalic acid solution. However, when crystallized, etching is not performed with an aqueous oxalic acid solution or a mixed acid composed of phosphoric acid, acetic acid, and nitric acid. As a result, the n-type oxide semiconductor layer 40 becomes resistant to a chemical solution (in this embodiment, an oxalic acid aqueous solution) that etches the oxide conductor layer 50 existing thereabove. The problem that the n-type oxide semiconductor layer 40 is eroded can be prevented. Further, the n-type oxide semiconductor layer 40 (active layer) is crystallized to exhibit stable semiconductor characteristics.

  Next, as shown in FIG. 2B, the second resist 61 is re-formed (step S6 in FIG. 1). That is, first, as shown in FIG. 4B, the resist on the pixel electrode 57 formed thin by halftone exposure is ashed out of the second resist 61, and the second resist 61 is re-formed.

FIG. 7 is a schematic view for explaining a process using a second halftone mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and (a) shows a fourth etching process. A cross-sectional view, (b) shows a cross-sectional view with the second resist removed.
In FIG. 6A, as the fourth etching, the re-formed second resist 61 and a mixed acid composed of phosphoric acid, acetic acid and nitric acid are used, and the metal oxide layer 68 and the metal layer on the pixel electrode 57 are used. 60 is selectively etched to expose the pixel electrode 57 (step S6 in FIG. 1). That is, the non-crystallized oxide conductor layer 50 (pixel electrode 57) is resistant to a mixed acid composed of phosphoric acid, acetic acid, and nitric acid, so that the pixel electrode 57 is not dissolved. The metal oxide layer 68 and the metal layer 60 on 57 are selectively etched.

  Subsequently, as shown in FIG. 5B, the re-formed second resist 61 is all ashed, and the source electrode 53, the drain electrode 54, the source wiring 55, the drain wiring 56, and the pixel electrode 57 are ashed. The auxiliary conductive layer made of the metal oxide layer 68 and the metal layer 60 is exposed (step S6 in FIG. 1). That is, the source electrode auxiliary electrode 531, the drain electrode auxiliary electrode 541, the source wiring auxiliary wiring 551, and the drain wiring auxiliary wiring 561 made of the metal oxide layer 68 and the metal layer 60 are exposed (see FIG. 8). The drain electrode 54, the channel portion 46, the source electrode 53, the source wiring 55, and the pixel electrode 57 shown in FIG. 7B show a CC cross section in FIG. 8, and the drain wiring 56 has a DD cross section. Is shown.

Next, as shown in FIG. 1, a protective insulating film 70 and a third resist 71 are sequentially stacked (step S7), and a drain wiring pad 58, a gate wiring pad 25, and a pixel are used using the third mask 72. The electrode 57 is exposed (step S8).
Next, processing using the third halftone mask 72 will be described with reference to the drawings.

FIG. 9 is a schematic diagram for explaining a process using a third mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention. FIG. Three resist-coated cross-sectional views are shown, and (b) is an exposed / developed cross-sectional view.
In FIG. 2A, first, a silicon nitride (SiNx) film is formed on the TFT substrate 1 on which the re-formed second resist 61 is ashed (usually on the entire upper surface of the TFT substrate 1) by glow discharge CVD. A protective insulating film 70 having a thickness of about 200 nm is deposited. As the discharge gas, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used. Subsequently, a third resist 71 is stacked on the protective insulating film 70 (step S7).

  Next, as shown in FIG. 4B, the third resist 71 is formed in a predetermined shape by the third mask 72 (step S8). The third resist 71 is formed so as to cover all the protective insulating films 70 except on the pixel electrode 57, the drain wiring pad 58 and the gate wiring pad 25.

FIG. 10 is a schematic view for explaining a process using a third mask in the method for manufacturing a TFT substrate according to the first embodiment of the present invention, and (a) is a fifth etched cross-sectional view. (B) is a cross-sectional view of the third resist removed.
In FIG. 6A, as a fifth etching, a protective resist film 70 on the pixel electrode 57 and the drain wiring pad 58, and a third resist 71 and CHF (CF ₄ , CHF ₃ gas, etc.), and Then, the protective insulating film 70 and the gate insulating film 30 on the gate wiring pad 25 are dry-etched to expose the pixel electrode 57, the drain wiring pad 58, and the gate wiring pad 25 (step S8 in FIG. 1).

  Next, as shown in FIG. 5B, when the third resist 71 is ashed, the protective insulating film 70 is formed on the substrate 10 except for the pixel electrode 57, the drain wiring pad 58, and the gate wiring pad 25. Exposed (see FIG. 11). The drain electrode 54, the channel portion 46, the gate electrode 23, the source electrode 53, the source wiring 55, and the pixel electrode 57 shown in FIG. 10B show the EE cross section in FIG. , FF cross section is shown, and the gate wiring pad 25 shows GG cross section.

Thus, according to the manufacturing method of the TFT substrate 1 of the present embodiment, the manufacturing cost can be significantly reduced by reducing the number of manufacturing steps, and the n-type oxide semiconductor layer 40 of the channel portion 46 can be reduced. Since the upper portion is protected by the protective insulating film 70, it can be stably operated over a long period of time. Furthermore, since the gate electrode / wiring thin film 20, the gate insulating film 30, the n-type oxide semiconductor layer 40 as the first oxide layer, and the first resist 41 are collectively formed on the substrate 10, the gate insulation The problem that impurities are mixed into the interface between the film 30 and the n-type oxide semiconductor layer 40 can be prevented, the quality of the n-type oxide semiconductor layer 40 serving as an active layer is improved, and the operational stability of the TFT substrate 1 is improved. Can do.
Further, the n-type oxide semiconductor layer 40 is formed only at predetermined positions (predetermined positions corresponding to the drain electrode 54, the channel portion 46, the source electrode 53, and the source wiring 55). It is possible to eliminate the worry of interference between the two (crosstalk). Furthermore, since the protective insulating film 70 is formed, an organic electroluminescent device can be easily obtained by providing the TFT substrate 1 with an organic EL material, an electrode, and a protective film.
Further, the source electrode auxiliary electrode 531, the drain electrode auxiliary electrode 541, the source wiring auxiliary wiring 551, and the drain wiring auxiliary wiring 561 formed of the metal oxide layer 68 and the metal layer 60 are formed. The electrical resistance of the drain electrode 54, the source wiring 55, and the drain wiring 56 can be reduced, reliability can be improved, and reduction in energy efficiency can be suppressed.

[Second Embodiment in Manufacturing Method of TFT Substrate]
FIG. 12 is a schematic flowchart for explaining a method for manufacturing a TFT substrate according to the second embodiment of the present invention.
In the figure, first, on a substrate 10, a gate electrode / wiring thin film 20, a gate insulating film 30, an n-type oxide semiconductor layer 40 as a first oxide layer, and an oxide as a second oxide layer. The conductor layer 50 and the first resist 51 are sequentially stacked (step S11), and then the gate electrode 23 and the gate wiring 24 are formed using the first halftone mask 52 (step S12). The first resist 51 is re-formed, the oxide conductor layer 50 and the n-type oxide semiconductor layer 40 above the gate wiring 24 are etched, and the gate electrode 23 and the gate wiring 24 are oxidized by anodic oxidation ( Step S13).
Next, processing using the first halftone mask 52 will be described with reference to the drawings.

(Process using the first halftone mask)
FIG. 13: is the schematic for demonstrating the process using the 1st halftone mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is the glass substrate before a process. Cross-sectional view, (b) is a cross-sectional view of gate electrode / wiring thin film formation / gate insulating film formation / n-type oxide semiconductor layer formation / oxide conductor layer formation / first resist coating , (C) shows a cross-sectional view after halftone exposure / development.
In FIG. 1A, first, a translucent glass substrate 10 is prepared.

Next, as shown in FIG. 2B, on the glass substrate 10, the gate electrode / wiring thin film 20, the gate insulating film 30, and the first oxide layer n are formed as the gate electrode 23 and the gate wiring 24. The type oxide semiconductor layer 40, the oxide conductor layer 50 as the second oxide layer, and the first resist 41 are sequentially stacked (step S1).
That is, Al (aluminum) -Ce (cerium) is laminated on the glass substrate 10 using a high frequency sputtering method, and a gate electrode / wiring thin film made of a metal thin film having a thickness of about 300 nm (for gate electrode and gate wiring). Thin film) 20 is formed.

Subsequently, a gate insulating film 30 that is a silicon nitride (for example, SiN _X film) is deposited on the gate electrode / wiring thin film 20 by a glow discharge CVD (chemical vapor deposition) method to a thickness of about 300 nm. At this time, a SiH ₄ —NH ₃ —N ₂ -based mixed gas is used as a discharge gas.

Next, an indium oxide-zinc oxide-gallium oxide (In ₂ O ₃ : ZnO: Ga ₂ O ₃ = about 90: 3: 7 wt%) target is used as the first oxide layer on the gate insulating film 30. Then, an n-type film having a thickness of about 100 nm is formed by a high-frequency sputtering method under a condition that oxygen is about 10%, argon is about 90%, and the substrate temperature does not exceed about 200 ° C. (that is, the n-type oxide semiconductor layer 40 is not crystallized). An oxide semiconductor layer (active layer) 40 is formed. Subsequently, an indium oxide-zinc oxide-tin oxide (In ₂ O ₃ : ZnO: SnO ₂ = about 60:20:20 wt%) target is used on the n-type oxide semiconductor layer 40 by a high-frequency sputtering method. An oxide semiconductor layer 50 having a thickness of about 120 nm is formed under conditions where oxygen is about 1%, argon is about 99%, and the oxide conductor layer 50 is not crystallized. The energy gap of the oxide conductor layer 60 was about 3.2 eV.
Next, the 1st resist 51 is laminated | stacked on the oxide conductor layer 50 (step S1).

  Next, as shown in FIG. 4C, the first resist 51 is formed into a predetermined shape by the first halftone mask 52 and halftone exposure (step S12). The first resist 51 covers the gate electrode 23 and the gate wiring 24, and the halftone mask portion 521 forms a portion covering the gate wiring 24 in a thinner shape than the other portions.

FIG. 14 is a schematic view for explaining a process using a first halftone mask in the method for manufacturing a TFT substrate according to the second embodiment of the present invention. FIG. 1 shows a cross-sectional view where the resist is re-formed, (b) shows a cross-sectional view after the second etching / first resist is peeled off, and (c) shows a cross-sectional view where the gate wiring / electrode is anodized. .
In FIG. 9A, first, as the first etching, the first resist 41 (see FIG. 13C) is used, and the oxide conductor layer 50 (not crystallized) with an oxalic acid aqueous solution and The n-type oxide semiconductor layer 40 (not crystallized) is etched, and then the gate insulating film 30 is etched by a reactive ion etching method (dry etching) using CHF (CF ₄ , CHF ₃ gas, etc.) Subsequently, the gate electrode / wiring thin film 20 is etched by a mixed acid composed of phosphoric acid, acetic acid and nitric acid. By the etching, the gate electrode 23 and the gate wiring 24 are formed (step S12). Subsequently, ashing is performed on the resist on the gate wiring 24 formed thin by halftone exposure in the first resist 51 (see FIG. 13C), and the first resist 51 is re-formed (FIG. 1). Step S13).

  Next, as shown in FIG. 6B, as the second etching, the re-formed first resist 41 and oxalic acid aqueous solution are used to form the oxide conductor layer 50 and the n-type over the gate wiring 24. The oxide semiconductor layer 40 is etched, and then the re-formed first resist 51 is ashed.

Next, as shown in FIG. 3C, the gate electrode 23 and the gate wiring 24 are anodized (step S13). That is, the gate electrode 23 and the gate wiring 24 whose upper surface is covered with the gate insulating film 30 and whose side surfaces are exposed in FIG. 4B are oxidized to the predetermined depth on the side surfaces, thereby forming an anodized portion 26 having insulating properties. Is done. As a result, the gate electrode 23 and the gate wiring 24 are insulated from the oxide conductor layer 50 (as the third oxide layer) that is further stacked in a later step. In addition, the gate electrode 23 shown in FIG.14 (c) has shown the HH cross section in FIG. 15, and the gate wiring 24 has shown the II cross section.
Subsequently, although not shown, the gate electrode 23 and the gate wiring 24 insulated by the gate insulating film 30 and the anodic oxidation portion 26 are formed, and then heat treatment (for example, at 200 ° C. or higher and 350 ° C. or lower) is performed. The resistance value of Al in the wiring thin film 20 is lowered, and the n-type oxide semiconductor layer 40 is crystallized.

  In the present embodiment, the gate electrode / wiring thin film 20, the gate insulating film 30, the n-type oxide semiconductor layer 40, the oxide conductor layer 50, and the first resist 51 are collectively formed on the substrate 10. . As a result, impurities are not mixed into the interface between the gate insulating film 30 and the n-type oxide semiconductor layer 40 and the interface between the n-type oxide semiconductor layer 40 and the oxide conductor layer 50. The quality of the layer 40 is improved, and the operational stability of the TFT substrate 1a can be improved. That is, in the TFT substrate 1a of the present embodiment, impurities are not mixed into the interface between the lower surface and the upper surface of the n-type oxide semiconductor layer 40 as compared with the TFT substrate 1, and therefore, the n-type oxide semiconductor layer 40 serving as an active layer. Quality can be further improved, and durability and operational stability can be further improved.

Next, as shown in FIG. 12, the oxide conductor layer 50 as the third oxide layer, the metal layer 60 and the metal oxide layer 68 as the auxiliary conductive layer, and the second resist 61 are sequentially stacked. Next, using the second halftone mask 62, the source electrode 53, the drain electrode 54, the source wiring 55, the drain wiring 56 and the pixel electrode 57, and the channel portion 46 are formed (step S14). S15) Subsequently, the second resist 61 is formed again, and the metal layer 60 on the pixel electrode 57 is selectively etched to expose the pixel electrode 57 (step S16).
Next, processing using the second halftone mask 62 will be described with reference to the drawings.

(Process using second halftone mask)
FIG. 16 is a schematic view for explaining a process using a second halftone mask in the method for producing a TFT substrate according to the second embodiment of the present invention. FIG. Film / metal layer film formation / metal oxide layer film formation / second resist-coated cross-sectional view, (b) shows a half-tone exposed / developed cross-sectional view.
In FIG. 1A, first, on the glass substrate 10 and the oxide conductor layer 50 and the gate insulating film 30 previously stacked and exposed, under the same conditions as the oxide conductor layer 50 previously stacked, A new oxide conductor layer 50 is stacked. That is, using an indium oxide-zinc oxide-tin oxide (In ₂ O ₃ : ZnO: SnO ₂ = about 60:20:20 wt%) target, high-frequency sputtering is used to provide about 1% oxygen, about 99% argon, and Then, a new oxide semiconductor layer 50 having a thickness of about 120 nm is formed under the condition that the oxide conductor layer 50 is not crystallized. As a result, the thickness of the oxide conductor layer 50 (formed by double stacking) above the gate electrode 23 is about 240 nm.

Next, a metal layer (Mo / Al / Mo) 60 serving as an auxiliary conductive layer is formed on the oxide conductor layer 50 by a method similar to that of the above embodiment, and the thickness of the Mo / Al / Mo layer is about 300 nm. Next, a metal oxide layer 68 (thickness: about 50 nm) having a conductivity and protecting the metal layer 60 is formed.
Next, the second resist 61 is stacked on the metal oxide layer 68 (step S14).

  Next, as shown in FIG. 4B, the second resist 61 is formed into a predetermined shape by the second halftone mask 62 and halftone exposure (step S15 in FIG. 12). The second resist 61 covers the source electrode 53, the drain electrode 54, the source wiring 55, the drain wiring 56, and the pixel electrode 57, and the other part covers the pixel electrode 57 by the halftone mask portion 621. It is formed in a shape thinner than this part.

FIG. 17 is a schematic view for explaining a process using a second halftone mask in the method for manufacturing a TFT substrate according to the second embodiment of the present invention, and FIG. FIG. 6B is a cross-sectional view of the second resist re-formed / fourth etched / second resist stripped.
In FIG. 6A, in the same manner as in the above embodiment, first, as the third etching, the second resist 61 and a mixed acid composed of phosphoric acid, acetic acid and nitric acid are used. Then, the metal layer 60 is etched, and then the oxide conductor layer 50 is selectively etched using the second resist 61 and an aqueous oxalic acid solution. Thus, the desired drain electrode 54, channel portion 46, source electrode 53, source wiring 55, drain wiring 56 and pixel electrode 57 are formed, and the source electrode auxiliary electrode 531 comprising the metal oxide layer 68 and the metal layer 60 is formed. The drain electrode auxiliary electrode 541, the source wiring auxiliary wiring 551, and the drain wiring auxiliary wiring 561 are formed (step S15 in FIG. 12).

  Next, as shown in FIG. 6B, the second resist 61 is re-formed, and then, as a fourth etching, the re-formed second resist 61, and phosphoric acid, acetic acid, and nitric acid The metal oxide layer 68 and the metal layer 60 on the pixel electrode 57 are selectively etched using the mixed acid made of to expose the pixel electrode 57 (step S16 in FIG. 12), and the re-formed first All the second resist 61 is ashed. As a result, the source electrode auxiliary electrode 531, the drain electrode auxiliary electrode 541, the source wiring auxiliary wiring 551, and the drain wiring auxiliary wiring 561 made of the metal oxide layer 68 and the metal layer 60 are exposed (see FIG. 8). The drain electrode 54, the channel portion 46, the source electrode 53, the source wiring 55, and the pixel electrode 57 shown in FIG. 17B show the CC cross section in FIG. 8, and the drain wiring 56 shows the DD cross section. Is shown.

Next, as shown in FIG. 12, the protective insulating film 70 and the third resist 71 are sequentially stacked (step S17), and the drain wiring pad 58, the gate wiring pad 25, and the pixel are used using the third mask 72. The electrode 57 is exposed (step S18).
Next, processing using the third halftone mask 72 will be described with reference to the drawings.

FIG. 18 is a schematic view for explaining a process using a third mask in the method for manufacturing a TFT substrate according to the second embodiment of the present invention. FIG. FIG. 3B is a sectional view of the third resist applied / exposed / developed, and FIG. 5B is a sectional view of the fifth etched / third resist stripped.
In FIG. 4A, a protective insulating film 70 is first deposited to a thickness of about 200 nm on the TFT substrate 1a on which the re-formed second resist 61 is ashed by the same method as in the above embodiment. Subsequently, a third resist 71 is stacked on the protective insulating film 70 (step S17). Next, the third resist 71 is formed in a predetermined shape by the third mask 72 (step S18). The third resist 71 is formed so as to cover all the protective insulating films 70 except on the pixel electrode 57, the drain wiring pad 58 and the gate wiring pad 25.

Next, as shown in FIG. 6B, the third resist 71 and CHF (CF ₄ , CHF ₃ gas, etc.) are used as the fifth etching to protect the pixel electrode 57 and the drain wiring pad 58. The insulating film 70 for protection, and the protective insulating film 70 and the gate insulating film 30 on the gate wiring pad 25 are dry-etched to expose the pixel electrode 57, the drain wiring pad 58, and the gate wiring pad 25 (step S18 in FIG. 12). ). Subsequently, when the third resist 71 is ashed, as shown in FIG. 11, the protective insulating film 70 is exposed on the substrate 10 except on the pixel electrode 57, the drain wiring pad 58 and the gate wiring pad 25. The drain electrode 54, the channel portion 46, the gate electrode 23, the source electrode 53, the source wiring 55, and the pixel electrode 57 shown in FIG. 18B show the EE cross section in FIG. , FF cross section is shown, and the gate wiring pad 25 shows GG cross section.

  As described above, according to the manufacturing method of the TFT substrate 1a of the present embodiment, impurities are not mixed into the interface between the lower surface and the upper surface of the n-type oxide semiconductor layer 40 as compared with the first embodiment. The quality of the n-type oxide semiconductor layer 40 can be further improved, and durability and operational stability can be further improved. Other effects are almost the same as those of the first embodiment.

[First embodiment of TFT substrate]
The present invention is also effective as the invention of the TFT substrate 1.
The TFT substrate 1 according to the first embodiment is formed on a glass substrate 10 and the glass substrate 10 as shown in FIGS. 10B and 11, and the upper surface is covered with a gate insulating film 30. The gate electrode 23 and the gate wiring 24 which are insulated by anodizing the side surfaces (by the anodized portion 26), and n as a first oxide layer formed on the gate insulating film 30 on the gate electrode 23 An oxide conductor layer 50 as a second oxide layer formed on the n-type oxide semiconductor layer 40 and the n-type oxide semiconductor layer 40 by being separated by a channel portion 46 is provided. In this case, usually, at least the gate electrode / wiring thin film 20, the gate insulating film 30, and the n-type oxide semiconductor layer 40 are collectively formed on the glass substrate 10, and the gate insulating film 30 and the n-type oxide semiconductor layer are formed. Since impurities are not mixed into the interface 40, the quality of the n-type oxide semiconductor layer 40 serving as the active layer is improved, and the operational stability can be improved. Further, by using the n-type oxide semiconductor layer 40 as the active layer of the TFT, it is stable even when a current is passed, and is useful for an organic electroluminescence device that operates by current control.

In the TFT substrate 1, the oxide conductor layer 50 also serves as the source wiring 55, the drain wiring 56, the source electrode 53, the drain electrode 54, and the pixel electrode 57. If it does in this way, the number of masks used at the time of manufacturing can be reduced, and a manufacturing process can be reduced, thereby improving production efficiency and reducing the cost of manufacturing.
Further, the TFT substrate 1 is covered with a protective insulating film 70 above the TFT substrate 1, and the protective insulating film 70 is opened at a position corresponding to the pixel electrode 57, the drain wiring pad 58 and the gate wiring pad 25. Since the upper portion of the n-type oxide semiconductor layer 40 that is the channel portion 46 is protected by the protective insulating film 70, it can operate stably over a long period of time. Further, since the TFT substrate 1 itself has a structure including the protective insulating film 70, it is possible to provide the TFT substrate 1 that can easily manufacture display means and light emitting means using liquid crystal or organic EL material.

In addition, the n-type oxide semiconductor layer 40 is formed at a predetermined position corresponding to the channel portion 46 in the TFT substrate 1. As described above, the n-type oxide semiconductor layer 40 is normally positioned at a predetermined position. Therefore, it is possible to eliminate the concern that the gate wirings 24 interfere with each other (crosstalk).
Further, the energy gap of the oxide conductor layer 50 is set to 3.0 eV or more, so that malfunction due to light in the pixel electrode 57 can be prevented.

Further, the TFT substrate 1 includes a source wiring auxiliary wiring 551 composed of a metal oxide layer 68 and a metal layer 60 on the source wiring 55, drain wiring 56, source electrode 53 and drain electrode 54, drain wiring auxiliary wiring 561, and so on. A source electrode auxiliary electrode 531 and a drain electrode auxiliary electrode 541 are formed. If it does in this way, the electrical resistance of each wiring 55 and 56 and the electrodes 53 and 54 can be reduced, and while being able to improve reliability, the fall of energy efficiency can be suppressed.
Here, in the TFT substrate 1, the auxiliary conductive layer has a metal layer 60 and a metal oxide layer 68 as a metal oxide layer for the auxiliary conductive layer that protects the metal layer 60 on the metal layer 60. As a configuration. In this way, corrosion of the metal layer 60 can be prevented and durability can be improved.

  Thus, according to the TFT substrate 1 of the present embodiment, since impurities are not mixed into the interface between the gate insulating film 30 and the n-type oxide semiconductor layer 40, the quality of the n-type oxide semiconductor layer 40 serving as an active layer is improved. And operational stability can be improved. In addition, the number of masks used in manufacturing can be reduced and the number of manufacturing processes can be reduced, so that the production efficiency can be improved and the manufacturing cost can be reduced. Furthermore, since the n-type oxide semiconductor layer 40 is usually formed only above the gate electrode 23, it is possible to eliminate the concern that the gate wirings 24 interfere with each other (crosstalk).

[Second Embodiment of TFT Substrate]
The present invention is also effective as an invention of the TFT substrate 1a.
Compared with the TFT substrate 1, the TFT substrate 1 a according to the second embodiment has an n-type oxide semiconductor layer below the oxide conductor layer 50 above the gate electrode 23 as shown in FIG. 40 and film formation together. As a result, impurities are not mixed into the interface between the lower surface and the upper surface of the n-type oxide semiconductor layer 40, so that the quality of the n-type oxide semiconductor layer 40 serving as an active layer is further improved, and durability and operational stability are further improved. Can be made. Other effects are almost the same as those of the TFT substrate 1 of the first embodiment.

  The TFT substrate and the method for manufacturing the TFT substrate according to the present invention have been described with reference to the preferred embodiments. However, the TFT substrate and the method for manufacturing the TFT substrate according to the present invention are not limited to the above-described embodiments. Needless to say, various modifications can be made within the scope of the present invention.

  The TFT substrate and the TFT substrate manufacturing method of the present invention are not limited to the TFT substrate and TFT substrate manufacturing method used for LCD (Liquid Crystal Display) and organic EL display devices. For example, LCD (Liquid Crystal Display) The present invention can also be applied to a display device other than a device) or an organic EL display device, or a TFT substrate used for other purposes and a manufacturing method of the TFT substrate.

The schematic flowchart figure for demonstrating the manufacturing method of the TFT substrate concerning 1st embodiment of this invention is shown. It is the schematic for demonstrating the process using the 1st halftone mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is sectional drawing of the glass substrate before a process, (B) is a gate electrode / wiring thin film deposition / gate insulating film deposition / n-type oxide semiconductor layer deposition / first resist coated cross-sectional view, and (c) is a halftone exposure / development. A cross-sectional view is shown. It is the schematic for demonstrating the process using the 1st halftone mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is 1st etching / 1st resist re-processing. The formed sectional view, (b) shows the sectional view after the second etching / first resist is removed, and (c) shows the anodized sectional view of the gate wiring / electrode. In the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, the schematic plan view of the principal part of the TFT substrate in which the gate electrode and the gate wiring were formed is shown. It is the schematic for demonstrating the process using the 2nd halftone mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is oxide conductor layer film formation / metal layer Sectional view of film formation / metal oxide layer formation / second resist coating, (b) shows a halftone exposure / development sectional view. It is the schematic for demonstrating the process using the 2nd halftone mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is 3rd etched sectional drawing, (B) is a cross-sectional view of the second resist formed again. It is the schematic for demonstrating the process using the 2nd halftone mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is 4th sectional drawing etched, (B) is a cross-sectional view of the second resist peeled off. In the TFT substrate manufacturing method according to the first embodiment of the present invention, the main part of the glass substrate with the source electrode auxiliary electrode, the drain electrode auxiliary electrode, the source wiring auxiliary wiring, the drain wiring auxiliary wiring, and the pixel electrode exposed. The schematic plan view of is shown. It is the schematic for demonstrating the process using the 3rd mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is film-forming of protective insulating film / 3rd resist application | coating (B) shows the exposed / developed cross-sectional view. It is the schematic for demonstrating the process using the 3rd mask of the manufacturing method of the TFT substrate concerning 1st embodiment of this invention, (a) is sectional drawing which carried out the 5th etching, (b) ) Shows a sectional view after the third resist is peeled off. FIG. 2 is a schematic plan view of a main part of a TFT substrate with a protective insulating film, source / drain wiring pads, gate wiring pads, and pixel electrodes exposed in the TFT substrate manufacturing method according to the first embodiment of the present invention. The schematic flowchart figure for demonstrating the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention is shown. It is the schematic for demonstrating the process using the 1st halftone mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is sectional drawing of the glass substrate before a process, (B) is a gate electrode / wiring thin film formation / gate insulating film formation / n-type oxide semiconductor layer formation / oxide conductor layer formation / first resist-coated cross-sectional view. Shows a cross-sectional view after halftone exposure / development. It is the schematic for demonstrating the process using the 1st halftone mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is 1st etching / 1st resist re-processing. The formed sectional view, (b) shows the sectional view after the second etching / first resist is removed, and (c) shows the anodized sectional view of the gate wiring / electrode. In the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, the schematic plan view of the principal part of the TFT substrate in which the gate electrode and the gate wiring were formed is shown. It is the schematic for demonstrating the process using the 2nd halftone mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is an oxide conductor layer film formation / metal layer Cross-sectional view of film formation / metal oxide layer formation / second resist application, (b) shows a cross-sectional view of halftone exposure / development. It is the schematic for demonstrating the process using the 2nd halftone mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is 3rd etched sectional drawing, (B) is a cross-sectional view of the second resist re-formed / fourth etching / second resist stripped. It is the schematic for demonstrating the process using the 3rd mask of the manufacturing method of the TFT substrate concerning 2nd embodiment of this invention, (a) is film-forming of protective insulating film / 3rd resist application / Exposure / development sectional view, (b) shows a fifth etching / third resist stripped sectional view. It is the schematic for demonstrating the manufacturing method of the TFT substrate concerning a prior art example, (a) is sectional drawing in which the gate electrode was formed, (b) is sectional drawing in which the etch stopper was formed, (c). Is a cross-sectional view in which a source electrode and a drain electrode are formed, (d) is a cross-sectional view in which an interlayer insulating film is formed, and (e) is a cross-sectional view in which a transparent electrode is formed.

Explanation of symbols

1, 1a TFT substrate 10 Glass substrate 20 Gate electrode / wiring thin film 23 Gate electrode 24 Gate wiring 25 Gate wiring pad 26 Anodized portion 30 Gate insulating film 40 n-type oxide semiconductor layer 41 First resist 42 First half Tone mask 46 Channel portion 40 N-type oxide semiconductor layer 46 Channel portion 50 Oxide conductor layer 51 First resist 52 First halftone mask 53 Source electrode 54 Drain electrode 55 Source wiring 56 Drain wiring 57 Pixel electrode 60 Metal Layer 61 Second resist 62 Second halftone mask 68 Metal oxide layer 70 Protective insulating film 71 Third resist 72 Third mask 210 Glass substrate 212 Gate electrode 213 Gate insulating film 214 α-Si: H ( i) Film 215 Etch stopper 216 α-Si: H (n) film 21 a Source electrode 217b Drain electrode 218 Interlayer insulating film 218a Through hole 219 Transparent electrode 531 Source electrode auxiliary electrode 541 Drain electrode auxiliary electrode 551 Source wiring auxiliary wiring 561 Drain wiring auxiliary wiring 421 Halftone mask portion 521 Halftone mask portion 621 Halftone mask

Claims (11)

A substrate,
A gate electrode and a gate wiring which are formed on the substrate, the upper surface is covered with a gate insulating film, and the side surface is insulated by anodization;
A first oxide layer formed on the gate insulating film on the gate electrode;
A TFT substrate, comprising: a second oxide layer formed on the first oxide layer and separated by a channel portion.   The TFT substrate according to claim 1, wherein the second oxide layer also serves as at least a pixel electrode.   The upper part of the TFT substrate is covered with a protective insulating film, and the protective insulating film has openings at positions corresponding to the pixel electrodes, source / drain wiring pads, and gate wiring pads. The TFT substrate according to claim 1 or 2.   The first oxide layer is an n-type oxide semiconductor layer, and the second oxide layer is an oxide conductor layer. TFT substrate according to item.   5. The TFT substrate according to claim 1, wherein the first oxide layer is formed at a predetermined position corresponding to the channel portion. 6.   The TFT substrate according to claim 1, wherein an energy gap of the second oxide layer is 3.0 eV or more.   The TFT substrate according to claim 1, wherein an auxiliary conductive layer is formed on at least one of the source wiring, the drain wiring, the source electrode, the drain electrode, and the pixel electrode.   8. The TFT substrate according to claim 7, wherein the auxiliary conductive layer has a metal oxide layer for an auxiliary conductive layer for protecting the auxiliary conductive layer on the upper side. A step of sequentially laminating a gate electrode and a gate electrode thin film for gate wiring, a gate insulating film, a first oxide layer, and a first resist on the substrate;
Using the first halftone mask, the step of forming the first resist into a predetermined shape by halftone exposure;
Etching the gate electrode / wiring thin film, the gate insulating film and the first oxide layer to form the gate electrode and the gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the first oxide layer above the gate wiring; and
A step of oxidizing the gate electrode and the gate wiring by anodic oxidation;
A step of sequentially laminating a second oxide layer, an auxiliary conductive layer, and a second resist;
Using the second halftone mask, the step of forming the second resist into a predetermined shape by halftone exposure;
Etching the auxiliary conductive layer and the second oxide layer to form a source electrode, a drain electrode, a source wiring, a drain wiring and a pixel electrode, and a channel portion;
Re-forming the second resist into a predetermined shape;
Selectively etching the auxiliary conductive layer on the pixel electrode to expose the pixel electrode;
A step of sequentially stacking a protective insulating film and a third resist;
Etching the protective insulating film using a third mask to expose the source / drain wiring pad, the gate wiring pad, and the pixel electrode. A step of sequentially laminating a gate electrode and a thin film for wiring to be a gate wiring, a gate insulating film, a first oxide layer, a second oxide layer, and a first resist on a substrate;
Using the first halftone mask, the step of forming the first resist into a predetermined shape by halftone exposure;
Etching the gate electrode / wiring thin film, the gate insulating film, the first oxide layer and the second oxide layer to form the gate electrode and the gate wiring;
Re-forming the first resist into a predetermined shape;
Etching the second oxide layer and the first oxide layer above the gate wiring; and
A step of oxidizing the gate electrode and the gate wiring by anodic oxidation;
A step of sequentially laminating a third oxide layer, an auxiliary conductive layer, and a second resist;
Using the second halftone mask, the step of forming the second resist into a predetermined shape by halftone exposure;
Etching the auxiliary conductive layer, the third oxide layer, and the second oxide layer to form a source electrode, a drain electrode, a source wiring, a drain wiring, a pixel electrode, and a channel portion;
Re-forming the second resist into a predetermined shape;
Selectively etching the auxiliary conductive layer on the pixel electrode to expose the pixel electrode;
A step of sequentially stacking a protective insulating film and a third resist;
Etching the protective insulating film using a third mask to expose the source / drain wiring pad, the gate wiring pad, and the pixel electrode.   11. The method for manufacturing a TFT substrate according to claim 9, wherein a metal oxide layer for an auxiliary conductive layer that protects the auxiliary conductive layer is formed on the auxiliary conductive layer.

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