CN102165569A - Process for producing field effect transistor - Google Patents
Process for producing field effect transistor Download PDFInfo
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- CN102165569A CN102165569A CN2009801378486A CN200980137848A CN102165569A CN 102165569 A CN102165569 A CN 102165569A CN 2009801378486 A CN2009801378486 A CN 2009801378486A CN 200980137848 A CN200980137848 A CN 200980137848A CN 102165569 A CN102165569 A CN 102165569A
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- 238000004544 sputter deposition Methods 0.000 claims abstract description 23
- 229910007541 Zn O Inorganic materials 0.000 claims abstract description 17
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- 238000004519 manufacturing process Methods 0.000 claims description 21
- 238000006243 chemical reaction Methods 0.000 claims description 3
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- 238000005477 sputtering target Methods 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
Abstract
A process for producing a field effect transistor is provided which can attain an improvement in transistor characteristics without the need of high-temperature annealing. An In-Ga-Zn-O thin film constituting an active layer is formed by sputtering at a film deposition temperature of 100 DEG C or higher. Thereafter, the thin film is annealed in the air at 300 DEG C. The annealing is conducted in order to improve the transistor characteristics of the active layer which has just been deposited. The In-Ga-Zn-O thin film deposited by sputtering while heating the substrate is reduced in internal strain and defects as compared with an In-Ga-Zn-O thin film deposited without heating. Consequently, the In-Ga-Zn-O thin film formed as an active layer with heating is capable of being more effectively annealed than an active layer of the same material deposited without heating. Thus, an active layer having excellent transistor characteristics can be formed through low-temperature annealing.
Description
Technical field
The present invention relates to a kind of manufacture method with field-effect transistor of active layer, this active layer is formed by InGaZnO based semiconductor oxide.
Background technology
In recent years, people are extensive use of active matrix liquid crystal display.Each pixel of this active matrix liquid LCD has the field effect thin-film transistor (TFT) as switch element.
The known thin-film transistor that following kind is arranged of people, that is, and the amorphous silicon film transistor that polycrystalline SiTFT that active layer is made of polysilicon and active layer are made of amorphous silicon.
Compare with polycrystalline SiTFT, amorphous silicon film transistor have that active layer is easy to make and can be on bigger substrate the even advantage of film forming.
Because transparent amorphous oxides film is compared with amorphous silicon, the mobile degree of its charge carrier (electronics, hole) is higher, and as active layer material, people develop it.For example, in patent documentation 1, record a kind of field-effect transistor, its active layer has used Compound I nMO of the same clan
3(ZnO)
m(M=In, Fe, Ga or Al, m are the integer of 1 above less than 50).In addition, in patent documentation 2, record the manufacture method that a kind of In-Ga-Zn-O of being formed with is the field-effect transistor of active layer, to by having InGaO
3(ZnO)
4The target that the polycrystalline sintered body of composition constitutes carries out sputter processing and forms this In-Ga-Zn-O is active layer.
The open communique spy of [patent documentation 1] Japanese patent of invention opens ([0010] section) 2004-103957 number
The open communique spy of [patent documentation 2] Japanese patent of invention opens ([0103]～[0119] section) 2006-165527 number
Under the state that has just formed, do not have practical transistor characteristic (conducting current characteristics, cut-off current characteristic, ON/OFF current ratio etc.) owing to have the active layer of In-Ga-Zn-O set member, so after forming active layer, will under suitable temperature, carry out annealing in process.Annealing temperature is high more can to obtain transistor characteristic preferably more.
But the upper limit of annealing temperature is subject to the heat resisting temperature of the effect film (electrode film, dielectric film) outside employed base material or the active layer.Therefore, consider the thermal endurance of these structure sheafs, occur following problem sometimes, that is, can't obtain required transistor characteristic because of annealing grade is insufficient.
Summary of the invention
In view of the foregoing, the object of the present invention is to provide a kind of manufacture method of field-effect transistor, it need not to carry out The high temperature anneal also can improve transistor characteristic.
To achieve these goals, on one side the manufacture method of the described field-effect transistor of one embodiment of the present invention comprises that heated substrate adopts sputtering method to form the operation of active layer on this base material on one side, wherein, active layer has the In-Ga-Zn-O set member.Formed described active layer is carried out annealing in process.
Description of drawings
Fig. 1 is the profile at the main position of each operation in the manufacture method of the described field-effect transistor of expression explanation embodiment of the present invention.
Fig. 2 is the profile at the main position of each operation in the manufacture method of the described field-effect transistor of expression explanation embodiment of the present invention.
Fig. 3 is the profile at the main position of each operation in the manufacture method of the described field-effect transistor of expression explanation embodiment of the present invention.
Fig. 4 is the profile at the main position of each operation in the manufacture method of the described field-effect transistor of expression explanation embodiment of the present invention.
Fig. 5 is the profile at the main position of each operation in the manufacture method of the described field-effect transistor of expression explanation embodiment of the present invention.。
Fig. 6 is evaluation the conducting current characteristics of sample and the experimental result of cut-off current characteristic that the expression embodiment of the present invention will illustrate.
Fig. 7 is the simulated section figure of the expression embodiment of the present invention evaluation that will illustrate with sample.
Fig. 8 is the evaluation annealing conditions of sample and the experimental result of the relation between the switch current ratio that the expression embodiment of the present invention will illustrate.
Embodiment
The manufacture method of the described field-effect transistor of one embodiment of the present invention comprises that heated substrate adopts sputtering method to form the operation of active layer on this base material on one side on one side, and wherein, active layer has the In-Ga-Zn-O set member.Formed described active layer is carried out annealing in process.
The purpose of implementing annealing in process is to improve the transistor characteristic of the active layer that has just formed.Compare with the In-Ga-Zn-O film that forms without heating, on one side heated substrate adopt sputtering method on one side and the internal strain or the defective of the In-Ga-Zn-O film that forms are less.Therefore, compare with the In-Ga-Zn-O film that forms without heating, the same material film that will form through heating can improve the annealing effect during as active layer.Thereby the present invention can handle the active layer that forms the transistor characteristic with excellence by process annealing.
Comparatively typical base material is a glass substrate.Size to this base material does not have particular determination.
The film-forming temperature of above-mentioned active layer can be more than 100 ℃.
Therefore, compare with the active layer that forms without heating, the present invention can reduce annealing temperature required when giving the regulation transistor characteristic.In addition, film-forming temperature is not limited to 100 ℃, can be according to the membrance casting condition appropriate change.Heater as heated substrate is used can use heating tube or heating lamp.
The annealing temperature of above-mentioned active layer also can be more than 300 ℃.The annealing in process pressure of above-mentioned active layer can be standard atmospheric pressure, can also be lower than standard atmospheric pressure.Processing environment can be in air, also can be in oxygen atmosphere.
According to experimental result that the present inventor did as can be known, resulting result compares when carrying out annealing in process with the active layer that will form without heating in 400 ℃ of conditions and atmosphere, and the active layer that forms through heating can obtain identical switch current ratio (conducting electric current/cut-off current) when carrying out annealing in process in 300 ℃ of conditions and atmosphere.Hence one can see that, compares with the active layer that forms without heating, and the active layer of the same material that forms through heating is handled by process annealing can form the active layer with excellent transistor characteristic.
In forming the operation of above-mentioned active layer, also can adopt can with oxidizing gas (O for example
2, O
3, H
2Deng) sputtering method that chemical reaction takes place forms above-mentioned active layer.
For the sputtering target that forms the In-Ga-Zn-O film can use simple In-Ga-Zn-O target, also can use In
2O
3Target, Ga
2O
3A plurality of targets such as target, ZnO target.The processing of the spatter film forming that carries out in oxygen atmosphere when controlling, can easily be controlled the oxygen concentration in the film to the oxygen pneumatic (flow) that imports.
Above-mentioned base material comprises grid, also can form the gate insulating film that is used for covering described grid before forming above-mentioned active layer.
Can be made into the bottom gate type field-effect transistor thus.Grid also can be formed in the electrode film on the base material, also can adopt the structure of base material as grid itself.
The diaphragm that covers above-mentioned active layer be can form, and the source electrode and the drain electrode of this active layer of contact formed.Can adopt sputtering method to form diaphragm.
Embodiments of the present invention are described below with reference to the accompanying drawings.
[first execution mode]
Fig. 1～Fig. 5 is the profile at main position of each operation of the manufacture method of the described field-effect transistor of expression explanation first embodiment of the invention.The manufacture method of the field-effect transistor with so-called bottom gate type transistor arrangement is described in the present embodiment.
Shown in (A) among Fig. 1, at first form gate electrode film 11F on a surface of base material 10.
Comparatively typical base material 10 is a glass substrate.Comparatively typical gate electrode film 11F is made of the metal single layer film or the metallized multilayer film of molybdenum, chromium, aluminium etc., and it for example adopts sputtering method to form.Thickness to gate electrode film 11F does not have particular determination, and for example it is 300nm.
Next shown in (D) among (B)～Fig. 1 among Fig. 1, gate electrode film 11F is processed into the pattern with regulation shape forms with mask 12 against corrosion.This operation has photoresist film 12F and forms operation (among Fig. 1 (B)), exposure process (among Fig. 1 (C)), developing procedure (among Fig. 1 (D)).
Make it dry after being coated in the liquid photosensitive material on the gate electrode film 11F and form photoresist film 12F.Also can use dry type film resist as photoresist film 12F.After exposing, 13 couples of formed photoresist film 12F of mask can develop.Therefore, can on gate electrode film 11F, form mask 12 against corrosion.
Then shown in (E) among Fig. 1, as mask gate electrode film 11F is carried out etching and processing with mask 12 against corrosion.Therefore, can form grid 11 on the surface of base material 10.
Engraving method to gate electrode film 11F does not have particular determination, can adopt wet etching, can adopt the dry-etching method yet.Remove mask 12 against corrosion after the etching and processing.The method of removing mask 12 against corrosion is suitable for the ashing treatment of oxygen plasma, but present embodiment is not limited thereto, and also can adopt the method for removing with soup.
Next, shown in (A) among Fig. 2, but form the gate insulating film 14 of cover gate 11 on one of base material 10 surface.
Comparatively typical gate insulating film 14 is by silicon oxide film (SiO
2), silicon nitride film (SiN
x) wait oxide-film or nitride film to constitute, it is CVD method or the formation of employing sputtering method for example.Thickness to gate electrode film 11F does not have particular determination, and for example it is 200～500nm.
Next shown in (B) among Fig. 2, on gate insulating film 14, form film (being designated hereinafter simply as " IGZO film ") 15F and barrier layer successively and form film 16F with In-Ga-Zn-O set member.Adopt sputtering method to form IGZO film 15F and barrier layer formation film 16F.Can form IGZO film 15F and barrier layer continuously and form film 16F.At this moment, the sputtering target that is used for forming the sputtering target of IGZO film 15F and is used for forming barrier layer formation film 16F also can be set in same sputter cavity.By switching employed target, can independently form IGZO film 15F or barrier layer and form film 16F.
Under the state that base material 10 is heated to set point of temperature, form IGZO film 15F.The heating-up temperature of base material 10 is for example more than 100 ℃.In the present embodiment, the sputtering method that employing can produce chemical reaction forms active layer 15 (IGZO film 15F), wherein, and by in oxygen atmosphere, target being carried out sputter and will being deposited on the base material 10 with the reactant that oxygen reacts.Discharge type can be any in DC discharge, AC discharge, the RF discharge.In addition, also can adopt the magnetron discharge method that permanent magnet is set in the rear side of target.
IGZO film 15F and barrier layer formation film 16F thickness are not separately had particular determination, and for example the thickness of IGZO film 15F is 50～200nm, and the thickness that the barrier layer forms film 16F is 30～300nm.
Active layer (current-carrying layer) 15 by IGZO film 15F transistor formed.The metal film pattern that constitutes source electrode and drain electrode in aftermentioned forms operation; with adopt processing method to remove in the operation of unwanted part of IGZO film 15F, the barrier layer forms film 16F and plays the etch protection layer effect of trench region of protection IGZO film to prevent etched dose of erosion.The barrier layer forms film 16F for example by SiO
2Constitute.
Next, shown in (D) among (C) and Fig. 2 among Fig. 2, the barrier layer is formed film 16F be processed into the pattern with regulation shape and form with behind the mask 27 against corrosion, 16F carries out etching and processing through 27 pairs of barrier layers formation of this mask against corrosion film.Therefore, can form the barrier layer 16 that clips gate insulating film 14 and IGZO film 15F and face with grid 14.
Shown in (E) among Fig. 2, remove the metal film 17F that mask 27 back formation against corrosion can cover IGZO film 15F and barrier layer 16.
Comparatively typical metal film 17F is made of the metal single layer film or the metallized multilayer film of molybdenum, chromium, aluminium etc., and it for example adopts sputtering method to form.Thickness to metal film 17F does not have particular determination, and for example it is 100～500nm.
Then shown in (B) among (A) and Fig. 3 among Fig. 3, metal film 17F is carried out pattern form processing.
The pattern of metal film 17F forms operation and has the formation operation (among Fig. 3 (A)) of mask 18 against corrosion and the etching work procedure (among Fig. 3 (B)) of metal film 17F.Mask 18 against corrosion has area just above and the uncovered mask pattern in each transistorized peripheral region that makes barrier layer 16.Forming mask against corrosion 18 backs adopts wet etching that metal film 17F is carried out etching and processing.Therefore, metal film 17F is separated into source electrode 17S and drain electrode 17D.In addition, in explanation after this, also source electrode 17S and drain electrode 17D are generically and collectively referred to as source/drain electrode 17 sometimes.
In source/drain electrode 17 formation operations, the effect of the etch stop layer of metal film 17F is played on barrier layer 16.Barrier layer 16 forms in the mode that covers the zone (hereinafter referred to as " trench region ") between source electrode 17S on the IGZO film 15F and drain electrode 17D.Therefore, the trench region of IGZO film 15F is unaffected in the etching work procedure of metal film 17F.
Next, shown in (D) among (C) and Fig. 3 among Fig. 3, be that mask carries out etching and processing to IGZO film 15F with mask 18 against corrosion.
Engraving method is not had particular determination, can adopt wet etching, can adopt the dry-etching method yet.Through the etching work procedure of this IGZO film 15F, IGZO film 15F promptly can be that unit is isolated with the element, can form the active layer 15 that is made of IGZO film 15F again.
At this moment, the effect of the etching protective film of the IGZO film 15F that is positioned at trench region is played on barrier layer 16.Therefore, the trench region of active layer 15 is unaffected in the etching work procedure of IGZO film 15F.
After the pattern of IGZO film 15F forms processing, adopt method such as ashing treatment from the source/drain electrode 17 removal masks 18 against corrosion (Fig. 3 (D)).
Next shown in (A) among Fig. 4, form the diaphragm (passivating film) 19 that can cover source/drain electrode 17, barrier layer 16, active layer 15, gate insulating film 14 on the surface of base material 10.
Then shown in (D) among (B)～Fig. 4 among Fig. 4, on diaphragm 19, form the intercommunicating pore 19a that is communicated with source/drain electrode 17.This operation has the operation (among Fig. 4 (B)) that forms mask 20 against corrosion on diaphragm 19, the diaphragm 19 that the peristome 20a from mask 20 against corrosion is exposed carries out the operation (Fig. 4 (C)) of etching and processing, the operation (among Fig. 4 (D)) of removal mask 20 against corrosion.
Adopt the dry-etching method when forming intercommunicating pore 19a, but also can adopt wet etching.In addition, though omitted its diagram, be formed with the contact hole that is connected with source electrode 17S equally on the desired position arbitrarily.
Next, shown in (D) among (A)～Fig. 5 among Fig. 5, through the nesa coating 21 that intercommunicating pore 19a forms with the source/drain electrode 17 contacts.This operation has the operation (among Fig. 5 (A)) that forms transparent conductive film 21F, the operation (among Fig. 5 (B)) that forms mask 22 against corrosion on transparent conductive film 21F, the transparent conductive film 21F that is not covered by mask 22 against corrosion is carried out the operation (among Fig. 5 (C)) of etching and processing, the operation (among Fig. 5 (D)) of removal mask 20 against corrosion.
Comparatively typical transparent conductive film 21F is made of ITO film or IZO film, and it for example adopts sputtering method, CVD method to form.Adopted wet etching when transparent conductive film 21F is carried out etching and processing, but present embodiment is not limited thereto, also can adopts the dry-etching method.
Afterwards the transistor unit that is formed with nesa coating 21 shown in (D) among Fig. 5 100 is carried out annealing in process, its purpose is to relax the stress of active layer 15.Therefore, do like this and can give active layer 15 needed transistor characteristics.
By above each step, promptly can be made into field-effect transistor.
In the present embodiment, under the state that base material 10 is heated to set point of temperature, form the IGZO film 15F that constitutes active layer 15.Compare with the IGZO film that forms without heating, less as internal strain or the defective in the film of the above-mentioned IGZO film 15F that forms through heating.Compare with the active layer that forms without heating, by through heating and the IGZO film 15F that forms can obtain the transistor characteristic (conducting current characteristics, cut-off current characteristic, switch current ratio etc.) of excellence during as active layer 15.
The present inventor has measured the current characteristics (conducting current value, cut-off current value) of following three active layer samples respectively, and described three active layer samples are that heating-up temperature is that active layer (sample 1), the heating-up temperature that adopts sputtering method to form under 100 ℃ of conditions is to adopt the active layer (sample 2) of sputtering method formation and the active layer (sample 3) that adopts sputtering method to form without heating under 200 ℃ of conditions.Its experimental result of expression among Fig. 6.Oxygen pneumatic when transverse axis is for the formation film among the figure, the longitudinal axis is a current value.In addition, the conducting current value of " ● " expression sample 1 among the figure, the cut-off current value of " zero " expression sample 1, the cut-off current value of the conducting current value of " ◆ " expression sample 2, " ◇ " expression sample 2, the cut-off current value of the conducting current value of " ▲ " expression sample 3, " △ " expression sample 3.
Substrate temperature difference when just forming active layer in the membrance casting condition of sample 1, sample 2, sample 3, sample 1 are that 100 ℃, sample 2 are that 200 ℃, sample 3 are room temperature.The power of sputter cathode is that to handle gas be that mist, the ar pressure of argon gas and oxygen is constant 0.74Pa (flow: 230sccm) to the film forming of 0.6kW (DC), active layer.In addition, measure substrate temperature according to the output valve that is installed in the thermocouple on the substrate.
Fig. 7 is the simulated section figure of the structure of expression sample 1～3.Transistor unit in the sample 1～3 is by as the p type silicon substrate of grid 31, as the silicon nitride film of gate insulating film 32, as the IGZO film of active layer 33, constitute and adopt laminar structure as the aluminium film of source/drain electrode 34S, 34D.Adopt the CVD method to form gate insulating film 32, its thickness is 350nm.Adopt sputtering method to form active layer 33, its thickness is 50nm.
Above-mentioned this transistor unit has the function of following switch element,, is controlled at the size of the electric current (electric current I ds between source electrode-drain electrode) that flows between source electrode 34S and the drain electrode 34d through the size that control imposes on the voltage of grid 31 that is.Especially because its operation principle is to change the interior groove distribution situation of active layer according to the size that acts on the electric field between the gate-to-source, and control the size of the electric current between source electrode-drain electrode with this, so this transistor unit is called as field-effect transistor.
Experimental result shown in Fig. 6 is the current characteristics after active layer 33 has just formed, and does not implement annealing in process this moment.In addition each component size of sample 1, sample 2, sample 3, estimate the circuit that electrical characteristic uses structure all identical.The size of electric current (Ids) between the source electrode-drain electrode when the conducting current value means grid voltage (Vgs) and is higher than threshold voltage (Vth).The cut-off current value means the size of electric current (Ids) between the source electrode-drain electrode of grid voltage (Vgs) when being lower than threshold voltage.In general, as transistor characteristic, people require the conducting current value big and the cut-off current value is little, perhaps require the bigger of conducting current value/cut-off current value.
Shown in the experimental result among Fig. 6, therefrom can confirm for sample 1, sample 2, sample 3, their conducting current value changes along with the different of the oxygen pneumatic in the film forming environment with the cut-off current value.Especially can confirm following a kind of trend, that is, in the sample 1～3 any one, low more its conducting current value of oxygen pneumatic and cut-off current value are big more.
When comparative sample 1, sample 2 and sample 3, compare with the sample 3 with the active layer that forms without heating, the conducting current value with the sample 1 of the active layer that forms through heating and sample 2 is bigger.When this situation can be estimated as and form active layer by heating, strain and defective in the active layer are reduced, can improve the mobile degree in charge carrier (electronics, hole) like this.
In addition, can confirm it significantly from sample 1 and show following trend, that is, its cut-off current value also descends along with the increase of oxygen pneumatic, and especially its cut-off current value reduces to 1.0 * 10 when oxygen pneumatic is 0.28Pa
-14(A).The insulation property that this situation can be estimated as active layer strengthen along with the increase of oxygen pneumatic, can cause the decline of cut-off current value like this.
Also have, can confirm when comparative sample 1 and sample 2, when oxygen pneumatic was 0.02Pa, the conducting current value of sample 1 and cut-off current value be big than sample 2 all, but when oxygen pneumatic was 0.03～0.28Pa, the conducting current value of sample 2 and cut-off current value be big than sample 1 all then.The reason that difference appears in the conducting between sample 1 and the sample 2/cut-off current value is that film forming adds the difference of the heating-up temperature in man-hour.At least (below the above 0.28Pa of 0.02Pa) can confirm under the oxygen pneumatic condition in experiment, compares with the sample 3 with the active layer that forms without heating, can improve current characteristics and switch current ratio when adopting sample 1 and sample 2.
As mentioned above, compare, can improve the conducting current value when forming active layer with In-Ga-Zn-O composition through heating with the situation that forms active layer without heating.Here to be 100 ℃ and 200 ℃ be that example is illustrated to the film-forming temperature that adds man-hour with sputter.But heating-up temperature is not limited to example, for example its can less than 100 degree, or surpass 200 ℃ of 100 ℃ and less thaies, or surpass 200 ℃ and also can.That is, can suitably set heating-up temperature according to required transistor characteristic.
In addition, when under heating environment, adopting sputtering method to form active layer 15, can in annealing operation thereafter, obtain to anneal preferably effect.The purpose of implementing annealing in process is to improve the transistor characteristic of the active layer that has just formed.Compare with the situation that forms active layer without heating, owing to the internal strain or the defective of the active layer 15 that forms through heating are less, so it has higher sensitiveness for the heat of coming from exterior conductive, this temperature during to further reduction annealing in process has facilitation.
For Fig. 6 and illustrated sample 1, sample 2 and the sample 3 of Fig. 7, to be expression carry out the experimental result of the switch current ratio that records before and after the annealing in process respectively to them to Fig. 8.Estimating with sample is that to have in oxygen pneumatic be to adopt the sample of the active layer of sputtering method formation under the 0.28Pa condition.Annealing temperature be respectively 200 ℃, 300 ℃, 400 ℃, annealing in process environment all be in atmosphere, annealing time is 15 minutes.The switch current ratio of the switch current ratio of " ● " expression sample 1 among the figure, the switch current ratio of " ◆ " expression sample 2, " ▲ " expression sample 3.
For sample 3, under 400 ℃ of conditions, obtained to surpass the switch current ratio of 7 figure places with the active layer that forms without heating.With respect to this, for having the sample 1 and sample 2 that adopts the active layer that sputtering method forms under 100 ℃ and 200 ℃ of conditions, they have just obtained to reach the switch current ratio of 8 figure places under 300 ℃ of conditions.
From experimental result shown in Figure 8 as can be seen, be to obtain and sample 3 equal above switch current ratio, compare, the annealing in process temperature can be reduced to when employing sample 1 and sample 2 than the former and also hang down degree below 100 ℃ with the annealing in process temperature that sample 3 is required.Therefore, the active layer that forms through heating is when just forming, and because of the less cause of strain or defective in its film, its atom can have higher response to the heat load from the outside and spread.Therefore, even also can obtain transistor characteristic preferably to the lower heat load of temperature.
When especially adopting sample 1 and sample 2, owing to also obtaining transistor characteristic preferably under the temperature conditions that can be lower than sample 3, even so make treatment temperature limited because of the thermal endurance of the effect film outside base material or the active layer (electrode film, dielectric film), also have the following advantages when adopting sample 1 and sample 2, that is, be easy to obtain transistor characteristic preferably as the object of the invention by them.
In addition, when sample 1 and sample 2 being carried out annealing in process, can further improve switch current ratio with the high temperature that surpasses 300 ℃.Therefore, consider element thermal endurance etc. and adopt and be same as without heating when film forming annealing conditions carries out annealing in process, can further improve electrical characteristic.For example can make annealing temperature be more than 300 ℃ and 400 ℃ of less thaies.In addition, owing to can occur the problem of bag (the trickle projection of formation on the surface) when being formed from aluminium grid, and can control this generation of defects effectively when the upper limit of annealing temperature is set at 350 ℃.
Embodiments of the present invention more than have been described, the present invention is not limited to above-mentioned execution mode certainly, in the scope that does not break away from purport of the present invention, can carry out various modification to it.
For example, the manufacture method with the bottom gate type field-effect transistor is that example is illustrated in the above-described embodiment, and its grid is formed on lower floor's one side of active layer.But the present invention is not limited thereto, and in the manufacture method of the present invention applicable to the top gate type field-effect transistor, its grid is formed on upper strata one side of active layer.
In addition, in the above-described embodiment, the film-forming temperature of active layer 15 (IGZO film 15F) is more than 100 ℃, and the annealing temperature behind the formation active layer 15 is 300 ℃.But the present invention is not limited thereto, can be according to the transistor characteristic appropriate change film-forming temperature and the annealing temperature of required element.
[description of reference numerals]
10, base material; 11, grid; 14, gate insulating film; 15, active layer; 16, the barrier layer; 17 (17S, 17D), source/drain electrode; 19, diaphragm
Claims (6)
1. the manufacture method of a field-effect transistor is characterized in that,
Heated substrate adopts sputtering method to form active layer on one side on described base material on one side, and wherein, this active layer has the In-Ga-Zn-O set member,
Formed described active layer is carried out annealing in process.
2. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
The operation that forms described active layer comprises: with the temperature heated substrate more than 100 ℃ and form described active layer.
3. the manufacture method of field-effect transistor as claimed in claim 2 is characterized in that,
The operation of described active layer being carried out annealing in process comprises: with the temperature more than 300 ℃ described base material is heated.
4. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
Form in the operation of above-mentioned active layer and comprise: employing can form described active layer with the sputtering method of oxidizing gas generation chemical reaction.
5. the manufacture method of field-effect transistor as claimed in claim 1 is characterized in that,
Described base material comprises grid,
Before forming described active layer, form the gate insulating film that covers described grid.
6. the manufacture method of field-effect transistor as claimed in claim 5 is characterized in that,
Form the diaphragm that covers described active layer,
Form the source electrode and the drain electrode of this active layer of contact.
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