CN108288651B - Method for preparing all-transparent top gate structure thin film transistor through all-magnetron sputtering - Google Patents
Method for preparing all-transparent top gate structure thin film transistor through all-magnetron sputtering Download PDFInfo
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- 238000001755 magnetron sputter deposition Methods 0.000 title claims abstract description 43
- 239000010409 thin film Substances 0.000 title claims abstract description 35
- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 238000000151 deposition Methods 0.000 claims abstract description 22
- 238000002360 preparation method Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000004544 sputter deposition Methods 0.000 claims description 25
- 239000013077 target material Substances 0.000 claims description 6
- 238000009413 insulation Methods 0.000 claims description 2
- 238000005286 illumination Methods 0.000 abstract description 12
- 238000000137 annealing Methods 0.000 abstract description 3
- 238000001816 cooling Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 10
- 238000013112 stability test Methods 0.000 description 5
- 238000012360 testing method Methods 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000026058 directional locomotion Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
Abstract
The invention belongs to the technical field of thin film transistors and discloses a method for preparing a thin film transistor with a full-transparent top gate structure by full magnetron sputtering. Depositing a layer of Al on the substrate by using radio frequency magnetron sputtering in sequence at room temperature2O3A buffer layer, depositing a Nd-IZO semiconductor layer by radio frequency magnetron sputtering, depositing an ITO source drain electrode by direct current magnetron sputtering, and depositing an Al layer by radio frequency magnetron sputtering2O3A grid insulating layer, and depositing an ITO grid electrode by using direct current magnetron sputtering; and (3) carrying out thermal annealing on the whole device for 1h at 350-400 ℃ in an atmospheric environment, and naturally cooling to obtain the full-transparent top-gate structure thin film transistor. The method can realize the preparation of the top gate structure thin film transistor only by using magnetron sputtering equipment, and the device has excellent positive and negative bias stability and illumination stability.
Description
Technical Field
The invention belongs to the technical field of thin film transistors, and particularly relates to a method for preparing a full-transparent top gate structure thin film transistor through full magnetron sputtering.
Background
A Thin Film Transistor (TFT) is a three-terminal active semiconductor device with a wide application range, and the most important application is to drive the liquid crystal alignment change and the OLED pixel to emit light in a display.
The thin film transistor controls carriers of a semiconductor layer semiconductor by a gate voltage, thereby realizing an on or off state of the device. Wherein the source and drain electrodes in the thin film transistor provide a voltage to drive the directional movement of the carriers to form a current. The existing thin film transistor mainly comprises amorphous silicon, polycrystalline silicon and metal oxide thin film transistors. However, amorphous silicon has low mobility, polysilicon has high preparation cost and poor uniformity, and oxide thin film transistors have the advantages of high mobility, good uniformity, low cost and the like, and are widely studied in recent years. However, the bias stability and the light stability of the oxide thin film transistor have a great problem due to interface defects and various defects in the semiconductor. The method for preparing the thin film transistor mainly comprises the methods of magnetron sputtering, radio frequency pulse deposition, atomic layer deposition, chemical vapor deposition and the like, the radio frequency pulse deposition and the atomic layer deposition equipment are expensive and have low film forming rate, the processes of the chemical vapor deposition and the like are complex and need high temperature, the magnetron sputtering method has the advantages of simple instrument and equipment, simple process, no pollution to the environment, less consumable materials, uniform and compact film forming, large-area preparation, good uniformity and the like, and the investment of the instrument and equipment and the resource consumption can be greatly reduced by adopting full sputtering. Most of the existing all-sputtering devices adopt a bottom gate structure, researches show that a metal oxide semiconductor is extremely sensitive to water and oxygen in the air, and in order to improve the stability of the devices, the bottom gate structure devices often need to deposit a passivation layer to protect an active layer from being influenced by the water and oxygen, so that the process steps are increased. However, the semiconductor layer of the top gate structure device is deposited before the insulating layer, and the insulating layer deposited subsequently can protect the semiconductor layer from being corroded by water and oxygen in the air, so that the stability of the top gate structure device is obviously superior to that of the bottom gate structure device. Therefore, the development of the full-magnetron sputtering top gate structure thin film transistor has good application prospect.
Disclosure of Invention
Aiming at the defects and shortcomings of the prior art, the invention mainly aims to provide a method for preparing a full-transparent top gate structure thin film transistor through full magnetron sputtering.
The invention also aims to provide a full-transparent top-gate structure thin film transistor prepared by the method.
The purpose of the invention is realized by the following technical scheme:
a method for preparing a thin film transistor with a full-transparent top gate structure by full magnetron sputtering comprises the following preparation steps:
(1) depositing a layer of Al on the substrate by radio frequency magnetron sputtering at room temperature2O3A buffer layer;
(2) sputtering Al at room temperature by radio frequency magnetron2O3Depositing a graphical Nd-IZO semiconductor layer on the buffer layer;
(3) depositing a layer of graphical ITO source and drain electrodes on two sides of the semiconductor layer by using direct current magnetron sputtering at room temperature, wherein the source and drain electrodes are partially overlapped with the semiconductor layer;
(4) depositing a layer of graphical Al at room temperature by radio frequency magnetron sputtering2O3The grid insulating layer completely covers the semiconductor layer, partially covers the source and drain electrodes and exposes the leading-out wires of the source and drain electrodes;
(5) depositing a layer of graphical ITO gate electrode on the upper surface of the gate insulating layer by using direct-current magnetron sputtering at room temperature, wherein the ITO gate electrode is partially overlapped with the ITO source drain electrode;
(6) and (3) carrying out thermal annealing on the whole device for 1h at 350-400 ℃ in an atmospheric environment, and naturally cooling to obtain the full-transparent top-gate structure thin film transistor.
Preferably, the Al2O3The thickness of the buffer layer is 27-50 nm, the thickness of the Nd-IZO semiconductor layer is 7-15 nm, the thickness of the ITO source drain electrode is 100-150 nm, and the Al is2O3The thickness of the grid insulation layer is 250-300 nm, and the thickness of the ITO grid electrode is 100-150 nm.
Preferably, the background vacuum degree of the radio frequency magnetron sputtering in the step (1) and the step (4) is 4 x 10-6mTorr, bombardment of Al with Ar ions2O3The sputtering pressure of the target material is 1mTorr, O2The flow ratio/Ar was 0%, and the sputtering power was 120W.
Preferably, the method of radio frequency magnetron sputtering in the step (2)The degree of vacuum at the bottom is 4X 10-6mTorr, bombarding Nd-IZO target with Ar ion and sputtering pressure of 5mTorr and O2The flow ratio/Ar was 5%, and the sputtering power was 80W.
Preferably, the background vacuum degree of the direct current magnetron sputtering in the step (3) and the step (5) is 4 x 10-6mTorr, Ar ion bombarding ITO target material at sputtering pressure of 5mTorr and O2The flow ratio/Ar was 0%, and the sputtering power was 100W.
A full-transparent top-gate structure thin film transistor is prepared by the method.
Compared with the prior art, the invention has the following advantages and beneficial effects:
the invention provides a preparation method of a high-stability top gate structure metal oxide thin film transistor device, which can realize the preparation of a top gate structure thin film transistor only by using magnetron sputtering equipment, and the device has excellent positive and negative bias stability and illumination stability.
Drawings
Fig. 1 is a schematic diagram of a laminated structure of a fully transparent top-gate thin film transistor according to an embodiment of the present invention, where 01-a substrate, 02-a buffer layer, 03-a semiconductor layer, 04-source and drain electrodes, 05-a gate insulating layer, and 06-a top-gate electrode.
Fig. 2 is a graph of output characteristics of the fully transparent top-gate thin film transistor obtained in the embodiment of the present invention at different voltages.
Fig. 3 is a diagram illustrating the negative bias voltage (NBS) stability test result of the fully transparent top-gate thin film transistor according to the embodiment of the present invention.
Fig. 4 is a diagram illustrating the results of testing the stability of the forward bias voltage (PBS) of the fully transparent top-gate tft according to the embodiment of the present invention.
FIG. 5 is a diagram illustrating the Negative Bias Illumination (NBIS) stability test results of the fully transparent top-gate TFT according to the embodiment of the present invention.
FIG. 6 is a diagram illustrating the results of testing the stability of the forward bias illumination (PBIS) of the TFT with a fully transparent top gate structure according to the embodiment of the present invention.
Fig. 7 is a diagram illustrating a threshold voltage shift test result of the fully transparent top-gate thin film transistor according to the embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but the present invention is not limited thereto.
Examples
A schematic diagram of a laminated structure of the fully transparent top-gate thin film transistor of this embodiment is shown in fig. 1, and a buffer layer 02, a semiconductor layer 03, source-drain electrodes 04, a gate insulating layer 05, and a top gate electrode 06 are sequentially disposed on a substrate 01.
The fully transparent top-gate structure thin film transistor of the embodiment is prepared by the following method:
(1) depositing a layer of Al with the thickness of 27nm on a substrate by using radio frequency magnetron sputtering at room temperature2O3A buffer layer;
(2) sputtering Al at room temperature by radio frequency magnetron2O3Depositing a Nd-IZO semiconductor layer with the thickness of 7nm on the buffer layer;
(3) depositing a layer of ITO source and drain electrodes with the thickness of 140nm on two sides of the semiconductor layer by using direct current magnetron sputtering at room temperature, wherein the source and drain electrodes are partially overlapped with the semiconductor layer;
(4) depositing a layer of Al with the thickness of 290nm at room temperature by radio frequency magnetron sputtering2O3The grid insulating layer completely covers the semiconductor layer, partially covers the source and drain electrodes and exposes the leading-out wires of the source and drain electrodes;
(5) depositing a layer of ITO top gate electrode with the thickness of 140nm by using direct-current magnetron sputtering at room temperature, wherein the ITO top gate electrode is partially overlapped with the ITO source drain electrode;
(6) and (3) carrying out thermal annealing on the whole device for 1h at 400 ℃ in an atmospheric environment, and naturally cooling to obtain the full-transparent top-gate structure thin film transistor.
In this example, Al is described in step (1) and step (4)2O3Buffer layer and Al2O3The radio frequency magnetron sputtering conditions adopted by the gate insulating layer are as follows: background vacuum degree of 4X 10-6mTorr, bombardment of Al with Ar ions2O3The sputtering pressure of the target material is 1mTorr, O2Flow ratio of/Ar of 0%, sputteringThe power is 120W, and the sputtering time is 900s and 3.5h respectively.
In this embodiment, the direct-current magnetron sputtering conditions adopted by the ITO source/drain electrode layer and the ITO top gate electrode layer in step (3) and step (5) are as follows: background vacuum degree of 4X 10-6mTorr, Ar ion bombarding ITO target material at sputtering pressure of 5mTorr and O2The flow ratio/Ar was 0%, the sputtering power was 100W, and the sputtering time was 600 s.
The radio frequency magnetron sputtering conditions adopted by the Nd-IZO semiconductor layer in step (2) of this embodiment are as follows: background vacuum degree of 4X 10-6mTorr, bombarding Nd-IZO target with Ar ion and sputtering pressure of 5mTorr and O2The flow ratio/Ar was 5%, the sputtering power was 80W, and the sputtering time was 300 s.
The mobility of the all-transparent top-gate structure thin film transistor device obtained in the embodiment reaches 4.25 cm.V-1·S-1The subthreshold swing is 0.34V/decade, and the switching ratio reaches 106The threshold voltage was-0.97V.
The output characteristic curve of the all-transparent top-gate thin film transistor obtained in this embodiment under different voltages is shown in fig. 2, and it can be seen that the all-transparent top-gate thin film transistor exhibits good semiconductor characteristics.
The negative bias voltage (NBS) stability test result of the all-transparent top-gate thin film transistor obtained in this embodiment is shown in fig. 3, and it can be seen that the threshold voltage shifts by only-0.043V for 1 hour under the condition that the gate bias voltage is-10V, which indicates that the all-transparent top-gate thin film transistor has good negative bias voltage stability.
Fig. 4 shows a graph of the test result of the stability of the forward bias voltage (PBS) of the fully transparent top-gate thin film transistor obtained in this embodiment, and it can be seen that the threshold voltage shifts by only 0.076V for 1 hour under the condition that the gate bias voltage is +10V, which indicates that the device has good stability of the forward bias voltage.
Fig. 5 shows a Negative Bias Illumination (NBIS) stability test result diagram of the full-transparent top-gate thin film transistor obtained in this embodiment, which shows that a gate bias voltage is-10V, and a threshold voltage 1 shifts by-2.31V for a short time under illumination, and the shifting trend is weakened, which indicates that the device has better negative bias illumination stability.
Fig. 6 shows a Positive Bias Illumination (PBIS) stability test result diagram of the full-transparent top-gate thin film transistor obtained in this embodiment, which shows that a gate bias voltage is +10V, and a threshold voltage 1 shifts by-0.78V for a small time under illumination, and the shifting trend is weakened, which indicates that the device has better positive bias illumination stability.
Fig. 7 shows a threshold voltage shift test result diagram of the fully transparent top-gate thin film transistor obtained in this embodiment, which shows that the device has excellent positive and negative bias stability and good positive and negative bias illumination stability.
In conclusion, the all-transparent top-gate structure thin film transistor prepared by the all-magnetron sputtering method has good bias stability and good bias illumination stability, and the all-magnetron sputtering method preparation of the top-gate type thin film transistor with high stability and high performance is realized.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (5)
1. A method for preparing a thin film transistor with a full-transparent top gate structure by full magnetron sputtering is characterized by comprising the following preparation steps:
(1) depositing a layer of Al on the substrate by radio frequency magnetron sputtering at room temperature2O3A buffer layer;
(2) sputtering Al at room temperature by radio frequency magnetron2O3Depositing a graphical Nd-IZO semiconductor layer on the buffer layer;
(3) depositing a layer of graphical ITO source and drain electrodes on two sides of the semiconductor layer by using direct current magnetron sputtering at room temperature, wherein the source and drain electrodes are partially overlapped with the semiconductor layer;
(4) depositing a layer of graphical Al at room temperature by radio frequency magnetron sputtering2O3A gate insulating layer covering the semiconductor layer and partially covering the semiconductor layerA source/drain electrode, the source/drain electrode lead-out line being exposed;
(5) depositing a layer of graphical ITO gate electrode on the upper surface of the gate insulating layer by using direct-current magnetron sputtering at room temperature, wherein the ITO gate electrode is partially overlapped with the ITO source drain electrode;
(6) the whole device is thermally annealed for 1h at 350-400 ℃ in the atmospheric environment and naturally cooled to obtain a full-transparent top-gate structure thin film transistor;
the Al is2O3The thickness of the buffer layer is 27-50 nm, the thickness of the Nd-IZO semiconductor layer is 7-15 nm, the thickness of the ITO source drain electrode is 100-150 nm, and the Al is2O3The thickness of the grid insulation layer is 250-300 nm, and the thickness of the ITO grid electrode is 100-150 nm.
2. The method for preparing the thin film transistor with the fully transparent top gate structure by the fully magnetron sputtering according to claim 1, wherein the method comprises the following steps: the background vacuum degree of the radio frequency magnetron sputtering in the step (1) and the step (4) is 4 multiplied by 10-6mTorr, bombardment of Al with Ar ions2O3The sputtering pressure of the target material is 1mTorr, O2The flow ratio/Ar was 0%, and the sputtering power was 120W.
3. The method for preparing the thin film transistor with the fully transparent top gate structure by the fully magnetron sputtering according to claim 1, wherein the method comprises the following steps: the background vacuum degree of the direct current magnetron sputtering in the step (3) and the step (5) is 4 multiplied by 10-6mTorr, Ar ion bombarding ITO target material at sputtering pressure of 5mTorr and O2The flow ratio/Ar was 0%, and the sputtering power was 100W.
4. The method for preparing the thin film transistor with the fully transparent top gate structure by the fully magnetron sputtering according to claim 1, wherein the method comprises the following steps: the background vacuum degree of the radio frequency magnetron sputtering in the step (2) is 4 multiplied by 10-6mTorr, bombarding Nd-IZO target with Ar ion and sputtering pressure of 5mTorr and O2The flow ratio/Ar was 5%, and the sputtering power was 80W.
5. A full transparent top gate structure thin film transistor is characterized in that: prepared by the method of any one of claims 1 to 4.
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