CN102683423A - Metal oxide thin film transistor with top gate structure and manufacturing method thereof - Google Patents
Metal oxide thin film transistor with top gate structure and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a metal oxide thin film transistor with a top gate structure and a manufacturing method thereof. The thin film transistor comprises a substrate, an active layer, an insulating layer, a gate, a source and a drain, wherein the active layer is arranged on the substrate; the source is arranged at one end of the upper side of the active layer; the drain is arranged at the other end of the upper side of the active layer; the insulating layer is arranged in the middle of the upper side of the active layer; the gate is arranged on the insulating layer; a metallization layer is arranged between the active layer and the source; a metallization layer is also arranged between the active layer and the drain; and the active layer has a composite film structure and sequentially comprises an oxygen-poor metal oxide film layer and an oxygen-enriched metal oxide film layer from bottom to top. The active layer is made into the composite film layer through the same material and different processes, and the contact resistance in a source/drain electrode contact region is reduced through a metallization method; and the insulating layer is manufactured by employing an optimized sputtering process, and the plasma is prevented from damaging a channel active layer. Through the annealing treatment, the high-performance metal oxide thin film transistor with the top gate structure is obtained.
Description
Technical field
The present invention relates to a kind of thin-film transistor, particularly relate to a kind of top gate structure metal oxide thin-film transistor and preparation method thereof.
Background technology
Metal oxide thin-film transistor is mainly used in the active driving of organic light emitting display, liquid crystal display and Electronic Paper, also can be used for integrated circuit.
In recent years, based on the thin-film transistor of metal oxide because its mobility is high, light transmission is good, membrane structure is stable, the making temperature is low and low cost and other advantages receives increasing attention.Be the oxide semiconductor TFT technology of representative particularly, can realize higher resolution, then can improve yield, reduce cost and realize energy-conservationization with respect to LTPS TFT technology with respect to a-Si TFT with In-Ga-Zn-O (IGZO); In general, IGZO TFT technological synthesis superior performance has obtained a lot of breakthrough progress.
At present,, but still there is problem such as stability, uniformity, hinders its industrialization process though the development of IGZO technology has remarkable progress.Many seminar of industrial circle and academia launch research to IGZO rete technology of preparing; For example: people (Thin Solid Films such as Takafumi Aoi; 2010; 518 (11): 3004-3007) with people such as Dong Kyu Seo (Acta Materialia, 2011,59:6743-6750) report adopts different plated film mode (DC or RF) preparation IZGO films; People (Journal of Non-Crystalline Solids such as Hai Q.Chiang; 2008; 354:2826-2830), people (Thin Solid Films 2009 such as C.H.Jung; 517 (14): 4078 – 4081) and people such as C.J.Chiu (Vacuum, 2011,86 (3): 246-249) then studied the technology of preparing of IGZO respectively from filming parameters such as sputtering pressure, partial pressure of oxygen, power; South China Science & Engineering University's group proposes to adopt transition zone and semiconductor layer to improve the technology (application number: 201010182715.5) of oxide TFT characteristic specially to bottom grating structure.Also have seminar to report the treatment technology that improves after the active layer preparation; For example: people (Electrochemical and Solid-State Letters such as Seok-Jun Seo; 2010; 13 (10): H357-H359), people such as Soyeon Park (Journal of Nanoscience and Nanotechnology, 2011,11:6029-6033) with people (Thin Solid Films such as Chur-Shyang Fuh; 2011,520 (5): 1489-1494) the IGZO-TFT performance is optimized improvement through changing annealing conditions such as temperature, atmosphere, time.In addition; The optimization of channel protective layer preparation and material is also very crucial, people (Journal of Applied Physics, 2010 such as Antonis Olziersky; 108; 064505) and people such as Shou-En Liu (IEEE Electron Device Letters, 2011,32:161-163) production method and the material type through research raceway groove passivation layer.
To the research of IGZO oxide semiconductor TFT, most of device with bottom grating structure is main.In this structure,, after IGZO makes, be difficult to separately it carried out process modification, and other rete do not exerted an influence because active layer is positioned at the top of gate electrode and insulating barrier.And top gate structure TFT technology of preparing is had relatively high expectations, and has only minority enterprise or seminar adopting.For this structure, semiconductor active layer is in ground floor, can be optimized IGZO technology separately, and other rete is not had influence; And do not need follow-up etching barrier layer.Further, in the grid top contact structure of top, can handle active layer and interfacial dielectric layer better, reduce the boundary defect density of states, reduce the subthreshold value amplitude of oscillation, give full play to the characteristic that IGZO has high mobility; Simultaneously, can improve the contact interface of active layer and source/drain electrode, make it to form good Ohmic contact, reduce the current crowding phenomenon, thereby improve the output current of device, reduce driving voltage.But; For top gate structure, still there is the stability, uniformity problem, depositing insulating layer and electrode after the IGZO plated film; The subsequent film manufacture craft needs under vacuum or in the plasma atmosphere, to make; This can influence the microstructure of IGZO rete, and for example crystal grain is too small or excessive, and the crystal habit structure is inhomogeneous, unreasonable between the grain boundary; Even generation defective, for example ion room.Therefore, top gate structure TFT also has unique high requirement to the technology of preparing of active layer.
In view of this, people urgently hope to propose a kind of structure and manufacturing technology of compound active layer, to adapt among the top gate structure TFT specific (special) requirements to active layer; Simultaneously, to this compound active layer structure,, reduce contact resistance through with the metallized method of the active layer of source-drain area; And in suitable technology, anneal, finally obtain high performance top gate structure TFT device.
Summary of the invention
The technical problem that the present invention will solve is to the characteristic of existing film transistor device, uniformity and stability not enough, provides a kind of stability, uniformity good top gate structure metal oxide thin-film transistor; For this reason, the present invention also provides a kind of manufacture method of this top gate structure metal oxide thin-film transistor.
For solving above-mentioned first technical problem; Technical scheme of the present invention is: a kind of top gate structure metal oxide thin-film transistor, comprise substrate, active layer, insulating barrier, grid, source electrode and drain electrode, and active layer is located on the substrate; Source electrode is located at one of active layer upside end; The end in addition of active layer upside is located in drain electrode, and insulating barrier is located among the active layer upside, and grid is located on the insulating barrier; Be provided with metal layer between this active layer and the source electrode, also be provided with metal layer between this active layer and the drain electrode; This active layer is the composite film structure, from being followed successively by oxygen deprivation type metal oxide rete, rich oxygen type metal oxide rete down.
In technique scheme, said active layer adopts the sputtering method preparation, and in sputter procedure, uses same target, and the material of target is (In
2O
3)
x(Ga
2O
3)
y(ZnO)
z, wherein 0≤x, y, z≤1, and x+y+z=1; In sputter procedure, select anaerobic or hypoxic atmosphere to obtain oxygen deprivation type metal oxide rete, select oxygen-enriched atmosphere to obtain rich oxygen type metal oxide rete.
In technique scheme, the thickness of said metal layer is 0.1～20nm, is preferably 1～10nm.
For solving above-mentioned second technical problem, technical scheme of the present invention is: the manufacture method of the said top gate structure metal oxide thin-film transistor of a kind of claim 1 may further comprise the steps:
A, on substrate, adopt sputtering method to make active layer, select anaerobic or hypoxic atmosphere to obtain oxygen deprivation type metal oxide rete, select oxygen-enriched atmosphere to obtain rich oxygen type metal oxide rete; Active layer made and graphical after, high annealing, 150 ℃～500 ℃ of annealing temperatures, annealing is carried out under atmosphere or oxygen-containing atmosphere;
B, at the active layer upside, adopt sputter, chemical vapour deposition (CVD), spin coating or method of printing to make insulating barrier; And adopt photoetching or mask method to obtain the insulating barrier shape; After insulating barrier has been made, high annealing, 150 ℃～500 ℃ of annealing temperatures, annealing is carried out under atmosphere or oxygen-containing atmosphere;
C, at the two ends of active layer upside, make metal layer through vacuum splashing and plating or evaporation coating method respectively; Metal layer has been made the back high annealing, and metal diffusing is got into active layer, forms metallized source contact area or drain contact region;
C, at the two ends of active layer upside, make metal layer through vacuum splashing and plating or evaporation coating method respectively; Metal layer has been made the back high annealing, and metal diffusing is got into active layer, forms metallized source contact area or drain contact region; Annealing temperature is 150 ℃～500 ℃, and annealing is carried out under atmosphere or oxygen-containing atmosphere;
E, on insulating barrier through sputter or evaporation coating method manufacturing grid, and adopt photoetching or mask method to obtain gate shapes.
The invention has the beneficial effects as follows: the present invention is top gate structure; Adopt oxygen deprivation type metal oxide rete and rich oxygen type metal oxide rete to constitute the active layer of composite film structure; This active layer can better contact at the interface with insulating barrier; Reduce the charge defects at interface, and show better electric property; Be provided with metal layer between active layer of the present invention and the source electrode; And also be provided with metal layer between the drain electrode, improved the interface contact resistance between semiconductor active layer and source electrode or drain electrode, i.e. the contact zone of metallized semi conductor and source-drain electrode; Reduce contact resistance; Reduce state leakage, improve electron mobility, improve current on/off ratio (I
On/ I
Off), thereby can significantly improve the electric property of top-grate structure thin film transistor.In addition, the present invention improves annealing link and the environment in the preparation process; Further realize low off-state current, high electron mobility and the current on/off ratio of the enhancement mode metal oxide thin film transistor of good uniformity.
Description of drawings
Fig. 1 is a metal oxide thin-film transistor structural representation of the present invention.
Fig. 2 is embodiment 1 output characteristic curve figure among the present invention.
Fig. 3 is embodiment 1 transfer characteristic curve figure among the present invention.
Fig. 4 is embodiment 2 output characteristic curve figure among the present invention.
Fig. 5 is embodiment 2 transfer characteristic curve figure among the present invention.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment invention top gate structure metal oxide thin-film transistor and preparation method thereof is described in further detail.
As shown in Figure 1; This top gate structure metal oxide thin-film transistor comprises substrate 1, active layer 2, insulating barrier 3, grid 4, source electrode and drain electrode 6; Active layer is located on the substrate, and source electrode is located at one of active layer 2 upsides end, and the end in addition of active layer 2 upsides is located in drain electrode; Insulating barrier 3 is located among the active layer upside, and grid 4 is located on the insulating barrier 3; Be provided with metal layer 5 between this active layer 2 and the source electrode, also be provided with metal layer 5 between this active layer 2 and the drain electrode; This active layer 2 is the composite film structure, from being followed successively by oxygen deprivation type metal oxide rete 21, rich oxygen type metal oxide rete 22 down.
Said insulating barrier 3 is insulating metal oxide or silica-based insulating material or macromolecular material.
Hold, said active layer 2 adopts the sputtering method preparation, and in sputter procedure, uses same target, and the material of target is (In
2O
3)
x(Ga
2O
3)
y(ZnO)
z, wherein 0≤x, y, z≤1, and x+y+z=1; In sputter procedure, select anaerobic or hypoxic atmosphere to obtain oxygen deprivation type metal oxide rete 21, select oxygen-enriched atmosphere to obtain rich oxygen type metal oxide rete 22.
Said substrate 1 material is silicon chip or glass or pottery; Glass substrate is preferably alkali-free glass substrate or is coated with the glass substrate of silica membrane.
Said insulating barrier 3 is insulating metal oxide or silica-based insulating material or macromolecular material; Further, this silica-based insulating material is silicon dioxide or insulating silicon nitride material or the two composite material.
In the metal material that said metal layer 5 is metal A l, Mo, Cu, Ti or other low-resistivities one or more, preferred here AL.
The thickness of said metal layer 5 is 0.1～20nm, is preferably 1～10nm.
The manufacture method of above-mentioned top gate structure metal oxide thin-film transistor may further comprise the steps:
A, on substrate, adopt sputtering method to make active layer, select anaerobic or hypoxic atmosphere to obtain oxygen deprivation type metal oxide rete, select oxygen-enriched atmosphere to obtain rich oxygen type metal oxide rete; Active layer made and graphical after, high annealing, 150 ℃～500 ℃ of annealing temperatures, annealing is carried out under atmosphere or oxygen-containing atmosphere;
B, at the active layer upside, adopt sputter, chemical vapour deposition (CVD), spin coating or method of printing to make insulating barrier; And adopt photoetching or mask method to obtain the insulating barrier shape; After insulating barrier has been made, high annealing, 150 ℃～500 ℃ of annealing temperatures, annealing is carried out under atmosphere or oxygen-containing atmosphere;
C, at the two ends of active layer upside, make metal layer through vacuum splashing and plating or evaporation coating method respectively; Metal layer has been made the back high annealing, and metal diffusing is got into active layer, forms metallized source contact area or drain contact region; Annealing temperature is 150 ℃～500 ℃, and annealing is carried out under atmosphere or oxygen-containing atmosphere;
D, on metallized source contact area, make source electrode, and adopt photoetching or mask method to obtain the source electrode shape through sputter or evaporation coating method; On metallized drain contact region, make drain electrode, and adopt photoetching or mask method to obtain the shape that drains through sputter or evaporation coating method;
E, on insulating barrier through sputter or evaporation coating method manufacturing grid, and adopt photoetching or mask method to obtain gate shapes.
Further, the annealing temperature after said active layer has been made is preferably 150 ℃～350 ℃, and the annealing temperature after said insulating barrier has been made is preferably 150 ℃～350 ℃, and the annealing temperature after said metal layer has been made also is preferably 150 ℃～350 ℃.
The electrode material of said source electrode, drain and gate is one or more in the metal material of metal A l, Mo, Cu, Ti or other low-resistivities, preferred here Mo.
Concrete making step is:
Embodiment 1:
(1) sputter 20nm oxygen-starved IGZO (making of one pack system Ar atmosphere) on alkali-free glass uses identical target sputter 5nm rich oxygen type IGZO (making of one pack system oxygen atmosphere) again; Wet etching then, graphical IGZO;
(2) under dry oxygen ambient and 300 ℃ of temperature, annealed one hour;
(3) above compound active layer sputter 20nm silicon dioxide and 300nm silicon nitride as insulating barrier;
(4) under air and 200 ℃ of temperature, annealed one hour;
(5) sputter 100nm metal molybdenum is as gate electrode;
(6) sputter 100nm metal molybdenum is as source/drain electrode.
In addition, in this embodiment 1, output characteristic curve figure please refer to Fig. 2, and transfer characteristic curve figure please refer to Fig. 3.
Embodiment 2:
In this implements, according to the method and similar method of condition and condition making thin-film transistor of embodiment 1.Difference be (5) and (6) between increase following two steps:
(6) sputter 5nm metallic aluminium is used to the active layer that metallizes;
(7) under dry oxygen ambient and 300 ℃ of temperature, annealed one hour.
In addition, in this embodiment 2, output characteristic curve figure please refer to Fig. 4, and transfer characteristic curve figure please refer to Fig. 5.
Embodiment 3:
In this embodiment, according to making thin-film transistor with the method for embodiment 2 and the similar method of condition and condition.Difference is to cancel the insulating barrier annealing in (4) step.
Embodiment 4:
In this embodiment, according to making thin-film transistor with the method for embodiment 3 and the similar method of condition and condition.Difference be (1) and the annealing of (2) step active layer changed into before graphical and carrying out.
Embodiment 5:
In this embodiment, according to making thin-film transistor with the method for embodiment 4 and the similar method of condition and condition.Difference be (1) and the annealing of (2) step active layer changed into before graphical and carrying out once, carry out once after graphical.
Embodiment 6:
In this embodiment, according to making thin-film transistor with the method for embodiment 2 and the similar method of condition and condition.Difference is to cancel the annealing of (2) step active layer.
Table 1: the characteristic contrast of each embodiment
Result by table 1 can know, makes thin layer of aluminum in the source-drain electrode district, should distinguish active layer through the mode of thermal diffusion and metallize, and can effectively reduce the subthreshold value amplitude of oscillation of thin-film transistor, and threshold voltage is controlled near the 0V; The annealing of active layer is very big to the influence of tft characteristics, and each characteristic is all poor when unannealed; Active layer can improve the uniformity of thin-film transistor at graphical after annealing, improves the mobility of thin-film transistor, improves the subthreshold value amplitude of oscillation, makes obviously skew to the forward of device threshold voltage; Annealing before active layer is annealed than active layer graph respectively before and after graphical is more or less the same to tft characteristics, all poor, device threshold voltage skew slightly to the forward; In addition, make after annealing, can improve the uniformity of thin-film transistor, improve the mobility of thin-film transistor, the device mode of operation is strengthened from exhausting to become at insulating barrier.
Above content is to combine concrete preferred implementation to the further explain that the present invention did, and can not assert that practical implementation of the present invention is confined to these explanations.For the those of ordinary skill of technical field under the present invention, under the prerequisite that does not break away from the present invention's design, its framework form can be flexible and changeable, can the subseries product.Just make some simple deduction or replace, all should be regarded as belonging to the scope of patent protection that the present invention is confirmed by claims of being submitted to.
Claims (10)
1. top gate structure metal oxide thin-film transistor; Comprise substrate, active layer, insulating barrier, grid, source electrode and drain electrode; Active layer is located on the substrate, and source electrode is located at one of active layer upside end, and the end in addition of active layer upside is located in drain electrode; Insulating barrier is located among the active layer upside, and grid is located on the insulating barrier; It is characterized in that: be provided with metal layer between this active layer and the source electrode, also be provided with metal layer between this active layer and the drain electrode; This active layer is the composite film structure, from being followed successively by oxygen deprivation type metal oxide rete, rich oxygen type metal oxide rete down.
2. top gate structure metal oxide thin-film transistor according to claim 1 is characterized in that: said active layer adopts the sputtering method preparation, and in sputter procedure, uses same target, and the material of target is (In
2O
3)
x(Ga
2O
3)
y(ZnO)
z, wherein 0≤x, y, z≤1, and x+y+z=1; In sputter procedure, select anaerobic or hypoxic atmosphere to obtain oxygen deprivation type metal oxide rete, select oxygen-enriched atmosphere to obtain rich oxygen type metal oxide rete.
3. top gate structure metal oxide thin-film transistor according to claim 1 is characterized in that: said baseplate material is silicon chip or glass or pottery.
4. top gate structure metal oxide thin-film transistor according to claim 1 is characterized in that: said insulating barrier is insulating metal oxide or silica-based insulating material or macromolecular material.
5. top gate structure metal oxide thin-film transistor according to claim 4 is characterized in that: said silica-based insulating material is silicon dioxide or insulating silicon nitride material or the two composite material.
6. top gate structure metal oxide thin-film transistor according to claim 1 is characterized in that: said metal layer is one or more in the metal material of metal A l, Mo, Cu, Ti or other low-resistivities.
7. according to the described top gate structure metal oxide thin-film transistor of any claim in the claim 1～6, it is characterized in that: the thickness of said metal layer is 0.1～20nm, is preferably 1～10nm.
8. the manufacture method of the said top gate structure metal oxide thin-film transistor of claim 1 is characterized in that, may further comprise the steps:
A, on substrate, adopt sputtering method to make active layer, select anaerobic or hypoxic atmosphere to obtain oxygen deprivation type metal oxide rete, select oxygen-enriched atmosphere to obtain rich oxygen type metal oxide rete; Active layer made and graphical after, high annealing, 150 ℃～500 ℃ of annealing temperatures, annealing is carried out under atmosphere or oxygen-containing atmosphere;
B, at the active layer upside, adopt sputter, chemical vapour deposition (CVD), spin coating or method of printing to make insulating barrier; And adopt photoetching or mask method to obtain the insulating barrier shape; After insulating barrier has been made, high annealing, 150 ℃～500 ℃ of annealing temperatures, annealing is carried out under atmosphere or oxygen-containing atmosphere;
C, at the two ends of active layer upside, make metal layer through vacuum splashing and plating or evaporation coating method respectively; Metal layer has been made the back high annealing, and metal diffusing is got into active layer, forms metallized source contact area or drain contact region; Annealing temperature is 150 ℃～500 ℃, and annealing is carried out under atmosphere or oxygen-containing atmosphere;
D, on metallized source contact area, make source electrode, and adopt photoetching or mask method to obtain the source electrode shape through sputter or evaporation coating method; On metallized drain contact region, make drain electrode, and adopt photoetching or mask method to obtain the shape that drains through sputter or evaporation coating method;
E, on insulating barrier through sputter or evaporation coating method manufacturing grid, and adopt photoetching or mask method to obtain gate shapes.
9. the manufacture method of said according to Claim 8 top gate structure metal oxide thin-film transistor; It is characterized in that: the annealing temperature after said active layer has been made is 150 ℃～350 ℃; Annealing temperature after said insulating barrier has been made is 150 ℃～350 ℃, and the annealing temperature after said metal layer has been made is 150 ℃～350 ℃.
10. it is characterized in that according to Claim 8 or the manufacture method of 9 said top gate structure metal oxide thin-film transistors: the electrode material of said source electrode, drain and gate is one or more in the metal material of metal A l, Mo, Cu, Ti or other low-resistivities.
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| CN104282567A (en) * | 2013-07-05 | 2015-01-14 | 上海和辉光电有限公司 | Method for manufacturing IGZO layer and TFT |
| WO2015043008A1 (en) * | 2013-09-30 | 2015-04-02 | 深圳市华星光电技术有限公司 | Method for manufacturing thin film transistor array substrate |
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| CN106374044A (en) * | 2016-11-02 | 2017-02-01 | 杭州潮盛科技有限公司 | Semiconductor structure and fabrication method thereof |
| WO2017071658A1 (en) * | 2015-10-29 | 2017-05-04 | 陆磊 | Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel |
| CN108987470A (en) * | 2018-07-16 | 2018-12-11 | 华南理工大学 | The production method of thin film transistor (TFT), display panel and thin film transistor (TFT) |
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| CN102969364A (en) * | 2012-09-28 | 2013-03-13 | 东莞有机发光显示产业技术研究院 | Top gate structure metallic oxide thin film transistor for improving device uniformity and manufacture method thereof |
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| WO2017071658A1 (en) * | 2015-10-29 | 2017-05-04 | 陆磊 | Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel |
| CN106374044A (en) * | 2016-11-02 | 2017-02-01 | 杭州潮盛科技有限公司 | Semiconductor structure and fabrication method thereof |
| CN106374044B (en) * | 2016-11-02 | 2019-06-11 | 杭州潮盛科技有限公司 | Semiconductor structure and preparation method thereof |
| CN109980086A (en) * | 2017-12-28 | 2019-07-05 | 深圳Tcl工业研究院有限公司 | Oxide thin film transistor and preparation method thereof |
| CN108987470A (en) * | 2018-07-16 | 2018-12-11 | 华南理工大学 | The production method of thin film transistor (TFT), display panel and thin film transistor (TFT) |
| CN108987470B (en) * | 2018-07-16 | 2021-01-01 | 华南理工大学 | Thin film transistor, display panel and manufacturing method of thin film transistor |
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