WO2016132681A1 - Layered product and process for producing layered product - Google Patents

Layered product and process for producing layered product Download PDF

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Publication number
WO2016132681A1
WO2016132681A1 PCT/JP2016/000345 JP2016000345W WO2016132681A1 WO 2016132681 A1 WO2016132681 A1 WO 2016132681A1 JP 2016000345 W JP2016000345 W JP 2016000345W WO 2016132681 A1 WO2016132681 A1 WO 2016132681A1
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layer
metal
metal oxide
substrate
oxide layer
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PCT/JP2016/000345
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French (fr)
Japanese (ja)
Inventor
重和 笘井
義弘 上岡
隆司 関谷
勇輝 霍間
絵美 川嶋
基浩 竹嶋
井上　一吉
紘美 早坂
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出光興産株式会社
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Priority to JP2017500494A priority Critical patent/JPWO2016132681A1/en
Publication of WO2016132681A1 publication Critical patent/WO2016132681A1/en

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a laminate and a method for producing the laminate.
  • metal oxides include degenerate semiconductors such as indium tin oxide (ITO) and indium zinc oxide (IZO (registered trademark)), and non-degenerate semiconductors such as ZnO and indium gallium zinc oxide (IGZO). It has been. These have been put to practical use in displays, sensors, varistors, etc., taking advantage of the wide band gap.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGZO indium gallium zinc oxide
  • An electronic device using an oxide material tends to have a metal-insulator-semiconductor (MIS) structure due to the reaction of oxide oxygen with the electrode depending on the selection of the electrode material.
  • MIS structure may cause an increase in contact resistance, increase power consumption, and cause a decrease in response.
  • Patent Document 1 proposes a technique for suppressing the generation of an oxide film by using an Al alloy to which a small amount of a noble metal that is not easily oxidized by Al or a metal having a relatively low electrical conductivity as an oxide is used.
  • An object of the present invention is to provide a laminate having no contact resistance and a method for producing the laminate.
  • the problem of contact resistance becomes more prominent.
  • TFTs thin film transistors
  • a bottom contact type TFT in which an oxide semiconductor is formed after source and drain electrodes tends to have high contact resistance.
  • the contact resistance is increased, the voltage-current characteristic deviates from the ohmic characteristic, so that the image quality is lowered in the case of TFT, and the power conversion efficiency is lowered in the case of a power device.
  • FIG. 11 shows a typical example of voltage-current characteristics when the contact resistance is kept small.
  • the mixing layer is a mixed phase of an element constituting the metal oxide layer and an element constituting the support layer.
  • the support layer is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate. Laminated body. 4).
  • the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. body. 5.
  • the metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium.
  • the support layer, the first metal layer, and the metal oxide layer are laminated in this order, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer exceeds 0 nm.
  • the support layer is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate.
  • Laminated body 9.
  • the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. body. 10.
  • the metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium.
  • the laminate according to any one of 6 to 9, comprising one or more metal oxides selected from oxides. 11.
  • the metal oxide layer is formed on the support layer using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method.
  • the metal oxide layer is formed on the metal layer by using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method.
  • a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method.
  • the manufacturing method of the laminated body to form.
  • An electronic device comprising the laminate according to any one of 1 to 5, further comprising a metal layer on the metal oxide layer and exhibiting ohmic characteristics between the metal oxide layer and the support layer element. 14.
  • An electronic device comprising the laminate according to any one of 14.6 to 10, further comprising a second metal layer on the metal oxide layer, wherein the second metal layer is interposed between the metal oxide layer and the first metal layer.
  • An electronic device exhibiting ohmic characteristics. 15.
  • a laminate having no contact resistance and a method for producing the laminate can be provided.
  • FIG. 4 is a cross-sectional TEM photograph of a Si / Ga 2 O 3 / Ti laminate of Comparative Example 2.
  • 4 is a diagram of IV characteristics of Example 4, Comparative Example 3 and Comparative Example 4.
  • FIG. It is a figure which shows the typical example of the voltage-current characteristic in case the contact resistance of a thin-film transistor is high. It is a figure which shows the typical example of the voltage-current characteristic at the time of suppressing the contact resistance of a thin-film transistor small.
  • the support layer, the metal oxide layer, or the support layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer is more than 0 nm. 0 nm or less.
  • the second aspect of the laminate of the present invention is the order of the support layer, the first metal layer, and the metal oxide layer, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer.
  • the thickness of the mixing layer is greater than 0 nm and equal to or less than 5.0 nm.
  • the first embodiment and the second embodiment are collectively referred to as the laminate of the present invention.
  • the substrate and the metal oxide react to form a thin insulating layer (mixing layer), which may make it impossible to control electrical characteristics.
  • the laminate of the present invention does not generate a mixing layer that is generated at the initial stage of film formation, or realizes good ohmic characteristics by appropriately controlling the thickness thereof. Can do.
  • the laminated body 1 shows an example of the first aspect of the laminated body of the present invention, and includes a support layer 10, a mixing layer 20, and a metal oxide layer 30.
  • the laminated body 2 shows an example of the second aspect of the laminated body of the present invention, and includes a support layer 10, a first metal layer 15, a mixing layer 20, and a metal oxide layer 30.
  • each layer used for a laminated body is demonstrated.
  • the support layer is a substrate on which a metal oxide layer or a first metal layer is formed.
  • a wafer substrate such as Si, SiC, GaN, Al 2 O 3 , ZnO, Ga 2 O 3 , yttria stable zirconia (YSZ), strontium titanate (STO), a glass substrate, a resin substrate, or the like is used. It is done.
  • the support layer also includes an element substrate on which a transistor such as a TFT or MOSFET is mounted.
  • the support layer is preferably a Si wafer, a SiC wafer, or a GaN wafer.
  • a Si wafer substrate is preferable.
  • Conventionally known B, P, Sb and the like can be used as the dopant.
  • As or red phosphorus may be used as a dopant.
  • the thickness of the support layer is not particularly limited, and is usually 200 to 1000 ⁇ m.
  • polishing may be performed by a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • a TAIKO type structure that leaves the outer peripheral part a structure that is back-ground with only the outer peripheral part on the back surface
  • Polishing may be performed before or after the metal oxide is laminated.
  • the material of the wafer may be a single crystal structure or a polycrystalline structure.
  • a Czochralski method, a floating zone method, or the like can be used, and a conventionally known Si substrate can be used.
  • the first metal layer is formed on the support layer in the second embodiment.
  • the first metal layer is not particularly limited as long as it has excellent conductivity, and is preferably excellent in heat stability, little structural change, and excellent adhesion.
  • the film thickness of the first metal layer is not particularly limited, but a film thickness that can exhibit a metal work function is preferably 5 to 30 nm.
  • the first metal layer examples include Mo, Ti, Pd, Pt, Cr, Al, Ag, Au, Cu, In, ITO, and IZO (registered trademark).
  • the material may be used after being flattened by using a CMP method or the like.
  • two or more kinds of metals may be laminated, or an alloy of two or more kinds of metals may be used.
  • the alloy include conventionally known alloys such as MoTa, MoW, AlNd, AgPdCu, AgCe, and CuMn.
  • Preferred metals constituting the first metal layer include Ti, Pd, Cr, In, IZO, and Mo.
  • a metal having a work function close to that of the metal oxide layer is appropriately selected as the first metal layer.
  • a metal having a work function larger than that of the metal oxide layer is appropriately selected as the first metal layer.
  • the work function of the first metal layer is measured by an atmospheric photoelectron spectrometer (for example, Riken Keiki AC-3).
  • the mixing layer may or may not exist.
  • the mixing layer is formed on the support layer or the first metal layer.
  • the thickness of the mixing layer is more than 0 nm and not more than 5.0 nm.
  • the mixing layer is preferably a mixed phase of elements constituting the metal oxide layer and the support layer, or a mixed phase of elements constituting the metal oxide layer and the first metal layer.
  • the mixing layer is formed when the metal oxide layer is deposited on the support layer or the first metal layer using a low energy deposition process.
  • the low energy film forming process include a low power sputtering method, a plasma chemical vapor deposition (PECVD) method, an organic metal CVD method, a mist CVD method, a molecular beam epitaxy (MBE) method, an ion plating method, and the like.
  • the low power sputtering method and the ion plating method can be uniformly formed on a substrate having an area of 300 cm 2 or more, which is advantageous in production.
  • the present invention can be applied to large-diameter Si wafers of 8 inches, 12 inches, 18 inches, etc., 7th generation, 8th generation, 10th generation class large LCD glass, or long-winding type resin films.
  • the low energy film formation process can suppress the implantation of the metal oxide layer into the support layer or the first metal.
  • a mixing layer composed of an element constituting the underlayer and an element constituting the metal oxide layer is generated at the interface between the underlayer and the metal oxide layer.
  • the mixing layer formed during the high energy deposition process is lower than the electrical resistance of SiO 2 but causes an increase in electrical resistance.
  • a low power process may be used only in the initial stage of film formation in a normal film formation method.
  • the power may be lowered only at the initial stage of film formation, and the sputtering power may be raised when the growth of the mixing layer is completed.
  • the sputtering power of the low power sputtering method varies depending on the shape of the apparatus used, the magnetic field strength, etc.
  • the cathode potential may be set to ⁇ 100 V to ⁇ 300 V, and high frequency (RF).
  • the power density is preferably 1.5 W / cm 2 or less.
  • the RF sputtering power density of 1.5 W / cm 2 or less is not unique because the distribution depends on the magnet strength of the sputtering apparatus, but in the case of a 4-inch ⁇ target, it corresponds to a power of approximately 100 W or less.
  • the thickness of the mixing layer is preferably more than 0 nm and not more than 4.0 nm, more preferably more than 0 nm and not more than 3.0 nm. A thinner mixing layer is preferable. When the mixing layer thickness exceeds 5.0 nm, a MIS structure is obtained, and it becomes difficult to control the ohmic junction or the Schottky junction.
  • the film thickness of the mixing layer depends on the metal oxide film forming method and the heat treatment temperature. The film thickness of the mixing layer is measured by a TEM (transmission electron microscope). Further, the constituent elements of the mixing layer can be confirmed using SIMS (Secondary Ion Mass Spectrometry) or an energy dispersive X-ray analyzer.
  • the metal oxide layer is a layer containing one or more metal oxides.
  • the thickness of the metal oxide layer is not particularly limited, but is preferably 10 nm to 10 ⁇ m, and more preferably 500 to 2000 nm.
  • the thickness of the metal oxide layer is appropriately selected depending on performance values such as the withstand voltage, on-resistance, and drive voltage of the target element.
  • the metal oxide examples include oxides containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al.
  • degenerate semiconductors such as ITO, IZO (registered trademark), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), SnO 2 , ZnO, indium aluminum oxide (IAO), IGZO (registered)
  • Non-degenerate semiconductors such as Ga 2 O 3 , In 2 O 3 , indium tin zinc oxide (ITZO), indium gallium oxide (IGO), and indium gallium aluminum oxide (IGAO) can be given.
  • the metal oxide constituting the metal oxide layer is preferably at least one selected from In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , IAO, IGZO, ITZO, GZO, IZO and IGO.
  • the composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) emission analyzer, XRF ((X-ray Fluorescence Analysis), or SIMS (Secondary Ion Mass Spectrometry).
  • ICP Inductively Coupled Plasma
  • XRF X-ray Fluorescence Analysis
  • SIMS Secondary Ion Mass Spectrometry
  • the metal oxide may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide preferably has an amorphous or microcrystalline structure.
  • “Microcrystalline structure” refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries.
  • the laminated body of this invention has a 2nd metal layer (a metal layer in a 1st aspect) on a metal oxide layer.
  • the second metal layer include metals such as Ti, Al, Cr, Ni, Cu, Mo, Ag, Pt, and Au, and degenerate semiconductor oxides such as IZO and ITO.
  • the thickness of the second metal layer is not particularly limited, but is preferably 30 to 500 nm, and more preferably 50 to 300 nm.
  • the film formation method of the first metal layer and the second metal layer is not particularly limited, and examples thereof include a sputtering method, a vacuum evaporation method, an electroplating method, an electroless plating method, and various CVD methods.
  • the laminate of the present invention can be used for electronic devices, sensors and the like.
  • the electronic device of the present invention including the laminate of the present invention can be used for various electric circuits, electric devices, vehicles, and the like.
  • the electronic element include a diode, a vertical MOSFET (metal-field-effect transistor), a TFT (Thin Film Transistor), a TVS (Transient Voltage Suppressor) diode, a capacitor, and a resistor.
  • Various power supply circuits such as rectifier circuits and DC-DC converters, various control circuits, voltage shift circuits, and external interfaces, which are mounted on an integrated circuit, taking advantage of the easy film formation and easy processability of the laminate of the present invention.
  • the balance between breakdown voltage and capacity is important, but the dielectric constant and band gap are adjusted by changing the material composition using the laminate of the present invention, and the device size and film thickness are optimized. Can be achieved.
  • the varistor voltage can be controlled under a low leakage current and a low dielectric constant.
  • both the dielectric constant and the leakage current are small compared to a conventional zinc oxide system, it is optimal for the application.
  • the material is appropriately selected. At this time, by setting the film thickness of the mixing layer present at the interface between the oxide semiconductor and the metal electrode to be more than 0.0 nm and not more than 5.0 nm, the varistor voltage can be designed correctly.
  • the laminate of the present invention can be used for a rectifier circuit, a power supply circuit, a standby monitoring circuit, and the like when receiving power or a signal from an electromagnetic field of an environment such as a wireless tag or an energy harvester.
  • the rectifier diode used for these is a low-voltage Si-SBD or Ge diode, but has a large reverse leakage current, which has a problem in terms of power conversion efficiency.
  • the laminate of the present invention is used, the leak current is small because of the wide gap, and the rectifying effect can be enhanced.
  • the forward voltage can be kept low by using the tunnel effect and the like by adjusting the film thickness and energy level. This laminated body can maintain a high rectifying effect even with respect to a change in temperature.
  • the preferable film thickness of the mixing layer present at the interface between the oxide semiconductor and the metal electrode is more than 0.0 nm and not more than 5.0 nm. Furthermore, unlike non-oxide semiconductors such as Si, SiC, and GaN, an oxide semiconductor does not require an annealing process, and thus it is possible to mount a rectifier circuit on a resin substrate such as PET or PC, which has been difficult in the past. .
  • the laminate of the present invention When the laminate of the present invention is used as a cathode electrode of an OLED (Organic Light Emitting Diode), a reduction in driving voltage and an improvement in image quality can be expected. Since an oxide semiconductor that has recently attracted attention is an n-channel, a source electrode is connected to the anode side of the OLED. In the case of this connection method, a change in the driving voltage of the OLED also affects the TFT operation, which may cause luminance unevenness. Therefore, if the metal oxide layer used in the present invention is stacked on the drain electrode to form a cathode, it is possible to prevent the change in the driving voltage of the OLED from affecting the TFT operation and improve the image quality.
  • OLED Organic Light Emitting Diode
  • an electron injection level can be adjusted by sandwiching a metal oxide layer between the drain electrode and C12A7, and the driving voltage can be further lowered. At this time, it is required that there is no high resistance mixing layer at the interface between the drain electrode and the metal oxide layer.
  • sensors include optical sensors such as ultraviolet rays and radiation, gas sensors such as oxygen and nitrogen, biosensors such as ion concentrations and microorganisms, and thermal sensors that detect temperature changes. Further, it is effective to apply the laminate of the present invention to a portion where the contact resistance of the combined interface between the electrode and the oxide semiconductor needs to be kept small, such as a nonvolatile phase change memory and a solar cell.
  • the electronic device of the present invention exhibits ohmic characteristics or Schottky characteristics between the metal oxide layer and the first metal layer, or between the metal oxide layer and the support layer. Moreover, it is preferable that a non-linear electrical property is exhibited between the metal oxide layer and the second metal layer (metal layer). Non-linear electrical characteristics refer to electrical conduction that does not follow Ohm's law. As the non-linear electrical characteristics, rectification characteristics and Schottky characteristics are preferable. A non-linear electrical characteristic is exhibited between the metal oxide layer and the second metal layer, whereby a Schottky junction element can be obtained.
  • the laminated body of the present invention when used for a diode, the characteristics of high-speed switching, high breakdown voltage, and low On resistance can be realized at the mass production level.
  • the metal oxide When the metal oxide is likely to be n-type due to oxygen deficiency and difficult to be p-type, it becomes a unipolar device and is preferably used for high-speed switching.
  • the ideality factor of a diode is represented by n that is determined when a voltage-current characteristic indicating nonlinear electrical characteristics is approximated by the following expression.
  • I is a current
  • I 0 is a constant
  • q is an elementary charge
  • V is an applied voltage
  • k is a Boltzmann constant
  • T is an absolute temperature.
  • the laminated body of this invention is used for a diode, since the board
  • the stacked body of the present invention is used as a high-speed FWD (Free Wheel Diode) chip in combination with a switching element such as an insulated gate bipolar transistor (IGBT) or MOSFET, it can be designed with a wiring layout similar to the conventional one.
  • IGBT insulated gate bipolar transistor
  • MOSFET insulated gate bipolar transistor
  • the forward rising voltage can be kept low, it is also suitable for a low voltage diode used in an energy harvesting circuit.
  • Example 1 As a support, an n-type Si substrate having a resistivity of 0.02 ⁇ ⁇ cm (an n-type Si substrate having a diameter of 4 inches and manufactured by KST World Co., Ltd.) was prepared. This was installed in a sputtering apparatus CS-200 (manufactured by ULVAC), first treated in reverse sputtering mode for 15 seconds, part of the natural oxide film was etched, DC sputtering was performed on the Mo target, and 15 nm of Mo was deposited. A film was formed (first metal layer).
  • this Mo-supported substrate is set in an ion plating apparatus SIP-800 (made by Showa Vacuum) through an area mask on which a square pattern with a side of 1 mm is formed, and ion plating (IP)
  • IP ion plating
  • a 1000 nm Ga 2 O 3 film was formed by a method (metal oxide layer).
  • This Si wafer / Mo / Ga 2 O 3 laminate was again mounted on the sputtering apparatus CS-200, and Ti was deposited at a thickness of 150 nm on the Ga 2 O 3 film via an electrode area mask (secondary film). Metal layer).
  • FIG. 3 is a diagram of IV characteristics of Example 1 and Comparative Example 1.
  • Figure 4 shows a cross-sectional TEM photograph of Si / Mo / Ga 2 O 3 / Ti laminate of Example 1. As observation points, the intersections of the diagonal lines of the metal oxide layer and the field of view of a total of five points of the midpoint between the intersection and each vertex are observed, and the metal oxide layer is divided into 10 equal parts at equal intervals. The interface with the first metal layer was measured, and the average value of a total of 55 locations was taken as the film thickness of the mixing layer. As a result, the analysis limit was exceeded, and no mixing layer was observed.
  • Comparative Example 1 A Si / Mo / Ga 2 O 3 film was formed in the same manner as in Example 1 except that a sputtering apparatus CS-200 was used instead of the ion plating apparatus SIP-800 and a Ga 2 O 3 film was formed by RF sputtering. / Ti laminate was manufactured and evaluated.
  • the RF power was 300 W (3.70 W / cm 2 ) for a 4-inch target.
  • FIG. 5 shows a cross-sectional TEM photograph of Si / Mo / Ga 2 O 3 / Ti laminate of Comparative Example 1.
  • the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Example 2 A Si / Ga 2 O 3 / Ti laminate was produced and evaluated in the same manner as in Example 1 except that no Mo film was formed.
  • FIG. 6 is a diagram of IV characteristics of Example 2 and Comparative Example 2.
  • the thickness of the mixing layer was 4 nm.
  • Figure 7 shows a cross-sectional TEM photograph of Si / Ga 2 O 3 / Ti laminate of Example 2.
  • the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 2 A Si / Ga 2 O 3 / Ti laminate was produced and evaluated in the same manner as in Comparative Example 1 except that no Mo film was formed. When IV characteristics were evaluated, negative resistance was obtained. The results are shown in FIG. This is considered that the tunnel current by MIS structure was expressed. The thickness of the mixing layer was 9 nm.
  • Figure 8 shows a cross-sectional TEM photograph of Si / Ga 2 O 3 / Ti laminate of Comparative Example 2. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Example 3 A Si / Mo / Ga 2 O 3 / IZO laminate was produced in the same manner as in Example 1 except that IZO was used instead of Ti. As in Example 1, when the IV characteristics of the obtained Si / Mo / Ga 2 O 3 / IZO laminate were evaluated, the interface between the Ga 2 O 3 layer and the Mo layer was ohmic, and the Ga 2 O 3 layer and The interface of the IZO layer had rectification characteristics. A Schottky junction element was obtained. Further, when the film thickness of the mixing layer was measured in the same manner as in Example 1, it was below the analysis limit and the presence of the mixing layer was not recognized.
  • HF: H2O 1: 50
  • the laminated body having the Au / Ti / a-IGZO / In / Ni / Ti / Si structure thus obtained was evaluated using 4200-SCS, ohmic characteristics were obtained.
  • the results are shown in FIG.
  • the thickness of the mixing layer at the interface between the In layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and the result was 4 nm.
  • the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 3 The film was formed in the same manner as in Example 4 except that Mo was used instead of In and the film formation power of IGZO was 200 W (2.47 W / cm 2 ), and Au / Ti / a-IGZO / Mo / A laminate having a Ni / Ti / Si structure was obtained. When this laminate was evaluated for IV characteristics using 4200-SCS, non-ohmic characteristics were obtained. The results are shown in FIG. Further, the thickness of the mixing layer at the interface between the Mo layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and as a result, it was 8 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 4 The film was formed in the same manner as in Example 4 except that Cr was used instead of In and the film formation power of IGZO was set to 400 W (4.93 W / cm 2 ), and Au / Ti / a-IGZO / Cr / A laminate having a Ni / Ti / Si structure was obtained. When this laminate was evaluated for IV characteristics using 4200-SCS, non-ohmic characteristics were obtained. The results are shown in FIG. Further, the thickness of the mixing layer at the interface between the Cr layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and as a result, it was 20 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Example 4 since the RF sputtering of IGZO was performed with a power of 1.5 W / cm 2 or less, the implantation effect on In was suppressed, the mixing layer was less than 5 nm, and ohmic characteristics were obtained.
  • Comparative Example 3 and Comparative Example 4 since RF sputtering of IGZO was performed with a high power exceeding 1.5 W / cm 2 , Mo and Cr were oxidized to form a high-resistance mixing layer, and non-ohmic characteristics and became.
  • This PET / Pd / IGO laminate was taken out again into the atmosphere, an electrode area mask was set and mounted on the sputtering apparatus CS-200, and 50 nm of Ti and Au were deposited in this order on the IGO film ( Second metal layer).
  • the first metal layer Pd and the metal oxide layer IGO Diode characteristics were obtained in which the interface was an ohmic junction and the interface between the metal oxide layer IGO and the second metal layer Ti was a Schottky junction.
  • the ideality factor n of the diode was evaluated to be 4.7. Moreover, it was 3 nm as a result of evaluating the thickness of the mixing layer of the interface of 1st metal layer Pd and metal oxide layer IGO like Example 1.
  • FIG. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 5 A Schottky with a PET / Pd / IGO / Ti / Au configuration was used in the same manner as in Example 5 except that the RF power when the metal oxide layer was formed by sputtering was 300 W (3.70 W / cm 2 ). A barrier diode was obtained. As for the obtained diode characteristics, it was confirmed that the interface between the first metal layer Pd and the metal oxide layer IGO was a Schottky junction as in Example 5, but the diode ideality factor n was 15. As a result of evaluating the thickness of the mixing layer at the interface between the first metal layer Pd and the metal oxide layer IGO in the same manner as in Example 1, it was 7 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Table 1 shows the evaluation results of Examples 1 and 3-5 and Comparative Examples 1 and 3-5 in which a laminate having a metal layer (first metal layer) between the support and the metal oxide layer was produced and evaluated. Show.
  • Table 2 shows the evaluation results of Example 2 and Comparative Example 2 in which a laminate having no metal layer between the support and the metal oxide layer was produced and evaluated.
  • the laminate of the present invention can be used for electronic devices and the like.
  • the electronic device of the present invention can be used for electric circuits, electric devices, and vehicles.

Abstract

A layered product which comprises a support layer and a metal oxide layer superposed in this order or comprises a support layer, a mixing layer, and a metal oxide layer superposed in this order, wherein the mixing layer has a film thickness larger than 0 nm but not larger than 5.0 nm.

Description

積層体及び積層体の製造方法Laminate and method for producing laminate
　本発明は、積層体及び積層体の製造方法に関する。 The present invention relates to a laminate and a method for producing the laminate.
　金属酸化物には、インジウム錫酸化物（ＩＴＯ）やインジウム亜鉛酸化物（ＩＺＯ（登録商標））のような縮退半導体、ＺｎＯやインジウムガリウム亜鉛酸化物（ＩＧＺＯ）のような非縮退半導体等が知られている。これらはバンドギャップが広いことを活かして、ディスプレイやセンサー、バリスター等で実用化されている。 Examples of metal oxides include degenerate semiconductors such as indium tin oxide (ITO) and indium zinc oxide (IZO (registered trademark)), and non-degenerate semiconductors such as ZnO and indium gallium zinc oxide (IGZO). It has been. These have been put to practical use in displays, sensors, varistors, etc., taking advantage of the wide band gap.
　酸化物材料を用いた電子デバイスは、電極材料の選定によっては、酸化物の酸素と電極とが反応し、金属－絶縁体－半導体（ＭＩＳ）構造になりやすい。ＭＩＳ構造は、接触抵抗の増大を招き、消費電力を増やしたり、レスポンスの低下を招くことがある。 An electronic device using an oxide material tends to have a metal-insulator-semiconductor (MIS) structure due to the reaction of oxide oxygen with the electrode depending on the selection of the electrode material. The MIS structure may cause an increase in contact resistance, increase power consumption, and cause a decrease in response.
　例えば、表示デバイスでは、信号線であるＡｌ配線上に画素電極であるＩＴＯをスパッタ成膜すると、Ａｌ表面に酸化物層が生成する。このため、信号線と画素電極の間の接触抵抗が高まり、画面の表示品位の低下を招くことがある。 For example, in a display device, when ITO that is a pixel electrode is formed by sputtering on an Al wiring that is a signal line, an oxide layer is formed on the Al surface. For this reason, the contact resistance between the signal line and the pixel electrode is increased, and the display quality of the screen may be deteriorated.
　特許文献１では、Ａｌに酸化されにくい貴金属や酸化物としての電気伝導率が比較的低い金属を少量添加したＡｌ合金を用いることで、酸化膜の発生を抑える技術が提唱されている。 Patent Document 1 proposes a technique for suppressing the generation of an oxide film by using an Al alloy to which a small amount of a noble metal that is not easily oxidized by Al or a metal having a relatively low electrical conductivity as an oxide is used.
特開２００４－２１４６０６号公報JP 2004-214606 A
　本発明の目的は、接触抵抗のない積層体及び積層体の製造方法を提供することである。 An object of the present invention is to provide a laminate having no contact resistance and a method for producing the laminate.
　積層する材料がＩＴＯのような縮退伝導を示す金属酸化物ではなく、より抵抗の高い酸化物半導体の場合、接触抵抗の問題はより顕著となる。例えば酸化物半導体を用いた薄膜トランジスタ（ＴＦＴ）のうち、ソース及びドレイン電極の後に酸化物半導体を成膜するボトムコンタクト型ＴＦＴは接触抵抗が高くなりやすい。接触抵抗が高くなると、電圧－電流特性がオーミック特性から外れてくるため、ＴＦＴの場合は画質の低下、パワーデバイスの場合は電力変換効率の低下を招く。接触抵抗が高い場合の電圧―電流特性の典型例を図１０に示す。接触抵抗を小さく抑えた場合の電圧―電流特性の典型例を図１１に示す。
　また、シリコンウェハー上に酸化物半導体を成膜すると接触抵抗が高くなりやすい。本発明者らは、これらの現象が、金属と金属酸化物の界面に、両者の混合層（ミキシング層）が形成され、この電気抵抗が金属、金属酸化物のいずれよりも高いためと考え、本発明に至った。 When the material to be stacked is not a metal oxide exhibiting degenerate conduction such as ITO but an oxide semiconductor having higher resistance, the problem of contact resistance becomes more prominent. For example, among thin film transistors (TFTs) using an oxide semiconductor, a bottom contact type TFT in which an oxide semiconductor is formed after source and drain electrodes tends to have high contact resistance. When the contact resistance is increased, the voltage-current characteristic deviates from the ohmic characteristic, so that the image quality is lowered in the case of TFT, and the power conversion efficiency is lowered in the case of a power device. A typical example of voltage-current characteristics when the contact resistance is high is shown in FIG. FIG. 11 shows a typical example of voltage-current characteristics when the contact resistance is kept small.
In addition, when an oxide semiconductor is formed over a silicon wafer, the contact resistance tends to increase. The present inventors think that these phenomena are because a mixed layer (mixing layer) of both is formed at the interface between the metal and the metal oxide, and this electric resistance is higher than either the metal or the metal oxide, The present invention has been reached.
　本発明によれば、以下の積層体及び積層体の製造方法等が提供される。
１．支持体層、金属酸化物層の順に、又は支持体層、ミキシング層、金属酸化物層の順に積層され、前記ミキシング層の膜厚が０ｎｍ超５．０ｎｍ以下である積層体。
２．前記ミキシング層が、前記金属酸化物層を構成する元素及び支持体層を構成する元素の混合相である１に記載の積層体。
３．前記支持体層が、Ｓｉ基板、ＳｉＣ基板、ＧａＮ基板、Ａｌ２Ｏ３基板、ＺｎＯ基板、Ｇａ２Ｏ３基板、イットリア安定ジルコニア基板及びチタン酸ストロンチウム基板から選ばれる基板である１又は２に記載の積層体。
４．前記金属酸化物層がＩｎ，Ｓｎ，Ｇｅ，Ｔｉ，Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ，Ｇａ及びＡｌのいずれか１以上を含有する金属酸化物を含む１～３のいずれかに記載の積層体。
５．前記金属酸化物層がＩｎ２Ｏ３，ＺｎＯ，Ｇａ２Ｏ３，ＳｎＯ２、インジウムアルミニウム酸化物、インジウムガリウム亜鉛酸化物、インジウムスズ亜鉛酸化物、ガリウム亜鉛酸化物、インジウム亜鉛酸化物及びインジウムガリウム酸化物から選ばれる１以上の金属酸化物を含む１～４のいずれかに記載の積層体。
６．支持体層、第一の金属層、金属酸化物層の順に、又は支持体層、第一の金属層、ミキシング層、金属酸化物層の順に積層され、前記ミキシング層の膜厚が０ｎｍ超５．０ｎｍ以下である積層体。
７．前記ミキシング層が、前記金属酸化物層を構成する元素及び第一の金属層を構成する元素の混合相である６に記載の積層体。
８．前記支持体層が、Ｓｉ基板、ＳｉＣ基板、ＧａＮ基板、Ａｌ２Ｏ３基板、ＺｎＯ基板、Ｇａ２Ｏ３基板、イットリア安定ジルコニア基板及びチタン酸ストロンチウム基板から選ばれる基板である６又は７に記載の積層体。
９．前記金属酸化物層がＩｎ，Ｓｎ，Ｇｅ，Ｔｉ，Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ，Ｇａ及びＡｌのいずれか１以上を含有する金属酸化物を含む６～８のいずれかに記載の積層体。
１０．前記金属酸化物層がＩｎ２Ｏ３，ＺｎＯ，Ｇａ２Ｏ３，ＳｎＯ２、インジウムアルミニウム酸化物、インジウムガリウム亜鉛酸化物、インジウムスズ亜鉛酸化物、ガリウム亜鉛酸化物、インジウム亜鉛酸化物及びインジウムガリウム酸化物から選ばれる１以上の金属酸化物を含む６～９のいずれかに記載の積層体。
１１．金属酸化物層を、低電圧スパッタリング法、プラズマ化学蒸着法、有機金属化学蒸着法、ミスト化学蒸着法、分子線エピタキシー法及びイオンプレーティング法から選ばれる成膜法を用いて、支持体層上に形成する積層体の製造方法。
１２．金属酸化物層を、低電圧スパッタリング法、プラズマ化学蒸着法、有機金属化学蒸着法、ミスト化学蒸着法、分子線エピタキシー法及びイオンプレーティング法から選ばれる成膜法を用いて、金属層上に形成する積層体の製造方法。
１３．１～５のいずれかに記載の積層体を含む電子素子であって、金属酸化物層上にさらに金属層を有し、金属酸化物層及び支持体層の間でオーミック特性を示す電子素子。
１４．６～１０のいずれかに記載の積層体を含む電子素子であって、金属酸化物層上にさらに第二の金属層を有し、金属酸化物層及び第一の金属層の間でオーミック特性を示す電子素子。
１５．前記金属酸化物層及び金属層の間、又は前記金属酸化物層及び第二の金属層の間が非線形の電気特性を示す１３又は１４に記載の電子素子。
１６．１３～１５のいずれかに記載の電子素子を１以上用いた、電気回路、電気機器又は車両。 According to the present invention, there are provided the following laminates, laminate production methods, and the like.
1. A laminate in which a support layer, a metal oxide layer, or a support layer, a mixing layer, and a metal oxide layer are laminated in this order, and the thickness of the mixing layer is greater than 0 nm and less than or equal to 5.0 nm.
2. 2. The laminate according to 1, wherein the mixing layer is a mixed phase of an element constituting the metal oxide layer and an element constituting the support layer.
3. 3. The substrate according to 1 or 2, wherein the support layer is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate. Laminated body.
4). The stack according to any one of 1 to 3, wherein the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. body.
5. The metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium. The laminate according to any one of 1 to 4, comprising one or more metal oxides selected from oxides.
6). The support layer, the first metal layer, and the metal oxide layer are laminated in this order, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer exceeds 0 nm. A laminate having a thickness of 0.0 nm or less.
7). The laminate according to 6, wherein the mixing layer is a mixed phase of an element constituting the metal oxide layer and an element constituting the first metal layer.
8). 6. The substrate according to 6 or 7, wherein the support layer is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate. Laminated body.
9. The stack according to any one of 6 to 8, wherein the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. body.
10. The metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium. The laminate according to any one of 6 to 9, comprising one or more metal oxides selected from oxides.
11. The metal oxide layer is formed on the support layer using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method. The manufacturing method of the laminated body formed in 1st.
12 The metal oxide layer is formed on the metal layer by using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method. The manufacturing method of the laminated body to form.
13. An electronic device comprising the laminate according to any one of 1 to 5, further comprising a metal layer on the metal oxide layer and exhibiting ohmic characteristics between the metal oxide layer and the support layer element.
14. An electronic device comprising the laminate according to any one of 14.6 to 10, further comprising a second metal layer on the metal oxide layer, wherein the second metal layer is interposed between the metal oxide layer and the first metal layer. An electronic device exhibiting ohmic characteristics.
15. 15. The electronic device according to 13 or 14, wherein non-linear electrical characteristics are exhibited between the metal oxide layer and the metal layer or between the metal oxide layer and the second metal layer.
16. An electric circuit, an electric device, or a vehicle using one or more electronic devices according to any one of 13 to 15.
　本発明によれば、接触抵抗のない積層体及び積層体の製造方法が提供できる。 According to the present invention, a laminate having no contact resistance and a method for producing the laminate can be provided.
本発明の積層体の第一の態様の一例の図である。It is a figure of an example of the 1st aspect of the laminated body of this invention. 本発明の積層体の第二の態様の一例の図である。It is a figure of an example of the 2nd aspect of the laminated body of this invention. 実施例１及び比較例１のＩＶ特性の図である。It is a figure of IV characteristic of Example 1 and Comparative Example 1. 実施例１のＳｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真である。 2 is a cross-sectional TEM photograph of the Si / Mo / Ga 2 O 3 / Ti laminated body of Example 1. 比較例１のＳｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真である。4 is a cross-sectional TEM photograph of the Si / Mo / Ga 2 O 3 / Ti laminate of Comparative Example 1. 実施例２及び比較例２のＩＶ特性の図である。It is a figure of IV characteristic of Example 2 and Comparative Example 2. 実施例２のＳｉ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真である。4 is a cross-sectional TEM photograph of the Si / Ga 2 O 3 / Ti laminated body of Example 2. 比較例２のＳｉ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真である。4 is a cross-sectional TEM photograph of a Si / Ga 2 O 3 / Ti laminate of Comparative Example 2. 実施例４、比較例３及び比較例４のＩＶ特性の図である。4 is a diagram of IV characteristics of Example 4, Comparative Example 3 and Comparative Example 4. FIG. 薄膜トランジスタの接触抵抗が高い場合の電圧―電流特性の典型例を示す図である。It is a figure which shows the typical example of the voltage-current characteristic in case the contact resistance of a thin-film transistor is high. 薄膜トランジスタの接触抵抗を小さく抑えた場合の電圧―電流特性の典型例を示す図である。It is a figure which shows the typical example of the voltage-current characteristic at the time of suppressing the contact resistance of a thin-film transistor small.
　本発明の積層体の第一の態様は、支持体層、金属酸化物層の順に、又は支持体層、ミキシング層、金属酸化物層の順に積層され、ミキシング層の膜厚が０ｎｍ超５．０ｎｍ以下である。 In the first aspect of the laminate of the present invention, the support layer, the metal oxide layer, or the support layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer is more than 0 nm. 0 nm or less.
　また、本発明の積層体の第二の態様は、支持体層、第一の金属層、金属酸化物層の順に、又は支持体層、第一の金属層、ミキシング層、金属酸化物層の順に積層され、ミキシング層の膜厚が０ｎｍ超５．０ｎｍ以下である。 Further, the second aspect of the laminate of the present invention is the order of the support layer, the first metal layer, and the metal oxide layer, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer. The thickness of the mixing layer is greater than 0 nm and equal to or less than 5.0 nm.
　第一の態様及び第二の態様を総括して、本発明の積層体という。 The first embodiment and the second embodiment are collectively referred to as the laminate of the present invention.
　金属酸化物層を基板上に成膜すると、基板と金属酸化物が反応して薄い絶縁層（ミキシング層）が生成し、電気特性が制御できなくなることがある。
　しかしながら、本発明の積層体は、酸化物金属層を積層する際に、成膜初期に発生するミキシング層を発生させない、又はその厚みの適切に制御することで、良好なオーミック特性を実現することができる。 When a metal oxide layer is formed on a substrate, the substrate and the metal oxide react to form a thin insulating layer (mixing layer), which may make it impossible to control electrical characteristics.
However, when the oxide metal layer is laminated, the laminate of the present invention does not generate a mixing layer that is generated at the initial stage of film formation, or realizes good ohmic characteristics by appropriately controlling the thickness thereof. Can do.
　本発明の積層体の第一の態様及び第二の態様の一例を図１及び２に示す。積層体１は、本発明の積層体の第一の態様の一例を示し、支持体層１０、ミキシング層２０、金属酸化物層３０からなる。積層体２は、本発明の積層体の第二の態様の一例を示し、支持体層１０、第一の金属層１５、ミキシング層２０、金属酸化物層３０からなる。
　以下、積層体に用いる各層について説明する。 An example of the first aspect and the second aspect of the laminate of the present invention is shown in FIGS. The laminated body 1 shows an example of the first aspect of the laminated body of the present invention, and includes a support layer 10, a mixing layer 20, and a metal oxide layer 30. The laminated body 2 shows an example of the second aspect of the laminated body of the present invention, and includes a support layer 10, a first metal layer 15, a mixing layer 20, and a metal oxide layer 30.
Hereinafter, each layer used for a laminated body is demonstrated.
　支持体層は、その上に金属酸化物層又は第一の金属層の成膜を行うための基板である。
　支持体層としては、Ｓｉ，ＳｉＣ，ＧａＮ，Ａｌ２Ｏ３，ＺｎＯ，Ｇａ２Ｏ３，イットリア安定ジルコニア（ＹＳＺ），チタン酸ストロンチウム（ＳＴＯ）等のウェハー基板やガラス基板、樹脂基板等が用いられる。また、支持体層には、ＴＦＴやＭＯＳＦＥＴ等のトランジスタを実装した素子基板も含む。 The support layer is a substrate on which a metal oxide layer or a first metal layer is formed.
As the support layer, a wafer substrate such as Si, SiC, GaN, Al 2 O 3 , ZnO, Ga 2 O 3 , yttria stable zirconia (YSZ), strontium titanate (STO), a glass substrate, a resin substrate, or the like is used. It is done. The support layer also includes an element substrate on which a transistor such as a TFT or MOSFET is mounted.
　縦方向（厚さ方向）に通電させて用いる場合には、支持体層としては、Ｓｉウェハー，ＳｉＣウェハー，ＧａＮウェハーが好ましい。
　量産性やコストを考慮するとＳｉウェハー基板が好ましい。Ｓｉウェハーはドーピングの有無、種類によってｎ型、ｉ型、ｐ型が存在するが、縦方向に電流を流す上では、電気抵抗の小さいｎ型又はｐ型が好ましい。ドーパントとしては従来公知のＢ，Ｐ，Ｓｂ等を用いることができる。特に抵抗を下げたい場合は、Ａｓや赤リンをドーパントとしてもよい。 When used by energizing in the vertical direction (thickness direction), the support layer is preferably a Si wafer, a SiC wafer, or a GaN wafer.
In consideration of mass productivity and cost, a Si wafer substrate is preferable. There are n-type, i-type, and p-type Si wafers depending on the presence / absence and type of doping, but the n-type or p-type with low electrical resistance is preferable in order to pass a current in the vertical direction. Conventionally known B, P, Sb and the like can be used as the dopant. In particular, when it is desired to lower the resistance, As or red phosphorus may be used as a dopant.
　支持体層の厚みに、特に制限はなく、通常、２００～１０００μｍである。縦方向の抵抗を下げたい場合には化学機械研磨（ＣＭＰ）法等により研磨してもよい。基板の反りが問題になる場合は、外周部を残したＴＡＩＫＯ型の構造（裏面の外周部のみを残してバックグラインドされた構造）を用いてもよい。研磨は金属酸化物を積層する前に行ってもよいし、後に行ってもよい。 The thickness of the support layer is not particularly limited, and is usually 200 to 1000 μm. In order to reduce the resistance in the vertical direction, polishing may be performed by a chemical mechanical polishing (CMP) method or the like. When warping of the substrate becomes a problem, a TAIKO type structure that leaves the outer peripheral part (a structure that is back-ground with only the outer peripheral part on the back surface) may be used. Polishing may be performed before or after the metal oxide is laminated.
　Ｓｉウェハーを用いる場合、ウェハーの材質は単結晶及び多結晶のいずれの構造でもよい。製法に関しても、チョクラルスキー法やフローティングゾーン法等を用いることができ、従来公知のＳｉ基板を用いることができる。 When using a Si wafer, the material of the wafer may be a single crystal structure or a polycrystalline structure. Regarding the manufacturing method, a Czochralski method, a floating zone method, or the like can be used, and a conventionally known Si substrate can be used.
　第一の金属層は、第二の態様において、支持体層上に成膜される。第一の金属層は、導電性に優れたものであれば特に限定されず、熱に対する安定性に優れ、構造変化の少なく、密着性に優れるものが好ましい。 The first metal layer is formed on the support layer in the second embodiment. The first metal layer is not particularly limited as long as it has excellent conductivity, and is preferably excellent in heat stability, little structural change, and excellent adhesion.
　第一の金属層の膜厚に、特に制限はないが、金属の仕事関数が発揮できる膜厚として５～３０ｎｍが好ましい。 The film thickness of the first metal layer is not particularly limited, but a film thickness that can exhibit a metal work function is preferably 5 to 30 nm.
　第一の金属層として、例えばＭｏ，Ｔｉ，Ｐｄ，Ｐｔ，Ｃｒ、Ａｌ、Ａｇ，Ａｕ、Ｃｕ、Ｉｎ、ＩＴＯ，ＩＺＯ（登録商標）等が挙げられる。尚、ＩＴＯのように結晶化させて用いることがある場合は粒界の凹凸が接触抵抗の増加を招くため、ＣＭＰ法等を用いて平坦化させて使用するとよい。導電性と、安定性及び密着性とを両立するために、二種以上の金属を積層させてもよいし、二種以上の金属の合金を用いてもよい。当該合金としては、例えば、ＭｏＴａ、ＭｏＷ、ＡｌＮｄ、ＡｇＰｄＣｕ，ＡｇＣｅ，ＣｕＭｎ等、従来公知の合金が挙げられる。
　第一の金属層を構成する好ましい金属としては、Ｔｉ，Ｐｄ，Ｃｒ、Ｉｎ，ＩＺＯ，Ｍｏが挙げられる。
　ミキシング層を介して接する金属酸化物層に対してオーミック接合を得たい場合は、金属酸化物層の仕事関数に近い金属が第一の金属層として適宜選択される。金属酸化物層に対してショットキー接合を得たい場合は、金属酸化物層よりも仕事関数の大きな金属が第一の金属層として適宜選択される。
　第一の金属層の仕事関数は、大気中光電子分光装置（例えば、理研計器ＡＣ－３）によって測定する。 Examples of the first metal layer include Mo, Ti, Pd, Pt, Cr, Al, Ag, Au, Cu, In, ITO, and IZO (registered trademark). In the case where the material is crystallized and used like ITO, the unevenness of the grain boundary causes an increase in contact resistance. Therefore, the material may be used after being flattened by using a CMP method or the like. In order to achieve both conductivity and stability and adhesion, two or more kinds of metals may be laminated, or an alloy of two or more kinds of metals may be used. Examples of the alloy include conventionally known alloys such as MoTa, MoW, AlNd, AgPdCu, AgCe, and CuMn.
Preferred metals constituting the first metal layer include Ti, Pd, Cr, In, IZO, and Mo.
When it is desired to obtain an ohmic junction with the metal oxide layer that is in contact with the mixing layer, a metal having a work function close to that of the metal oxide layer is appropriately selected as the first metal layer. When a Schottky junction is desired for the metal oxide layer, a metal having a work function larger than that of the metal oxide layer is appropriately selected as the first metal layer.
The work function of the first metal layer is measured by an atmospheric photoelectron spectrometer (for example, Riken Keiki AC-3).
　本発明の積層体において、ミキシング層は存在してもよいし、しなくてもよい。
　ミキシング層は支持体層又は第一の金属層上に形成される。ミキシング層の膜厚は０ｎｍ超５．０ｎｍ以下である。
　ミキシング層は、金属酸化物層及び支持体層を構成する元素の混合相、又は金属酸化物層及び第一の金属層を構成する元素の混合相であることが好ましい。 In the laminate of the present invention, the mixing layer may or may not exist.
The mixing layer is formed on the support layer or the first metal layer. The thickness of the mixing layer is more than 0 nm and not more than 5.0 nm.
The mixing layer is preferably a mixed phase of elements constituting the metal oxide layer and the support layer, or a mixed phase of elements constituting the metal oxide layer and the first metal layer.
　ミキシング層は、金属酸化物層を、低エネルギーの成膜プロセスを用いて、支持体層又は第一の金属層上に成膜する際に、形成される。
　低エネルギーの成膜プロセスとしては、低パワースパッタリング法、プラズマ化学蒸着（ＰＥＣＶＤ）法、有機金属ＣＶＤ法、ミストＣＶＤ法、分子線エピタキシー（ＭＢＥ）法、イオンプレーティング法等があげられる。
　このうち、低パワースパッタ法とイオンプレーティング法は面積が３００ｃｍ２以上の基板にも均一に成膜することができ、生産上有利である。例えば、８インチ、１２インチ、１８インチ等の大口径Ｓｉウェハーや７世代、８世代、１０世代クラスの大型ＬＣＤ用ガラス、あるいは長尺巻き取り式の樹脂フィルム等にも適用することができる。
　低エネルギーの成膜プロセスにより、金属酸化物層の、支持体層又は第一の金属への打込みを抑制することができる。 The mixing layer is formed when the metal oxide layer is deposited on the support layer or the first metal layer using a low energy deposition process.
Examples of the low energy film forming process include a low power sputtering method, a plasma chemical vapor deposition (PECVD) method, an organic metal CVD method, a mist CVD method, a molecular beam epitaxy (MBE) method, an ion plating method, and the like.
Among these, the low power sputtering method and the ion plating method can be uniformly formed on a substrate having an area of 300 cm 2 or more, which is advantageous in production. For example, the present invention can be applied to large-diameter Si wafers of 8 inches, 12 inches, 18 inches, etc., 7th generation, 8th generation, 10th generation class large LCD glass, or long-winding type resin films.
The low energy film formation process can suppress the implantation of the metal oxide layer into the support layer or the first metal.
　一般に、金属酸化物層を真空プロセスで成膜すると、下地層と金属酸化物層の界面に、下地層を構成する元素と金属酸化物層を構成する元素からなるミキシング層が生成する。
　高エネルギーの成膜プロセス中により形成されるミキシング層は、ＳｉＯ２の電気抵抗よりは低いが、電気抵抗の上昇の原因となる。 In general, when a metal oxide layer is formed by a vacuum process, a mixing layer composed of an element constituting the underlayer and an element constituting the metal oxide layer is generated at the interface between the underlayer and the metal oxide layer.
The mixing layer formed during the high energy deposition process is lower than the electrical resistance of SiO 2 but causes an increase in electrical resistance.
　尚、生産性を考慮する場合は、通常の成膜法において、成膜の初期のみ低パワープロセスとしてもよい。例えば、スパッタ法の場合、製膜の初期のみパワーを下げ、ミキシング層の成長が完了した時点でスパッタパワーを上げてもよい。
　尚、低パワースパッタ法のスパッタパワーは、使用する装置の形状、磁場強度等によって変わるが、例えば、直流（ＤＣ）スパッタの場合、カソード電位を－１００Ｖ～－３００Ｖとするとよく、高周波（ＲＦ）スパッタの場合、パワー密度を１．５Ｗ／ｃｍ２以下とするとよい。ＲＦスパッタのパワー密度１．５Ｗ／ｃｍ２以下は、スパッタ装置の磁石強度によって分布が生じるため一義的ではないが、４インチφのターゲットの場合、概ね１００Ｗ以下のパワーに相当する。 In consideration of productivity, a low power process may be used only in the initial stage of film formation in a normal film formation method. For example, in the case of the sputtering method, the power may be lowered only at the initial stage of film formation, and the sputtering power may be raised when the growth of the mixing layer is completed.
The sputtering power of the low power sputtering method varies depending on the shape of the apparatus used, the magnetic field strength, etc. For example, in the case of direct current (DC) sputtering, the cathode potential may be set to −100 V to −300 V, and high frequency (RF). In the case of sputtering, the power density is preferably 1.5 W / cm 2 or less. The RF sputtering power density of 1.5 W / cm 2 or less is not unique because the distribution depends on the magnet strength of the sputtering apparatus, but in the case of a 4-inch φ target, it corresponds to a power of approximately 100 W or less.
　ミキシング層の膜厚は、好ましくは０ｎｍ超４．０ｎｍ以下であり、より好ましくは０ｎｍ超３．０ｎｍ以下である。ミキシング層の膜厚は薄い方が好ましい。
　ミキシング層厚さが５．０ｎｍを超えると、ＭＩＳ構造となり、オーミック接合やショットキー接合の制御が困難になる。
　ミキシング層の膜厚は金属酸化物の成膜方法や熱処理温度に依存する。ミキシング層の膜厚は、その断面をＴＥＭ（透過型電子顕微鏡）により測定する。また、ミキシング層の構成元素は、ＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）、又はエネルギー分散型Ｘ線分析装置を用いて確認できる。 The thickness of the mixing layer is preferably more than 0 nm and not more than 4.0 nm, more preferably more than 0 nm and not more than 3.0 nm. A thinner mixing layer is preferable.
When the mixing layer thickness exceeds 5.0 nm, a MIS structure is obtained, and it becomes difficult to control the ohmic junction or the Schottky junction.
The film thickness of the mixing layer depends on the metal oxide film forming method and the heat treatment temperature. The film thickness of the mixing layer is measured by a TEM (transmission electron microscope). Further, the constituent elements of the mixing layer can be confirmed using SIMS (Secondary Ion Mass Spectrometry) or an energy dispersive X-ray analyzer.
　金属酸化物層は、１又は２以上の金属酸化物を含む層である。
　金属酸化物層の膜厚に、特に制限はないが、１０ｎｍ～１０μｍが好ましく、５００～２０００ｎｍがより好ましい。金属酸化物層の膜厚は、目的とする素子の耐圧、オン抵抗、駆動電圧等の性能値によって適宜選択される。 The metal oxide layer is a layer containing one or more metal oxides.
The thickness of the metal oxide layer is not particularly limited, but is preferably 10 nm to 10 μm, and more preferably 500 to 2000 nm. The thickness of the metal oxide layer is appropriately selected depending on performance values such as the withstand voltage, on-resistance, and drive voltage of the target element.
　金属酸化物としては、Ｉｎ，Ｓｎ，Ｇｅ，Ｔｉ、Ｚｎ，Ｙ，Ｓｍ，Ｃｅ、Ｎｄ、Ｇａ及びＡｌのいずれか１以上を含有する酸化物等が挙げられる。例えば、ＩＴＯ、ＩＺＯ（登録商標、以下同）、アルミニウム亜鉛酸化物（ＡＺＯ）、ガリウム亜鉛酸化物（ＧＺＯ）、ＳｎＯ２等の縮退半導体や、ＺｎＯ、インジウムアルミニウム酸化物（ＩＡＯ）、ＩＧＺＯ（登録商標、以下同）、Ｇａ２Ｏ３、Ｉｎ２Ｏ３、インジウムスズ亜鉛酸化物（ＩＴＺＯ）、インジウムガリウム酸化物（ＩＧＯ）、インジウムガリウムアルミニウム酸化物（ＩＧＡＯ）等の非縮退半導体が挙げられる。
　金属酸化物層を構成する金属酸化物は、好ましくはＩｎ２Ｏ３、ＺｎＯ、Ｇａ２Ｏ３、ＳｎＯ２、ＩＡＯ、ＩＧＺＯ、ＩＴＺＯ、ＧＺＯ、ＩＺＯ及びＩＧＯから選ばれる１以上である。 Examples of the metal oxide include oxides containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. For example, degenerate semiconductors such as ITO, IZO (registered trademark), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), SnO 2 , ZnO, indium aluminum oxide (IAO), IGZO (registered) Non-degenerate semiconductors such as Ga 2 O 3 , In 2 O 3 , indium tin zinc oxide (ITZO), indium gallium oxide (IGO), and indium gallium aluminum oxide (IGAO) can be given.
The metal oxide constituting the metal oxide layer is preferably at least one selected from In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , IAO, IGZO, ITZO, GZO, IZO and IGO.
　金属酸化物の組成は、ＩＣＰ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ）発光分析装置やＸＲＦ（（Ｘ－ｒａｙ　Ｆｌｕｏｒｅｓｃｅｎｃｅ　Ａｎａｌｙｓｉｓ，）又はＳＩＭＳ（Ｓｅｃｏｎｄａｒｙ　Ｉｏｎ　Ｍａｓｓ　Ｓｐｅｃｔｒｏｍｅｔｒｙ）によって測定する。 The composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) emission analyzer, XRF ((X-ray Fluorescence Analysis), or SIMS (Secondary Ion Mass Spectrometry).
　金属酸化物は、非晶質でも結晶質でもよく、結晶は、微結晶でも単結晶でもよいが、金属酸化物は非晶質又は微結晶構造が好ましい。
　「微結晶構造」とは、結晶粒径のサイズがサブミクロン以下であり、明解な粒界が存在しないものを言う。 The metal oxide may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide preferably has an amorphous or microcrystalline structure.
“Microcrystalline structure” refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries.
　本発明の積層体は、金属酸化物層上に第二の金属層（第一の態様では金属層）を有することが好ましい。第二の金属層としては、Ｔｉ，Ａｌ，Ｃｒ，Ｎｉ，Ｃｕ，Ｍｏ，Ａｇ、Ｐｔ，Ａｕ等の金属やＩＺＯ、ＩＴＯ等の縮退半導体酸化物等が挙げられる。
　第二の金属層の膜厚に、特に制限はないが、３０～５００ｎｍが好ましく、５０～３００ｎｍがより好ましい。 It is preferable that the laminated body of this invention has a 2nd metal layer (a metal layer in a 1st aspect) on a metal oxide layer. Examples of the second metal layer include metals such as Ti, Al, Cr, Ni, Cu, Mo, Ag, Pt, and Au, and degenerate semiconductor oxides such as IZO and ITO.
The thickness of the second metal layer is not particularly limited, but is preferably 30 to 500 nm, and more preferably 50 to 300 nm.
　第一の金属層及び第二の金属層の成膜法は特に限定されず、スパッタ法、真空蒸着法、電界めっき法、無電解めっき法、各種ＣＶＤ法等が挙げられる。 The film formation method of the first metal layer and the second metal layer is not particularly limited, and examples thereof include a sputtering method, a vacuum evaporation method, an electroplating method, an electroless plating method, and various CVD methods.
　本発明の積層体は、電子素子、センサー等に用いることができる。また、本発明の積層体を含む本発明の電子素子は、多様な電気回路や電気機器、車両等に用いることができる。
　電子素子としては、ダイオード、縦型ＭＯＳＦＥＴ（ｍｅｔａｌ－ｏｘｉｄｅ－ｓｅｍｉｃｏｎｄｕｃｔｏｒ　ｆｉｅｌｄ－ｅｆｆｅｃｔ　ｔｒａｎｓｉｓｔｏｒ）、ＴＦＴ（Ｔｈｉｎ　Ｆｉｌｍ　Ｔｒａｎｓｉｓｔｏｒ）、ＴＶＳ（Ｔｒａｎｓｉｅｎｔ　Ｖｏｌｔａｇｅ　Ｓｕｐｐｒｅｓｓｏｒ）ダイオード、キャパシタ、抵抗体等が挙げられる。 The laminate of the present invention can be used for electronic devices, sensors and the like. In addition, the electronic device of the present invention including the laminate of the present invention can be used for various electric circuits, electric devices, vehicles, and the like.
Examples of the electronic element include a diode, a vertical MOSFET (metal-field-effect transistor), a TFT (Thin Film Transistor), a TVS (Transient Voltage Suppressor) diode, a capacitor, and a resistor.
　本発明の積層体の易成膜性、易加工性を活かし、集積回路上に搭載される、整流回路、ＤＣ－ＤＣコンバーターのような様々な電源回路や各種制御回路、電圧シフト回路、外部インターフェースを構成するのに特に用いることができる。その要素部品となる薄膜抵抗体、固定容量キャパシタ、可変容量キャパシタ、スイッチングトランジスター、保護用ダイオード、定電圧ダイオード、還流ダイオード等に用いることができる。
　これらのデバイスは、耐圧と容量のバランスが重要だが、本発明の積層体を用い、材料組成を変更することで、誘電率とバンドギャップを調整し、さらに素子のサイズと膜厚とで最適化を図ることができる。例えば、バリスタダイオードでは、低リーク電流、低誘電率の下で、バリスタ電圧を制御できればよいが、従来の酸化亜鉛系と比較して、誘電率、リーク電流ともに小さいため、用途に応じた最適な材料が適宜選択される。このとき、酸化物半導体と金属電極との界面に存在するミキシング層の膜厚を０．０ｎｍ超、５．０ｎｍ以下とすることで、バリスタ電圧を正しく設計することが可能となる。 Various power supply circuits such as rectifier circuits and DC-DC converters, various control circuits, voltage shift circuits, and external interfaces, which are mounted on an integrated circuit, taking advantage of the easy film formation and easy processability of the laminate of the present invention. Can be used in particular to construct. It can be used for a thin film resistor, a fixed capacitor, a variable capacitor, a switching transistor, a protective diode, a constant voltage diode, a freewheeling diode, and the like as its component parts.
In these devices, the balance between breakdown voltage and capacity is important, but the dielectric constant and band gap are adjusted by changing the material composition using the laminate of the present invention, and the device size and film thickness are optimized. Can be achieved. For example, in a varistor diode, it is sufficient if the varistor voltage can be controlled under a low leakage current and a low dielectric constant. However, since both the dielectric constant and the leakage current are small compared to a conventional zinc oxide system, it is optimal for the application. The material is appropriately selected. At this time, by setting the film thickness of the mixing layer present at the interface between the oxide semiconductor and the metal electrode to be more than 0.0 nm and not more than 5.0 nm, the varistor voltage can be designed correctly.
　無線タグやエネルギーハーベスターのような環境の電磁界から電力や信号を受電する際の、整流回路、電源回路、待機監視回路等に本発明の積層体を用いることができる。これらに使用される整流ダイオードは、低圧のＳｉ－ＳＢＤやＧｅダイオードが用いられるが、逆方向のリーク電流が大きく、電力変換効率の点で問題があった。しかし、本発明の積層体を使用すれば、ワイドギャップのためリーク電流が小さく、整流効果を高めることができる。順方向電圧は、膜厚とエネルギー準位の調整によりトンネル効果等も利用しながら低く抑えることができる。本積層体は特に温度の変化に対しても、高い整流効果を維持することができる。このとき、酸化物半導体と金属電極との界面に存在するミキシング層の好ましい膜厚は０．０ｎｍ超、５．０ｎｍ以下である。さらに、酸化物半導体はＳｉ、ＳｉＣ，ＧａＮ等の非酸化物半導体と異なり、アニール処理が必須でないため、従来困難だったＰＥＴやＰＣ等の樹脂基板上に整流回路を実装することが可能になる。 The laminate of the present invention can be used for a rectifier circuit, a power supply circuit, a standby monitoring circuit, and the like when receiving power or a signal from an electromagnetic field of an environment such as a wireless tag or an energy harvester. The rectifier diode used for these is a low-voltage Si-SBD or Ge diode, but has a large reverse leakage current, which has a problem in terms of power conversion efficiency. However, if the laminate of the present invention is used, the leak current is small because of the wide gap, and the rectifying effect can be enhanced. The forward voltage can be kept low by using the tunnel effect and the like by adjusting the film thickness and energy level. This laminated body can maintain a high rectifying effect even with respect to a change in temperature. At this time, the preferable film thickness of the mixing layer present at the interface between the oxide semiconductor and the metal electrode is more than 0.0 nm and not more than 5.0 nm. Furthermore, unlike non-oxide semiconductors such as Si, SiC, and GaN, an oxide semiconductor does not require an annealing process, and thus it is possible to mount a rectifier circuit on a resin substrate such as PET or PC, which has been difficult in the past. .
　本発明の積層体をＯＬＥＤ（Ｏｒｇａｎｉｃ　Ｌｉｇｈｔ　Ｅｍｉｔｔｉｎｇ　Ｄｉｏｄｅ）のカソード電極として用いた場合、駆動電圧の低下や画質の向上が期待できる。最近注目されている酸化物半導体はｎチャンネルのため、ＯＬＥＤのアノード側にソース電極が接続される。この接続方法の場合、ＯＬＥＤの駆動電圧変化がＴＦＴ動作にも影響し、輝度ムラを招くおそれがある。そこで、ドレイン電極上に本発明に使用する金属酸化物層を積層してカソードとすれば、ＯＬＥＤの駆動電圧変化がＴＦＴ動作に影響することを防止でき、画質を向上することができる。また、Ｃ１２Ａ７等の透明カソードを使用する場合も、ドレイン電極とＣ１２Ａ７の間に金属酸化物層を挟むことで、電子の注入レベルを合わせることができ、さらに駆動電圧を下げることができる。このとき、ドレイン電極と金属酸化物層の界面に高抵抗ミキシング層のないことが求められる。このような構成にすることで、輝度ムラの画質劣化を防止し、駆動電圧が低く、大面積化が可能なＯＬＥＤを実現することができる。
　センサーとしては、紫外線や放射線等の光センサー、酸素や窒素等のガスセンサー、イオン濃度や微生物等のバイオセンサー、温度変化を検知する熱センサーが挙げられる。
　また、不揮発相変化メモリー、太陽電池等、電極と酸化物半導体との組合せ界面の接触抵抗を小さく抑える必要のある部位に本発明の積層体を適用すると効果的である。 When the laminate of the present invention is used as a cathode electrode of an OLED (Organic Light Emitting Diode), a reduction in driving voltage and an improvement in image quality can be expected. Since an oxide semiconductor that has recently attracted attention is an n-channel, a source electrode is connected to the anode side of the OLED. In the case of this connection method, a change in the driving voltage of the OLED also affects the TFT operation, which may cause luminance unevenness. Therefore, if the metal oxide layer used in the present invention is stacked on the drain electrode to form a cathode, it is possible to prevent the change in the driving voltage of the OLED from affecting the TFT operation and improve the image quality. Also, when a transparent cathode such as C12A7 is used, an electron injection level can be adjusted by sandwiching a metal oxide layer between the drain electrode and C12A7, and the driving voltage can be further lowered. At this time, it is required that there is no high resistance mixing layer at the interface between the drain electrode and the metal oxide layer. With such a configuration, it is possible to realize an OLED capable of preventing image quality deterioration due to luminance unevenness, having a low driving voltage, and having a large area.
Examples of sensors include optical sensors such as ultraviolet rays and radiation, gas sensors such as oxygen and nitrogen, biosensors such as ion concentrations and microorganisms, and thermal sensors that detect temperature changes.
Further, it is effective to apply the laminate of the present invention to a portion where the contact resistance of the combined interface between the electrode and the oxide semiconductor needs to be kept small, such as a nonvolatile phase change memory and a solar cell.
　本発明の電子素子は、金属酸化物層及び第一の金属層の間、又は金属酸化物層及び支持体層の間では、オーミック特性又はショットキー特性を示す。
　また、金属酸化物層及び第二の金属層（金属層）の間が非線形の電気特性を示すことが好ましい。非線形の電気特性とは、オームの法則に従わない電気伝導をいう。
　非線形の電気特性として、整流特性、ショットキー特性が好ましい。
　金属酸化物層及び第二の金属層の間が非線形の電気特性を示すことにより、ショットキー接合素子とすることができる。 The electronic device of the present invention exhibits ohmic characteristics or Schottky characteristics between the metal oxide layer and the first metal layer, or between the metal oxide layer and the support layer.
Moreover, it is preferable that a non-linear electrical property is exhibited between the metal oxide layer and the second metal layer (metal layer). Non-linear electrical characteristics refer to electrical conduction that does not follow Ohm's law.
As the non-linear electrical characteristics, rectification characteristics and Schottky characteristics are preferable.
A non-linear electrical characteristic is exhibited between the metal oxide layer and the second metal layer, whereby a Schottky junction element can be obtained.
　特に、本発明の積層体をダイオードに用いた場合、高速スイッチング、高耐圧、低Ｏｎ抵抗の特性を量産レベルで実現することができる。
　金属酸化物が酸素欠損によりｎ型になりやすく、ｐ型ができにくい場合、ユニポーラデバイスとなり、高速スイッチング用途にすることが好ましい。 In particular, when the laminated body of the present invention is used for a diode, the characteristics of high-speed switching, high breakdown voltage, and low On resistance can be realized at the mass production level.
When the metal oxide is likely to be n-type due to oxygen deficiency and difficult to be p-type, it becomes a unipolar device and is preferably used for high-speed switching.
　本発明の積層体をダイオードに用いた場合、ダイオードの理想係数が、ｎ＝１～５の範囲であることが好ましい。ダイオードの理想係数とは、非線形の電気特性を示す電圧－電流特性を、以下の式で近似した時に定まるｎで示される。式中、Ｉは電流であり、Ｉ０は定数であり、ｑは電荷素量であり、Ｖは印加電圧であり、ｋはボルツマン定数であり、Ｔは絶対温度である。
　Ｉ＝Ｉ０｛ｅｘｐ（ｑＶ／ｎｋＴ）－１｝ When the laminate of the present invention is used for a diode, the ideality factor of the diode is preferably in the range of n = 1-5. The ideality factor of a diode is represented by n that is determined when a voltage-current characteristic indicating nonlinear electrical characteristics is approximated by the following expression. In the formula, I is a current, I 0 is a constant, q is an elementary charge, V is an applied voltage, k is a Boltzmann constant, and T is an absolute temperature.
I = I 0 {exp (qV / nkT) −1}
　また、本発明の積層体をダイオードに用いた場合、基板側がオーミック接合のため、後工程の親和性が高くなるため、好ましい。
　本発明の積層体を、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）やＭＯＳＦＥＴ等のスイッチング素子と組み合わせて高速ＦＷＤ（Ｆｒｅｅ　Ｗｈｅｅｌ　Ｄｉｏｄｅ）チップとして用いる場合、従来と同様の配線レイアウトで設計することができる。また、順方向の立ち上がり電圧を低く抑えることができるので、環境発電回路に用いる低圧ダイオードにも適している。 Moreover, when the laminated body of this invention is used for a diode, since the board | substrate side is ohmic junction and the affinity of a post process becomes high, it is preferable.
When the stacked body of the present invention is used as a high-speed FWD (Free Wheel Diode) chip in combination with a switching element such as an insulated gate bipolar transistor (IGBT) or MOSFET, it can be designed with a wiring layout similar to the conventional one. In addition, since the forward rising voltage can be kept low, it is also suitable for a low voltage diode used in an energy harvesting circuit.
　以下、適宜図面を参照しながら本発明の実施例を説明する。本発明は、これら実施例によって何ら限定されるものではない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings as appropriate. The present invention is not limited to these examples.
実施例１
　支持体として、抵抗率０．０２Ω・ｃｍのｎ型Ｓｉ基板（直径４インチ、ケイ・エス・ティ・ワールド株式会社製のｎ型Ｓｉ基板）を用意した。これをスパッタリング装置ＣＳ－２００（ＵＬＶＡＣ製）に装着し、最初に逆スパッタモードで１５秒処理し、自然酸化膜の一部をエッチング後、Ｍｏターゲットに対してＤＣスパッタを行い、１５ｎｍのＭｏを成膜した（第一の金属層）。
　次にイオンプレーティング装置ＳＩＰ－８００（昭和真空製）に、一辺が１ｍｍの正方形のパターンが形成されるようなエリアマスクを介して、このＭｏ付き支持基板をセットし、イオンプレーティング（ＩＰ）法によって１０００ｎｍのＧａ２Ｏ３膜を成膜した（金属酸化物層）。
　このＳｉウェハー／Ｍｏ／Ｇａ２Ｏ３積層体を再びスパッタリング装置ＣＳ－２００に装着し、電極用のエリアマスクを介してＧａ２Ｏ３膜上に、Ｔｉを１５０ｎｍで成膜した（第二の金属層）。 Example 1
As a support, an n-type Si substrate having a resistivity of 0.02 Ω · cm (an n-type Si substrate having a diameter of 4 inches and manufactured by KST World Co., Ltd.) was prepared. This was installed in a sputtering apparatus CS-200 (manufactured by ULVAC), first treated in reverse sputtering mode for 15 seconds, part of the natural oxide film was etched, DC sputtering was performed on the Mo target, and 15 nm of Mo was deposited. A film was formed (first metal layer).
Next, this Mo-supported substrate is set in an ion plating apparatus SIP-800 (made by Showa Vacuum) through an area mask on which a square pattern with a side of 1 mm is formed, and ion plating (IP) A 1000 nm Ga 2 O 3 film was formed by a method (metal oxide layer).
This Si wafer / Mo / Ga 2 O 3 laminate was again mounted on the sputtering apparatus CS-200, and Ti was deposited at a thickness of 150 nm on the Ga 2 O 3 film via an electrode area mask (secondary film). Metal layer).
　得られたＳｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ積層体のＩＶ特性を４２００－ＳＣＳ（株式会社ケースＬ－インスツルメンツ社製）により評価したところ、オーミック特性が得られた。
　結果を図３に示す。図３は、実施例１及び比較例１のＩＶ特性の図である。 When the IV characteristics of the obtained Si / Mo / Ga 2 O 3 / Ti laminate were evaluated by 4200-SCS (manufactured by Case L Instruments Co., Ltd.), ohmic characteristics were obtained.
The results are shown in FIG. FIG. 3 is a diagram of IV characteristics of Example 1 and Comparative Example 1.
　また、Ｍｏ層とＧａ２Ｏ３層の界面を、集束イオンビーム（ＦＩＢ）で加工した後にＴＥＭで観察した。図４に、実施例１のＳｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真を示す。
　観測箇所として、金属酸化物層の対角線の交点と、交点と各頂点の中間点の計５点の視野を観察し、その視野を等間隔に１０等分する箇所で、金属酸化物層と、第一の金属層との界面を測定し、その計５５か所の平均値をミキシング層の膜厚とした。その結果、解析限界を下回り、ミキシング層の存在は認められなかった。 Further, the interface between the Mo layer and the Ga 2 O 3 layer was observed with a TEM after being processed with a focused ion beam (FIB). Figure 4 shows a cross-sectional TEM photograph of Si / Mo / Ga 2 O 3 / Ti laminate of Example 1.
As observation points, the intersections of the diagonal lines of the metal oxide layer and the field of view of a total of five points of the midpoint between the intersection and each vertex are observed, and the metal oxide layer is divided into 10 equal parts at equal intervals. The interface with the first metal layer was measured, and the average value of a total of 55 locations was taken as the film thickness of the mixing layer. As a result, the analysis limit was exceeded, and no mixing layer was observed.
比較例１
　イオンプレーティング装置ＳＩＰ－８００に代えて、スパッタリング装置ＣＳ－２００を用い、ＲＦスパッタ法によりＧａ２Ｏ３膜を成膜した以外、実施例１と同様にして、Ｓｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ積層体を製造し、評価した。
　尚、ＲＦパワーは４インチターゲットに対して３００Ｗ（３．７０Ｗ／ｃｍ２）であった。ダイオード理想係数は、ｎ＝５．５であった。 Comparative Example 1
A Si / Mo / Ga 2 O 3 film was formed in the same manner as in Example 1 except that a sputtering apparatus CS-200 was used instead of the ion plating apparatus SIP-800 and a Ga 2 O 3 film was formed by RF sputtering. / Ti laminate was manufactured and evaluated.
The RF power was 300 W (3.70 W / cm 2 ) for a 4-inch target. The diode ideality factor was n = 5.5.
　ＩＶ特性を評価したところ、整流特性が得られた。結果を図３に示す。
　ミキシング層の膜厚は６ｎｍであった。図５に、比較例１のＳｉ／Ｍｏ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真を示す。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 When the IV characteristics were evaluated, rectification characteristics were obtained. The results are shown in FIG.
The thickness of the mixing layer was 6 nm. Figure 5 shows a cross-sectional TEM photograph of Si / Mo / Ga 2 O 3 / Ti laminate of Comparative Example 1. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
実施例２
　Ｍｏを成膜しなかった以外は、実施例１と同様にして、Ｓｉ／Ｇａ２Ｏ３／Ｔｉ積層体を製造し、評価した。 Example 2
A Si / Ga 2 O 3 / Ti laminate was produced and evaluated in the same manner as in Example 1 except that no Mo film was formed.
　ＩＶ特性を評価したところ、オーミック特性が得られた。結果を図６に示す。図６は、実施例２及び比較例２のＩＶ特性の図である。
　ミキシング層の膜厚は４ｎｍであった。図７に、実施例２のＳｉ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真を示す。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 When the IV characteristics were evaluated, ohmic characteristics were obtained. The results are shown in FIG. FIG. 6 is a diagram of IV characteristics of Example 2 and Comparative Example 2.
The thickness of the mixing layer was 4 nm. Figure 7 shows a cross-sectional TEM photograph of Si / Ga 2 O 3 / Ti laminate of Example 2. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
比較例２
　Ｍｏを成膜しなかった以外は、比較例１と同様にして、Ｓｉ／Ｇａ２Ｏ３／Ｔｉ積層体を製造し、評価した。
　ＩＶ特性を評価したところ、負性抵抗が得られた。結果を図６に示す。これはＭＩＳ構造によるトンネル電流が発現したものと考えられる。
　ミキシング層の膜厚は９ｎｍであった。図８に、比較例２のＳｉ／Ｇａ２Ｏ３／Ｔｉ積層体の断面ＴＥＭ写真を示す。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 Comparative Example 2
A Si / Ga 2 O 3 / Ti laminate was produced and evaluated in the same manner as in Comparative Example 1 except that no Mo film was formed.
When IV characteristics were evaluated, negative resistance was obtained. The results are shown in FIG. This is considered that the tunnel current by MIS structure was expressed.
The thickness of the mixing layer was 9 nm. Figure 8 shows a cross-sectional TEM photograph of Si / Ga 2 O 3 / Ti laminate of Comparative Example 2. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
実施例３
　Ｔｉに代えて、ＩＺＯを用いた以外は実施例１と同様にしてＳｉ／Ｍｏ／Ｇａ２Ｏ３／ＩＺＯ積層体を作製した。
　実施例１と同様に、得られたＳｉ／Ｍｏ／Ｇａ２Ｏ３／ＩＺＯ積層体のＩＶ特性を評価したところ、Ｇａ２Ｏ３層とＭｏ層の界面はオーミックで、Ｇａ２Ｏ３層とＩＺＯ層の界面は整流特性であった。ショットキー接合素子が得られた。
　また、実施例１と同様にミキシング層の膜厚を測定したところ、解析限界を下回り、ミキシング層の存在は認められなかった。 Example 3
A Si / Mo / Ga 2 O 3 / IZO laminate was produced in the same manner as in Example 1 except that IZO was used instead of Ti.
As in Example 1, when the IV characteristics of the obtained Si / Mo / Ga 2 O 3 / IZO laminate were evaluated, the interface between the Ga 2 O 3 layer and the Mo layer was ohmic, and the Ga 2 O 3 layer and The interface of the IZO layer had rectification characteristics. A Schottky junction element was obtained.
Further, when the film thickness of the mixing layer was measured in the same manner as in Example 1, it was below the analysis limit and the presence of the mixing layer was not recognized.
実施例４
　支持体として、実施例１と同じｎ型Ｓｉを用意し、希フッ酸（ＨＦ：Ｈ２Ｏ＝１：５０）に１分間浸漬して表面の自然酸化膜を除去後、速やかにスパッタリング装置ＣＳ－２００（ＵＬＶＡＣ製）に投入し、チャンバーを真空排気した。１０－４Ｐａ台に排気後、Ｔｉターゲットに対してＤＣスパッタを行い、厚さ５０ｎｍのＴｉを成膜し、続いてＮｉターゲットに対してＤＣスパッタを行い、厚さ５０ｎｍのＮｉ薄膜を得た。
　大気解放後、スパッタリング装置ＳＲＶ－４３００（神港精機製）にＳｉ／Ｔｉ／Ｎｉ積層体を取りつけ、Ｉｎターゲットに対してＤＣスパッタを行い、厚さ５０ｎｍのＩｎ膜（第一の金属層）をＮｉ膜上に成膜した。続いて真空をブレークせずに、ａ－ＩＧＺＯ（Ｉｎ：Ｇａ：Ｚｎ＝１：１：１）のターゲットに対してＲＦ１００Ｗ（１．２３Ｗ／ｃｍ２）のパワーで２００ｎｍのａ－ＩＧＺＯ膜（金属酸化物層）をＩｎ膜上に成膜した。
　一旦大気に取出して、空気中、３００℃、１時間の条件でアニール後、再度スパッタリング装置ＳＲＶ－４３００に取り付けて、電極マスクで覆い、Ｔｉ，Ａｕの順にスパッタ成膜を行った（第二の金属層）。 Example 4
As the support, the same n-type Si as in Example 1 was prepared and immersed in dilute hydrofluoric acid (HF: H2O = 1: 50) for 1 minute to remove the natural oxide film on the surface, and then quickly the sputtering apparatus CS-200. (ULVAC) and the chamber was evacuated. After evacuation to the 10 −4 Pa level, DC sputtering was performed on the Ti target to form a Ti film with a thickness of 50 nm, followed by DC sputtering on the Ni target to obtain a Ni thin film with a thickness of 50 nm. .
After release to the atmosphere, the Si / Ti / Ni laminate was attached to the sputtering apparatus SRV-4300 (manufactured by Shinko Seiki), DC sputtering was performed on the In target, and an In film (first metal layer) having a thickness of 50 nm was formed. A film was formed on the Ni film. Subsequently, a 200-nm a-IGZO film (metal) with a power of RF 100 W (1.23 W / cm 2 ) against a target of a-IGZO (In: Ga: Zn = 1: 1: 1) without breaking the vacuum. An oxide layer was formed on the In film.
Once taken out to the atmosphere and annealed in air at 300 ° C. for 1 hour, it was attached again to the sputtering apparatus SRV-4300, covered with an electrode mask, and sputtered in the order of Ti and Au (second film was formed). Metal layer).
　このようにして得たＡｕ／Ｔｉ／ａ－ＩＧＺＯ／Ｉｎ／Ｎｉ／Ｔｉ／Ｓｉ構成の積層体について、ＩＶ特性を４２００－ＳＣＳを用いて評価したところ、オーミック特性が得られた。結果を図９に示す。
　実施例１と同様にしてＩｎ層とａ－ＩＧＺＯ層の界面のミキシング層の厚みを評価した結果、４ｎｍであった。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 When the laminated body having the Au / Ti / a-IGZO / In / Ni / Ti / Si structure thus obtained was evaluated using 4200-SCS, ohmic characteristics were obtained. The results are shown in FIG.
The thickness of the mixing layer at the interface between the In layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and the result was 4 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
比較例３
　Ｉｎの代わりにＭｏを用い、ＩＧＺＯの成膜パワーを２００Ｗ（２．４７Ｗ／ｃｍ２）とした他は、実施例４と同様にして成膜を行い、Ａｕ／Ｔｉ／ａ－ＩＧＺＯ／Ｍｏ／Ｎｉ／Ｔｉ／Ｓｉ構成の積層体を得た。この積層体についてＩＶ特性を４２００－ＳＣＳを用いて評価したところ、非オーミック特性が得られた。結果を図９に示す。
　また、実施例１と同様にしてＭｏ層とａ－ＩＧＺＯ層の界面のミキシング層の厚みを評価した結果、８ｎｍであった。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 Comparative Example 3
The film was formed in the same manner as in Example 4 except that Mo was used instead of In and the film formation power of IGZO was 200 W (2.47 W / cm 2 ), and Au / Ti / a-IGZO / Mo / A laminate having a Ni / Ti / Si structure was obtained. When this laminate was evaluated for IV characteristics using 4200-SCS, non-ohmic characteristics were obtained. The results are shown in FIG.
Further, the thickness of the mixing layer at the interface between the Mo layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and as a result, it was 8 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
比較例４
　Ｉｎの代わりにＣｒを用い、ＩＧＺＯの成膜パワーを４００Ｗ（４．９３Ｗ／ｃｍ２）とした他は、実施例４と同様にして成膜を行い、Ａｕ／Ｔｉ／ａ－ＩＧＺＯ／Ｃｒ／Ｎｉ／Ｔｉ／Ｓｉ構成の積層体を得た。この積層体についてＩＶ特性を４２００－ＳＣＳを用いて評価したところ、非オーミック特性が得られた。結果を図９に示す。
　また、実施例１と同様にしてＣｒ層とａ－ＩＧＺＯ層の界面のミキシング層の厚みを評価した結果、２０ｎｍであった。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 Comparative Example 4
The film was formed in the same manner as in Example 4 except that Cr was used instead of In and the film formation power of IGZO was set to 400 W (4.93 W / cm 2 ), and Au / Ti / a-IGZO / Cr / A laminate having a Ni / Ti / Si structure was obtained. When this laminate was evaluated for IV characteristics using 4200-SCS, non-ohmic characteristics were obtained. The results are shown in FIG.
Further, the thickness of the mixing layer at the interface between the Cr layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and as a result, it was 20 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
　実施例４では、ＩＧＺＯのＲＦスパッタを１．５Ｗ／ｃｍ２以下のパワーで実施したため、Ｉｎに対する打ち込み効果が抑制され、ミキシング層も５ｎｍ未満となり、オーミック特性が得られた。一方、比較例３と比較例４では、ＩＧＺＯのＲＦスパッタを１．５Ｗ／ｃｍ２超の高パワーで実施したため、ＭｏやＣｒが酸化して高抵抗のミキシング層を形成し、非オーミック特性となった。 In Example 4, since the RF sputtering of IGZO was performed with a power of 1.5 W / cm 2 or less, the implantation effect on In was suppressed, the mixing layer was less than 5 nm, and ohmic characteristics were obtained. On the other hand, in Comparative Example 3 and Comparative Example 4, since RF sputtering of IGZO was performed with a high power exceeding 1.5 W / cm 2 , Mo and Cr were oxidized to form a high-resistance mixing layer, and non-ohmic characteristics and became.
実施例５
　支持体として、樹脂基板（東レのＰＥＴ基板、ルミラー６０）を準備し、これをスパッタリング装置ＣＳ－２００（ＵＬＶＡＣ製）に装着し、Ｐｄターゲットに対してＤＣスパッタを行い、５０ｎｍのＰｄを成膜した（第一の金属層）。一旦大気中に取出して、一辺が１ｍｍの正方形のパターンが形成されるようなエリアマスクを介して、このＰｄ付き支持基板を再度スパッタリング装置ＣＳ－２００にセットし、ＲＦスパッタリング（パワー１００Ｗ、１．２３Ｗ／ｃｍ２）によって５０ｎｍのＩＧＯ膜（Ｉｎ：Ｇａ＝５０：５０ａｔ％）を成膜した（金属酸化物層）。
　このＰＥＴ／Ｐｄ／ＩＧＯ積層体を再び大気中に取り出し、電極用のエリアマスクをセットして、スパッタリング装置ＣＳ－２００に装着し、ＩＧＯ膜上に、Ｔｉ、Ａｕの順にそれぞれ５０ｎｍ成膜した（第二の金属層）。 Example 5
A resin substrate (Toray PET substrate, Lumirror 60) is prepared as a support, and this is mounted on a sputtering apparatus CS-200 (manufactured by ULVAC), and DC sputtering is performed on a Pd target to form a 50 nm Pd film. (First metal layer). Once taken out into the atmosphere, this support substrate with Pd is set again in the sputtering apparatus CS-200 through an area mask that forms a square pattern with a side of 1 mm, and RF sputtering (power 100 W, 1.. 23 W / cm 2 ) to form a 50 nm IGO film (In: Ga = 50: 50 at%) (metal oxide layer).
This PET / Pd / IGO laminate was taken out again into the atmosphere, an electrode area mask was set and mounted on the sputtering apparatus CS-200, and 50 nm of Ti and Au were deposited in this order on the IGO film ( Second metal layer).
　得られたＰＥＴ／Ｐｄ／ＩＧＯ／Ｔｉ／Ａｕ積層体のＩＶ特性を４２００－ＳＣＳ（株式会社ケースＬ－インスツルメンツ社製）により評価したところ、第一の金属層Ｐｄと金属酸化物層ＩＧＯとの界面をオーミック接合とし、金属酸化物層ＩＧＯと第二の金属層Ｔｉとの界面をショットキー接合とするダイオード特性が得られた。また、ダイオードの理想係数ｎを評価したところ、４．７であった。
　また、実施例１と同様にして、第一の金属層Ｐｄと金属酸化物層ＩＧＯとの界面のミキシング層の厚みを評価した結果、３ｎｍであった。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 When the IV characteristics of the obtained PET / Pd / IGO / Ti / Au laminate were evaluated by 4200-SCS (Case L-Instruments, Inc.), the first metal layer Pd and the metal oxide layer IGO Diode characteristics were obtained in which the interface was an ohmic junction and the interface between the metal oxide layer IGO and the second metal layer Ti was a Schottky junction. The ideality factor n of the diode was evaluated to be 4.7.
Moreover, it was 3 nm as a result of evaluating the thickness of the mixing layer of the interface of 1st metal layer Pd and metal oxide layer IGO like Example 1. FIG. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
比較例５
　金属酸化物層をスパッタ成膜する際のＲＦパワーを３００Ｗ（３．７０Ｗ／ｃｍ２）としたこと以外は、実施例５と同様にして、ＰＥＴ／Ｐｄ／ＩＧＯ／Ｔｉ／Ａｕ構成のショットキーバリアダイオードを得た。得られたダイオード特性は、実施例５と同様に第一の金属層Ｐｄと金属酸化物層ＩＧＯとの界面をショットキー接合とすることを確認したが、ダイオード理想係数ｎは１５となった。
　実施例１と同様にして、第一の金属層Ｐｄと金属酸化物層ＩＧＯとの界面のミキシング層の厚みを評価した結果、７ｎｍであった。尚、エネルギー分散型Ｘ線分析装置により確認した結果、ミキシング層は、酸化物層を構成する元素と、第一の金属層を構成する元素との混合層であった。 Comparative Example 5
A Schottky with a PET / Pd / IGO / Ti / Au configuration was used in the same manner as in Example 5 except that the RF power when the metal oxide layer was formed by sputtering was 300 W (3.70 W / cm 2 ). A barrier diode was obtained. As for the obtained diode characteristics, it was confirmed that the interface between the first metal layer Pd and the metal oxide layer IGO was a Schottky junction as in Example 5, but the diode ideality factor n was 15.
As a result of evaluating the thickness of the mixing layer at the interface between the first metal layer Pd and the metal oxide layer IGO in the same manner as in Example 1, it was 7 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
　支持体と金属酸化物層の間に金属層（第一の金属層）を有する積層体を製造及び評価した実施例１及び３－５並びに比較例１及び３－５の評価結果を表１に示す。
　また、支持体と金属酸化物層との間に金属層を有さない積層体を製造及び評価した実施例２及び比較例２の評価結果を表２に示す。 Table 1 shows the evaluation results of Examples 1 and 3-5 and Comparative Examples 1 and 3-5 in which a laminate having a metal layer (first metal layer) between the support and the metal oxide layer was produced and evaluated. Show.
Table 2 shows the evaluation results of Example 2 and Comparative Example 2 in which a laminate having no metal layer between the support and the metal oxide layer was produced and evaluated.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000002
Figure JPOXMLDOC01-appb-T000002
　本発明の積層体は、電子素子等に用いることができる。また、本発明の電子素子は、電気回路、電気機器や車両に使用できる。 The laminate of the present invention can be used for electronic devices and the like. In addition, the electronic device of the present invention can be used for electric circuits, electric devices, and vehicles.
　上記に本発明の実施形態及び／又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び／又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
　本願のパリ優先の基礎となる日本出願明細書の内容を全てここに援用する。 Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
All the contents of the Japanese application specification that is the basis of the priority of Paris in this application are incorporated herein.

Claims (16)

  1. 　支持体層、金属酸化物層の順に、又は支持体層、ミキシング層、金属酸化物層の順に積層され、前記ミキシング層の膜厚が０ｎｍ超５．０ｎｍ以下である積層体。 A laminate in which the support layer, the metal oxide layer, or the support layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer is greater than 0 nm and less than 5.0 nm.
  2. 　前記ミキシング層が、前記金属酸化物層を構成する元素及び支持体層を構成する元素の混合相である請求項１に記載の積層体。 The laminate according to claim 1, wherein the mixing layer is a mixed phase of an element constituting the metal oxide layer and an element constituting the support layer.
  3. 　前記支持体層が、Ｓｉ基板、ＳｉＣ基板、ＧａＮ基板、Ａｌ２Ｏ３基板、ＺｎＯ基板、Ｇａ２Ｏ３基板、イットリア安定ジルコニア基板及びチタン酸ストロンチウム基板から選ばれる基板である請求項１又は２に記載の積層体。 3. The substrate is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate. The laminated body as described in.
  4. 　前記金属酸化物層がＩｎ，Ｓｎ，Ｇｅ，Ｔｉ，Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ，Ｇａ及びＡｌのいずれか１以上を含有する金属酸化物を含む請求項１～３のいずれかに記載の積層体。 4. The metal oxide layer according to claim 1, wherein the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. Laminated body.
  5. 　前記金属酸化物層がＩｎ２Ｏ３，ＺｎＯ，Ｇａ２Ｏ３，ＳｎＯ２、インジウムアルミニウム酸化物、インジウムガリウム亜鉛酸化物、インジウムスズ亜鉛酸化物、ガリウム亜鉛酸化物、インジウム亜鉛酸化物及びインジウムガリウム酸化物から選ばれる１以上の金属酸化物を含む請求項１～４のいずれかに記載の積層体。 The metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium. The laminate according to any one of claims 1 to 4, comprising one or more metal oxides selected from oxides.
  6. 　支持体層、第一の金属層、金属酸化物層の順に、又は支持体層、第一の金属層、ミキシング層、金属酸化物層の順に積層され、前記ミキシング層の膜厚が０ｎｍ超５．０ｎｍ以下である積層体。 The support layer, the first metal layer, and the metal oxide layer are laminated in this order, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer exceeds 0 nm. A laminate having a thickness of 0.0 nm or less.
  7. 　前記ミキシング層が、前記金属酸化物層を構成する元素及び第一の金属層を構成する元素の混合相である請求項６に記載の積層体。 The laminate according to claim 6, wherein the mixing layer is a mixed phase of an element constituting the metal oxide layer and an element constituting the first metal layer.
  8. 　前記支持体層が、Ｓｉ基板、ＳｉＣ基板、ＧａＮ基板、Ａｌ２Ｏ３基板、ＺｎＯ基板、Ｇａ２Ｏ３基板、イットリア安定ジルコニア基板及びチタン酸ストロンチウム基板から選ばれる基板である請求項６又は７に記載の積層体。 8. The substrate is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate. The laminated body as described in.
  9. 　前記金属酸化物層がＩｎ，Ｓｎ，Ｇｅ，Ｔｉ，Ｚｎ，Ｙ，Ｓｍ，Ｃｅ，Ｎｄ，Ｇａ及びＡｌのいずれか１以上を含有する金属酸化物を含む請求項６～８のいずれかに記載の積層体。 9. The metal oxide layer according to claim 6, wherein the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. Laminated body.
  10. 　前記金属酸化物層がＩｎ２Ｏ３，ＺｎＯ，Ｇａ２Ｏ３，ＳｎＯ２、インジウムアルミニウム酸化物、インジウムガリウム亜鉛酸化物、インジウムスズ亜鉛酸化物、ガリウム亜鉛酸化物、インジウム亜鉛酸化物及びインジウムガリウム酸化物から選ばれる１以上の金属酸化物を含む請求項６～９のいずれかに記載の積層体。 The metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium. The laminate according to any one of claims 6 to 9, comprising one or more metal oxides selected from oxides.
  11. 　金属酸化物層を、低電圧スパッタリング法、プラズマ化学蒸着法、有機金属化学蒸着法、ミスト化学蒸着法、分子線エピタキシー法及びイオンプレーティング法から選ばれる成膜法を用いて、支持体層上に形成する積層体の製造方法。 The metal oxide layer is formed on the support layer using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method. The manufacturing method of the laminated body formed in 1st.
  12. 　金属酸化物層を、低電圧スパッタリング法、プラズマ化学蒸着法、有機金属化学蒸着法、ミスト化学蒸着法、分子線エピタキシー法及びイオンプレーティング法から選ばれる成膜法を用いて、金属層上に形成する積層体の製造方法。 The metal oxide layer is formed on the metal layer by using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method. The manufacturing method of the laminated body to form.
  13. 　請求項１～５のいずれかに記載の積層体を含む電子素子であって、金属酸化物層上にさらに金属層を有し、金属酸化物層及び支持体層の間でオーミック特性を示す電子素子。 An electronic device comprising the laminate according to any one of claims 1 to 5, further comprising a metal layer on the metal oxide layer, and exhibiting ohmic characteristics between the metal oxide layer and the support layer. element.
  14. 　請求項６～１０のいずれかに記載の積層体を含む電子素子であって、金属酸化物層上にさらに第二の金属層を有し、金属酸化物層及び第一の金属層の間でオーミック特性を示す電子素子。 An electronic device comprising the laminate according to any one of claims 6 to 10, further comprising a second metal layer on the metal oxide layer, wherein the second metal layer is interposed between the metal oxide layer and the first metal layer. An electronic device exhibiting ohmic characteristics.
  15. 　前記金属酸化物層及び金属層の間、又は前記金属酸化物層及び第二の金属層の間が非線形の電気特性を示す請求項１３又は１４に記載の電子素子。 The electronic device according to claim 13 or 14, wherein non-linear electrical characteristics are exhibited between the metal oxide layer and the metal layer, or between the metal oxide layer and the second metal layer.
  16. 　請求項１３～１５のいずれかに記載の電子素子を１以上用いた、電気回路、電気機器又は車両。 An electric circuit, an electric device or a vehicle using one or more of the electronic elements according to any one of claims 13 to 15.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110896024A (en) * 2019-10-14 2020-03-20 西安电子科技大学 Silicon carbide epitaxial gallium oxide film method and silicon carbide epitaxial gallium oxide film structure
CN110993505A (en) * 2019-10-14 2020-04-10 西安电子科技大学 Semiconductor structure preparation method based on silicon carbide substrate and semiconductor structure
WO2021090790A1 (en) * 2019-11-08 2021-05-14 出光興産株式会社 Laminate and semiconductor device
KR20220076010A (en) * 2020-11-30 2022-06-08 서울대학교산학협력단 Manufacturing method of alpha-gallium oxide thin film using of alpha-aluminum gallium oxide buffer layer

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1053867A (en) * 1996-08-08 1998-02-24 Canon Inc Wiring board and its production
JP2004214434A (en) * 2003-01-06 2004-07-29 Sharp Corp Oxide semiconductor light emitting element and its manufacturing method
JP2005108982A (en) * 2003-09-29 2005-04-21 Sanyo Electric Co Ltd Semiconductor light-emitting element
JP2010073820A (en) * 2008-09-17 2010-04-02 Dowa Electronics Materials Co Ltd Electrode film for semiconductor element with conductive connection portion and manufacturing method thereof, and light emitting element with the electrode film for the semiconductor element
WO2012137781A1 (en) * 2011-04-08 2012-10-11 株式会社タムラ製作所 Semiconductor stacked body, method for manufacturing same, and semiconductor element
WO2013035472A1 (en) * 2011-09-08 2013-03-14 株式会社タムラ製作所 Substrate for epitaxial growth, and crystal laminate structure
JP2014241404A (en) * 2013-05-16 2014-12-25 株式会社半導体エネルギー研究所 Semiconductor device
JP2015227279A (en) * 2014-05-08 2015-12-17 株式会社Flosfia Crystalline laminated structure and semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1053867A (en) * 1996-08-08 1998-02-24 Canon Inc Wiring board and its production
JP2004214434A (en) * 2003-01-06 2004-07-29 Sharp Corp Oxide semiconductor light emitting element and its manufacturing method
JP2005108982A (en) * 2003-09-29 2005-04-21 Sanyo Electric Co Ltd Semiconductor light-emitting element
JP2010073820A (en) * 2008-09-17 2010-04-02 Dowa Electronics Materials Co Ltd Electrode film for semiconductor element with conductive connection portion and manufacturing method thereof, and light emitting element with the electrode film for the semiconductor element
WO2012137781A1 (en) * 2011-04-08 2012-10-11 株式会社タムラ製作所 Semiconductor stacked body, method for manufacturing same, and semiconductor element
WO2013035472A1 (en) * 2011-09-08 2013-03-14 株式会社タムラ製作所 Substrate for epitaxial growth, and crystal laminate structure
JP2014241404A (en) * 2013-05-16 2014-12-25 株式会社半導体エネルギー研究所 Semiconductor device
JP2015227279A (en) * 2014-05-08 2015-12-17 株式会社Flosfia Crystalline laminated structure and semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110896024A (en) * 2019-10-14 2020-03-20 西安电子科技大学 Silicon carbide epitaxial gallium oxide film method and silicon carbide epitaxial gallium oxide film structure
CN110993505A (en) * 2019-10-14 2020-04-10 西安电子科技大学 Semiconductor structure preparation method based on silicon carbide substrate and semiconductor structure
CN110896024B (en) * 2019-10-14 2023-08-04 西安电子科技大学 Silicon carbide epitaxial gallium oxide film method and silicon carbide epitaxial gallium oxide film structure
CN110993505B (en) * 2019-10-14 2023-08-04 西安电子科技大学 Preparation method of semiconductor structure based on silicon carbide substrate and semiconductor structure
WO2021090790A1 (en) * 2019-11-08 2021-05-14 出光興産株式会社 Laminate and semiconductor device
KR20220076010A (en) * 2020-11-30 2022-06-08 서울대학교산학협력단 Manufacturing method of alpha-gallium oxide thin film using of alpha-aluminum gallium oxide buffer layer
KR102537070B1 (en) 2020-11-30 2023-05-26 서울대학교산학협력단 Manufacturing method of alpha-gallium oxide thin film using of alpha-aluminum gallium oxide buffer layer

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