WO2016132681A1 - Produit constitué de couches et procédé de fabrication d'un produit constitué de couches - Google Patents

Produit constitué de couches et procédé de fabrication d'un produit constitué de couches Download PDF

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WO2016132681A1
WO2016132681A1 PCT/JP2016/000345 JP2016000345W WO2016132681A1 WO 2016132681 A1 WO2016132681 A1 WO 2016132681A1 JP 2016000345 W JP2016000345 W JP 2016000345W WO 2016132681 A1 WO2016132681 A1 WO 2016132681A1
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layer
metal
metal oxide
substrate
oxide layer
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PCT/JP2016/000345
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English (en)
Japanese (ja)
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重和 笘井
義弘 上岡
隆司 関谷
勇輝 霍間
絵美 川嶋
基浩 竹嶋
井上　一吉
紘美 早坂
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出光興産株式会社
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Priority to JP2017500494A priority Critical patent/JPWO2016132681A1/ja
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B9/00—Layered products comprising a layer of a particular substance not covered by groups B32B11/00 - B32B29/00
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/872—Schottky diodes

Definitions

  • the present invention relates to a laminate and a method for producing the laminate.
  • metal oxides include degenerate semiconductors such as indium tin oxide (ITO) and indium zinc oxide (IZO (registered trademark)), and non-degenerate semiconductors such as ZnO and indium gallium zinc oxide (IGZO). It has been. These have been put to practical use in displays, sensors, varistors, etc., taking advantage of the wide band gap.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • IGZO indium gallium zinc oxide
  • An electronic device using an oxide material tends to have a metal-insulator-semiconductor (MIS) structure due to the reaction of oxide oxygen with the electrode depending on the selection of the electrode material.
  • MIS structure may cause an increase in contact resistance, increase power consumption, and cause a decrease in response.
  • Patent Document 1 proposes a technique for suppressing the generation of an oxide film by using an Al alloy to which a small amount of a noble metal that is not easily oxidized by Al or a metal having a relatively low electrical conductivity as an oxide is used.
  • An object of the present invention is to provide a laminate having no contact resistance and a method for producing the laminate.
  • the problem of contact resistance becomes more prominent.
  • TFTs thin film transistors
  • a bottom contact type TFT in which an oxide semiconductor is formed after source and drain electrodes tends to have high contact resistance.
  • the contact resistance is increased, the voltage-current characteristic deviates from the ohmic characteristic, so that the image quality is lowered in the case of TFT, and the power conversion efficiency is lowered in the case of a power device.
  • FIG. 11 shows a typical example of voltage-current characteristics when the contact resistance is kept small.
  • the mixing layer is a mixed phase of an element constituting the metal oxide layer and an element constituting the support layer.
  • the support layer is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate. Laminated body. 4).
  • the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. body. 5.
  • the metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium.
  • the support layer, the first metal layer, and the metal oxide layer are laminated in this order, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer exceeds 0 nm.
  • the support layer is a substrate selected from a Si substrate, a SiC substrate, a GaN substrate, an Al 2 O 3 substrate, a ZnO substrate, a Ga 2 O 3 substrate, an yttria stable zirconia substrate, and a strontium titanate substrate.
  • Laminated body 9.
  • the metal oxide layer includes a metal oxide containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al. body. 10.
  • the metal oxide layer is In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , indium aluminum oxide, indium gallium zinc oxide, indium tin zinc oxide, gallium zinc oxide, indium zinc oxide, and indium gallium.
  • the laminate according to any one of 6 to 9, comprising one or more metal oxides selected from oxides. 11.
  • the metal oxide layer is formed on the support layer using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method.
  • the metal oxide layer is formed on the metal layer by using a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method.
  • a film forming method selected from a low voltage sputtering method, a plasma chemical vapor deposition method, a metal organic chemical vapor deposition method, a mist chemical vapor deposition method, a molecular beam epitaxy method, and an ion plating method.
  • the manufacturing method of the laminated body to form.
  • An electronic device comprising the laminate according to any one of 1 to 5, further comprising a metal layer on the metal oxide layer and exhibiting ohmic characteristics between the metal oxide layer and the support layer element. 14.
  • An electronic device comprising the laminate according to any one of 14.6 to 10, further comprising a second metal layer on the metal oxide layer, wherein the second metal layer is interposed between the metal oxide layer and the first metal layer.
  • An electronic device exhibiting ohmic characteristics. 15.
  • a laminate having no contact resistance and a method for producing the laminate can be provided.
  • FIG. 4 is a cross-sectional TEM photograph of a Si / Ga 2 O 3 / Ti laminate of Comparative Example 2.
  • 4 is a diagram of IV characteristics of Example 4, Comparative Example 3 and Comparative Example 4.
  • FIG. It is a figure which shows the typical example of the voltage-current characteristic in case the contact resistance of a thin-film transistor is high. It is a figure which shows the typical example of the voltage-current characteristic at the time of suppressing the contact resistance of a thin-film transistor small.
  • the support layer, the metal oxide layer, or the support layer, the mixing layer, and the metal oxide layer are laminated in this order, and the thickness of the mixing layer is more than 0 nm. 0 nm or less.
  • the second aspect of the laminate of the present invention is the order of the support layer, the first metal layer, and the metal oxide layer, or the support layer, the first metal layer, the mixing layer, and the metal oxide layer.
  • the thickness of the mixing layer is greater than 0 nm and equal to or less than 5.0 nm.
  • the first embodiment and the second embodiment are collectively referred to as the laminate of the present invention.
  • the substrate and the metal oxide react to form a thin insulating layer (mixing layer), which may make it impossible to control electrical characteristics.
  • the laminate of the present invention does not generate a mixing layer that is generated at the initial stage of film formation, or realizes good ohmic characteristics by appropriately controlling the thickness thereof. Can do.
  • the laminated body 1 shows an example of the first aspect of the laminated body of the present invention, and includes a support layer 10, a mixing layer 20, and a metal oxide layer 30.
  • the laminated body 2 shows an example of the second aspect of the laminated body of the present invention, and includes a support layer 10, a first metal layer 15, a mixing layer 20, and a metal oxide layer 30.
  • each layer used for a laminated body is demonstrated.
  • the support layer is a substrate on which a metal oxide layer or a first metal layer is formed.
  • a wafer substrate such as Si, SiC, GaN, Al 2 O 3 , ZnO, Ga 2 O 3 , yttria stable zirconia (YSZ), strontium titanate (STO), a glass substrate, a resin substrate, or the like is used. It is done.
  • the support layer also includes an element substrate on which a transistor such as a TFT or MOSFET is mounted.
  • the support layer is preferably a Si wafer, a SiC wafer, or a GaN wafer.
  • a Si wafer substrate is preferable.
  • Conventionally known B, P, Sb and the like can be used as the dopant.
  • As or red phosphorus may be used as a dopant.
  • the thickness of the support layer is not particularly limited, and is usually 200 to 1000 ⁇ m.
  • polishing may be performed by a chemical mechanical polishing (CMP) method or the like.
  • CMP chemical mechanical polishing
  • a TAIKO type structure that leaves the outer peripheral part a structure that is back-ground with only the outer peripheral part on the back surface
  • Polishing may be performed before or after the metal oxide is laminated.
  • the material of the wafer may be a single crystal structure or a polycrystalline structure.
  • a Czochralski method, a floating zone method, or the like can be used, and a conventionally known Si substrate can be used.
  • the first metal layer is formed on the support layer in the second embodiment.
  • the first metal layer is not particularly limited as long as it has excellent conductivity, and is preferably excellent in heat stability, little structural change, and excellent adhesion.
  • the film thickness of the first metal layer is not particularly limited, but a film thickness that can exhibit a metal work function is preferably 5 to 30 nm.
  • the first metal layer examples include Mo, Ti, Pd, Pt, Cr, Al, Ag, Au, Cu, In, ITO, and IZO (registered trademark).
  • the material may be used after being flattened by using a CMP method or the like.
  • two or more kinds of metals may be laminated, or an alloy of two or more kinds of metals may be used.
  • the alloy include conventionally known alloys such as MoTa, MoW, AlNd, AgPdCu, AgCe, and CuMn.
  • Preferred metals constituting the first metal layer include Ti, Pd, Cr, In, IZO, and Mo.
  • a metal having a work function close to that of the metal oxide layer is appropriately selected as the first metal layer.
  • a metal having a work function larger than that of the metal oxide layer is appropriately selected as the first metal layer.
  • the work function of the first metal layer is measured by an atmospheric photoelectron spectrometer (for example, Riken Keiki AC-3).
  • the mixing layer may or may not exist.
  • the mixing layer is formed on the support layer or the first metal layer.
  • the thickness of the mixing layer is more than 0 nm and not more than 5.0 nm.
  • the mixing layer is preferably a mixed phase of elements constituting the metal oxide layer and the support layer, or a mixed phase of elements constituting the metal oxide layer and the first metal layer.
  • the mixing layer is formed when the metal oxide layer is deposited on the support layer or the first metal layer using a low energy deposition process.
  • the low energy film forming process include a low power sputtering method, a plasma chemical vapor deposition (PECVD) method, an organic metal CVD method, a mist CVD method, a molecular beam epitaxy (MBE) method, an ion plating method, and the like.
  • the low power sputtering method and the ion plating method can be uniformly formed on a substrate having an area of 300 cm 2 or more, which is advantageous in production.
  • the present invention can be applied to large-diameter Si wafers of 8 inches, 12 inches, 18 inches, etc., 7th generation, 8th generation, 10th generation class large LCD glass, or long-winding type resin films.
  • the low energy film formation process can suppress the implantation of the metal oxide layer into the support layer or the first metal.
  • a mixing layer composed of an element constituting the underlayer and an element constituting the metal oxide layer is generated at the interface between the underlayer and the metal oxide layer.
  • the mixing layer formed during the high energy deposition process is lower than the electrical resistance of SiO 2 but causes an increase in electrical resistance.
  • a low power process may be used only in the initial stage of film formation in a normal film formation method.
  • the power may be lowered only at the initial stage of film formation, and the sputtering power may be raised when the growth of the mixing layer is completed.
  • the sputtering power of the low power sputtering method varies depending on the shape of the apparatus used, the magnetic field strength, etc.
  • the cathode potential may be set to ⁇ 100 V to ⁇ 300 V, and high frequency (RF).
  • the power density is preferably 1.5 W / cm 2 or less.
  • the RF sputtering power density of 1.5 W / cm 2 or less is not unique because the distribution depends on the magnet strength of the sputtering apparatus, but in the case of a 4-inch ⁇ target, it corresponds to a power of approximately 100 W or less.
  • the thickness of the mixing layer is preferably more than 0 nm and not more than 4.0 nm, more preferably more than 0 nm and not more than 3.0 nm. A thinner mixing layer is preferable. When the mixing layer thickness exceeds 5.0 nm, a MIS structure is obtained, and it becomes difficult to control the ohmic junction or the Schottky junction.
  • the film thickness of the mixing layer depends on the metal oxide film forming method and the heat treatment temperature. The film thickness of the mixing layer is measured by a TEM (transmission electron microscope). Further, the constituent elements of the mixing layer can be confirmed using SIMS (Secondary Ion Mass Spectrometry) or an energy dispersive X-ray analyzer.
  • the metal oxide layer is a layer containing one or more metal oxides.
  • the thickness of the metal oxide layer is not particularly limited, but is preferably 10 nm to 10 ⁇ m, and more preferably 500 to 2000 nm.
  • the thickness of the metal oxide layer is appropriately selected depending on performance values such as the withstand voltage, on-resistance, and drive voltage of the target element.
  • the metal oxide examples include oxides containing any one or more of In, Sn, Ge, Ti, Zn, Y, Sm, Ce, Nd, Ga, and Al.
  • degenerate semiconductors such as ITO, IZO (registered trademark), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), SnO 2 , ZnO, indium aluminum oxide (IAO), IGZO (registered)
  • Non-degenerate semiconductors such as Ga 2 O 3 , In 2 O 3 , indium tin zinc oxide (ITZO), indium gallium oxide (IGO), and indium gallium aluminum oxide (IGAO) can be given.
  • the metal oxide constituting the metal oxide layer is preferably at least one selected from In 2 O 3 , ZnO, Ga 2 O 3 , SnO 2 , IAO, IGZO, ITZO, GZO, IZO and IGO.
  • the composition of the metal oxide is measured by an ICP (Inductively Coupled Plasma) emission analyzer, XRF ((X-ray Fluorescence Analysis), or SIMS (Secondary Ion Mass Spectrometry).
  • ICP Inductively Coupled Plasma
  • XRF X-ray Fluorescence Analysis
  • SIMS Secondary Ion Mass Spectrometry
  • the metal oxide may be amorphous or crystalline, and the crystal may be microcrystalline or single crystal, but the metal oxide preferably has an amorphous or microcrystalline structure.
  • “Microcrystalline structure” refers to a crystal grain size that is submicron or smaller and has no clear grain boundaries.
  • the laminated body of this invention has a 2nd metal layer (a metal layer in a 1st aspect) on a metal oxide layer.
  • the second metal layer include metals such as Ti, Al, Cr, Ni, Cu, Mo, Ag, Pt, and Au, and degenerate semiconductor oxides such as IZO and ITO.
  • the thickness of the second metal layer is not particularly limited, but is preferably 30 to 500 nm, and more preferably 50 to 300 nm.
  • the film formation method of the first metal layer and the second metal layer is not particularly limited, and examples thereof include a sputtering method, a vacuum evaporation method, an electroplating method, an electroless plating method, and various CVD methods.
  • the laminate of the present invention can be used for electronic devices, sensors and the like.
  • the electronic device of the present invention including the laminate of the present invention can be used for various electric circuits, electric devices, vehicles, and the like.
  • the electronic element include a diode, a vertical MOSFET (metal-field-effect transistor), a TFT (Thin Film Transistor), a TVS (Transient Voltage Suppressor) diode, a capacitor, and a resistor.
  • Various power supply circuits such as rectifier circuits and DC-DC converters, various control circuits, voltage shift circuits, and external interfaces, which are mounted on an integrated circuit, taking advantage of the easy film formation and easy processability of the laminate of the present invention.
  • the balance between breakdown voltage and capacity is important, but the dielectric constant and band gap are adjusted by changing the material composition using the laminate of the present invention, and the device size and film thickness are optimized. Can be achieved.
  • the varistor voltage can be controlled under a low leakage current and a low dielectric constant.
  • both the dielectric constant and the leakage current are small compared to a conventional zinc oxide system, it is optimal for the application.
  • the material is appropriately selected. At this time, by setting the film thickness of the mixing layer present at the interface between the oxide semiconductor and the metal electrode to be more than 0.0 nm and not more than 5.0 nm, the varistor voltage can be designed correctly.
  • the laminate of the present invention can be used for a rectifier circuit, a power supply circuit, a standby monitoring circuit, and the like when receiving power or a signal from an electromagnetic field of an environment such as a wireless tag or an energy harvester.
  • the rectifier diode used for these is a low-voltage Si-SBD or Ge diode, but has a large reverse leakage current, which has a problem in terms of power conversion efficiency.
  • the laminate of the present invention is used, the leak current is small because of the wide gap, and the rectifying effect can be enhanced.
  • the forward voltage can be kept low by using the tunnel effect and the like by adjusting the film thickness and energy level. This laminated body can maintain a high rectifying effect even with respect to a change in temperature.
  • the preferable film thickness of the mixing layer present at the interface between the oxide semiconductor and the metal electrode is more than 0.0 nm and not more than 5.0 nm. Furthermore, unlike non-oxide semiconductors such as Si, SiC, and GaN, an oxide semiconductor does not require an annealing process, and thus it is possible to mount a rectifier circuit on a resin substrate such as PET or PC, which has been difficult in the past. .
  • the laminate of the present invention When the laminate of the present invention is used as a cathode electrode of an OLED (Organic Light Emitting Diode), a reduction in driving voltage and an improvement in image quality can be expected. Since an oxide semiconductor that has recently attracted attention is an n-channel, a source electrode is connected to the anode side of the OLED. In the case of this connection method, a change in the driving voltage of the OLED also affects the TFT operation, which may cause luminance unevenness. Therefore, if the metal oxide layer used in the present invention is stacked on the drain electrode to form a cathode, it is possible to prevent the change in the driving voltage of the OLED from affecting the TFT operation and improve the image quality.
  • OLED Organic Light Emitting Diode
  • an electron injection level can be adjusted by sandwiching a metal oxide layer between the drain electrode and C12A7, and the driving voltage can be further lowered. At this time, it is required that there is no high resistance mixing layer at the interface between the drain electrode and the metal oxide layer.
  • sensors include optical sensors such as ultraviolet rays and radiation, gas sensors such as oxygen and nitrogen, biosensors such as ion concentrations and microorganisms, and thermal sensors that detect temperature changes. Further, it is effective to apply the laminate of the present invention to a portion where the contact resistance of the combined interface between the electrode and the oxide semiconductor needs to be kept small, such as a nonvolatile phase change memory and a solar cell.
  • the electronic device of the present invention exhibits ohmic characteristics or Schottky characteristics between the metal oxide layer and the first metal layer, or between the metal oxide layer and the support layer. Moreover, it is preferable that a non-linear electrical property is exhibited between the metal oxide layer and the second metal layer (metal layer). Non-linear electrical characteristics refer to electrical conduction that does not follow Ohm's law. As the non-linear electrical characteristics, rectification characteristics and Schottky characteristics are preferable. A non-linear electrical characteristic is exhibited between the metal oxide layer and the second metal layer, whereby a Schottky junction element can be obtained.
  • the laminated body of the present invention when used for a diode, the characteristics of high-speed switching, high breakdown voltage, and low On resistance can be realized at the mass production level.
  • the metal oxide When the metal oxide is likely to be n-type due to oxygen deficiency and difficult to be p-type, it becomes a unipolar device and is preferably used for high-speed switching.
  • the ideality factor of a diode is represented by n that is determined when a voltage-current characteristic indicating nonlinear electrical characteristics is approximated by the following expression.
  • I is a current
  • I 0 is a constant
  • q is an elementary charge
  • V is an applied voltage
  • k is a Boltzmann constant
  • T is an absolute temperature.
  • the laminated body of this invention is used for a diode, since the board
  • the stacked body of the present invention is used as a high-speed FWD (Free Wheel Diode) chip in combination with a switching element such as an insulated gate bipolar transistor (IGBT) or MOSFET, it can be designed with a wiring layout similar to the conventional one.
  • IGBT insulated gate bipolar transistor
  • MOSFET insulated gate bipolar transistor
  • the forward rising voltage can be kept low, it is also suitable for a low voltage diode used in an energy harvesting circuit.
  • Example 1 As a support, an n-type Si substrate having a resistivity of 0.02 ⁇ ⁇ cm (an n-type Si substrate having a diameter of 4 inches and manufactured by KST World Co., Ltd.) was prepared. This was installed in a sputtering apparatus CS-200 (manufactured by ULVAC), first treated in reverse sputtering mode for 15 seconds, part of the natural oxide film was etched, DC sputtering was performed on the Mo target, and 15 nm of Mo was deposited. A film was formed (first metal layer).
  • this Mo-supported substrate is set in an ion plating apparatus SIP-800 (made by Showa Vacuum) through an area mask on which a square pattern with a side of 1 mm is formed, and ion plating (IP)
  • IP ion plating
  • a 1000 nm Ga 2 O 3 film was formed by a method (metal oxide layer).
  • This Si wafer / Mo / Ga 2 O 3 laminate was again mounted on the sputtering apparatus CS-200, and Ti was deposited at a thickness of 150 nm on the Ga 2 O 3 film via an electrode area mask (secondary film). Metal layer).
  • FIG. 3 is a diagram of IV characteristics of Example 1 and Comparative Example 1.
  • Figure 4 shows a cross-sectional TEM photograph of Si / Mo / Ga 2 O 3 / Ti laminate of Example 1. As observation points, the intersections of the diagonal lines of the metal oxide layer and the field of view of a total of five points of the midpoint between the intersection and each vertex are observed, and the metal oxide layer is divided into 10 equal parts at equal intervals. The interface with the first metal layer was measured, and the average value of a total of 55 locations was taken as the film thickness of the mixing layer. As a result, the analysis limit was exceeded, and no mixing layer was observed.
  • Comparative Example 1 A Si / Mo / Ga 2 O 3 film was formed in the same manner as in Example 1 except that a sputtering apparatus CS-200 was used instead of the ion plating apparatus SIP-800 and a Ga 2 O 3 film was formed by RF sputtering. / Ti laminate was manufactured and evaluated.
  • the RF power was 300 W (3.70 W / cm 2 ) for a 4-inch target.
  • FIG. 5 shows a cross-sectional TEM photograph of Si / Mo / Ga 2 O 3 / Ti laminate of Comparative Example 1.
  • the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Example 2 A Si / Ga 2 O 3 / Ti laminate was produced and evaluated in the same manner as in Example 1 except that no Mo film was formed.
  • FIG. 6 is a diagram of IV characteristics of Example 2 and Comparative Example 2.
  • the thickness of the mixing layer was 4 nm.
  • Figure 7 shows a cross-sectional TEM photograph of Si / Ga 2 O 3 / Ti laminate of Example 2.
  • the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 2 A Si / Ga 2 O 3 / Ti laminate was produced and evaluated in the same manner as in Comparative Example 1 except that no Mo film was formed. When IV characteristics were evaluated, negative resistance was obtained. The results are shown in FIG. This is considered that the tunnel current by MIS structure was expressed. The thickness of the mixing layer was 9 nm.
  • Figure 8 shows a cross-sectional TEM photograph of Si / Ga 2 O 3 / Ti laminate of Comparative Example 2. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Example 3 A Si / Mo / Ga 2 O 3 / IZO laminate was produced in the same manner as in Example 1 except that IZO was used instead of Ti. As in Example 1, when the IV characteristics of the obtained Si / Mo / Ga 2 O 3 / IZO laminate were evaluated, the interface between the Ga 2 O 3 layer and the Mo layer was ohmic, and the Ga 2 O 3 layer and The interface of the IZO layer had rectification characteristics. A Schottky junction element was obtained. Further, when the film thickness of the mixing layer was measured in the same manner as in Example 1, it was below the analysis limit and the presence of the mixing layer was not recognized.
  • HF: H2O 1: 50
  • the laminated body having the Au / Ti / a-IGZO / In / Ni / Ti / Si structure thus obtained was evaluated using 4200-SCS, ohmic characteristics were obtained.
  • the results are shown in FIG.
  • the thickness of the mixing layer at the interface between the In layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and the result was 4 nm.
  • the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 3 The film was formed in the same manner as in Example 4 except that Mo was used instead of In and the film formation power of IGZO was 200 W (2.47 W / cm 2 ), and Au / Ti / a-IGZO / Mo / A laminate having a Ni / Ti / Si structure was obtained. When this laminate was evaluated for IV characteristics using 4200-SCS, non-ohmic characteristics were obtained. The results are shown in FIG. Further, the thickness of the mixing layer at the interface between the Mo layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and as a result, it was 8 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 4 The film was formed in the same manner as in Example 4 except that Cr was used instead of In and the film formation power of IGZO was set to 400 W (4.93 W / cm 2 ), and Au / Ti / a-IGZO / Cr / A laminate having a Ni / Ti / Si structure was obtained. When this laminate was evaluated for IV characteristics using 4200-SCS, non-ohmic characteristics were obtained. The results are shown in FIG. Further, the thickness of the mixing layer at the interface between the Cr layer and the a-IGZO layer was evaluated in the same manner as in Example 1, and as a result, it was 20 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Example 4 since the RF sputtering of IGZO was performed with a power of 1.5 W / cm 2 or less, the implantation effect on In was suppressed, the mixing layer was less than 5 nm, and ohmic characteristics were obtained.
  • Comparative Example 3 and Comparative Example 4 since RF sputtering of IGZO was performed with a high power exceeding 1.5 W / cm 2 , Mo and Cr were oxidized to form a high-resistance mixing layer, and non-ohmic characteristics and became.
  • This PET / Pd / IGO laminate was taken out again into the atmosphere, an electrode area mask was set and mounted on the sputtering apparatus CS-200, and 50 nm of Ti and Au were deposited in this order on the IGO film ( Second metal layer).
  • the first metal layer Pd and the metal oxide layer IGO Diode characteristics were obtained in which the interface was an ohmic junction and the interface between the metal oxide layer IGO and the second metal layer Ti was a Schottky junction.
  • the ideality factor n of the diode was evaluated to be 4.7. Moreover, it was 3 nm as a result of evaluating the thickness of the mixing layer of the interface of 1st metal layer Pd and metal oxide layer IGO like Example 1.
  • FIG. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Comparative Example 5 A Schottky with a PET / Pd / IGO / Ti / Au configuration was used in the same manner as in Example 5 except that the RF power when the metal oxide layer was formed by sputtering was 300 W (3.70 W / cm 2 ). A barrier diode was obtained. As for the obtained diode characteristics, it was confirmed that the interface between the first metal layer Pd and the metal oxide layer IGO was a Schottky junction as in Example 5, but the diode ideality factor n was 15. As a result of evaluating the thickness of the mixing layer at the interface between the first metal layer Pd and the metal oxide layer IGO in the same manner as in Example 1, it was 7 nm. As a result of confirmation by an energy dispersive X-ray analyzer, the mixing layer was a mixed layer of an element constituting the oxide layer and an element constituting the first metal layer.
  • Table 1 shows the evaluation results of Examples 1 and 3-5 and Comparative Examples 1 and 3-5 in which a laminate having a metal layer (first metal layer) between the support and the metal oxide layer was produced and evaluated. Show.
  • Table 2 shows the evaluation results of Example 2 and Comparative Example 2 in which a laminate having no metal layer between the support and the metal oxide layer was produced and evaluated.
  • the laminate of the present invention can be used for electronic devices and the like.
  • the electronic device of the present invention can be used for electric circuits, electric devices, and vehicles.

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Abstract

La présente invention concerne un produit constitué de couches qui comprend une couche de support et une couche d'oxyde métallique superposées dans cet ordre ou qui comprend une couche de support, une couche de mélange, et une couche d'oxyde métallique superposées dans cet ordre, ladite couche de mélange ayant une épaisseur de film supérieure à 0 nm mais ne dépassant pas 5,0 nm.
PCT/JP2016/000345 2015-02-18 2016-01-25 Produit constitué de couches et procédé de fabrication d'un produit constitué de couches WO2016132681A1 (fr)

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CN110993505A (zh) * 2019-10-14 2020-04-10 西安电子科技大学 基于碳化硅衬底的半导体结构制备方法及半导体结构
WO2021090790A1 (fr) * 2019-11-08 2021-05-14 出光興産株式会社 Stratifié et dispositif semi-conducteur
KR20220076010A (ko) * 2020-11-30 2022-06-08 서울대학교산학협력단 알파-산화알루미늄갈륨을 활용한 알파-산화갈륨 박막의 제조방법

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CN110993505B (zh) * 2019-10-14 2023-08-04 西安电子科技大学 基于碳化硅衬底的半导体结构制备方法及半导体结构
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