CN110993505A - Semiconductor structure preparation method based on silicon carbide substrate and semiconductor structure - Google Patents

Semiconductor structure preparation method based on silicon carbide substrate and semiconductor structure Download PDF

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CN110993505A
CN110993505A CN201910975090.9A CN201910975090A CN110993505A CN 110993505 A CN110993505 A CN 110993505A CN 201910975090 A CN201910975090 A CN 201910975090A CN 110993505 A CN110993505 A CN 110993505A
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silicon carbide
carbide substrate
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semiconductor structure
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CN110993505B (en
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贾仁需
于淼
余建刚
王卓
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Xidian University
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    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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Abstract

The invention discloses a preparation method of a semiconductor structure based on a silicon carbide substrate, which comprises the following steps: selecting a silicon carbide substrate layer; preparing (In) on the surface of the silicon carbide substrate layerxGa1‑x)2O3A buffer layer; in the (In)xGa1‑x)2O3Preparation of Ga on the surface of buffer layer2O3A thin film layer. The preparation method of the semiconductor structure based on the silicon carbide substrate provided by the invention firstly forms (In) on the surface of the silicon carbide substrate layerxGa1‑x)2O3Buffer layer to reduce dislocation defect caused by lattice mismatch, and then (In)xGa1‑x)2O3Ga is formed on the surface of the buffer layer2O3Film layer, thereby increasingGa grown subsequently2O3The crystallinity of the thin film layer finally realizes the preparation of high-crystalline Ga on the silicon carbide substrate layer2O3The structure of the film material.

Description

Semiconductor structure preparation method based on silicon carbide substrate and semiconductor structure
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a silicon carbide epitaxial gallium oxide film method and a silicon carbide epitaxial gallium oxide film structure.
Background
In recent years, Ga as a third generation semiconductor2O3The material has a large forbidden band width, a high breakdown electric field strength and a small on-resistance, so that the material is widely concerned by people and is the best material for developing power devices. Ga can be prepared by a method of high temperature or the like at present2O3And Ga having excellent optical properties and electrical properties which can be homoepitaxially grown thereon2O3The thin film can be used as a power electronic device, an ultraviolet photoelectric detector and an ultraviolet sensor with high performance, and has wide application prospect, however, the application of the power electronic device at high temperature is limited due to the lower thermal conductivity of the thin film.
SiC has excellent performance as the third-generation semiconductor material and has higher thermal conductivity, SiC and Ga2O3Not only can exert their respective advantages, but also can solve the problem of low thermal conductivity of gallium oxide, however, SiC and Ga2O3The existence of many defects due to large lattice mismatch limits its wide application.
Thus, SiC and Ga are solved2O3Growing gallium oxide film with high crystallization quality on the silicon carbide substrate due to defect problem caused by lattice mismatch, for future SiC and Ga2O3The combination of materials has great significance in the application of power electronic devices in high-temperature environments.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a method for extending a gallium oxide film by silicon carbide and a gallium oxide film structure by silicon carbide extension. The technical problem to be solved by the invention is realized by the following technical scheme:
a preparation method of a semiconductor structure based on a silicon carbide substrate comprises the following steps:
selecting a silicon carbide substrate layer;
preparing (In) on the surface of the silicon carbide substrate layerxGa1-x)2O3A buffer layer;
in the (In)xGa1-x)2O3Preparation of Ga on the surface of buffer layer2O3A thin film layer.
In one embodiment of the invention, the thickness of the silicon carbide substrate layer is 300-700 μm.
In one embodiment of the present invention, an (In) layer is prepared on the surface of the silicon carbide substrate layerxGa1-x)2O3A buffer layer, comprising:
sputtering Ga on the surface of the silicon carbide substrate layer by utilizing a magnetron sputtering process in an oxygen and argon environment2O3Target material and In2O3Target formation (In)xGa1-x)2O3A layer of material;
subjecting the (In) to an annealing processxGa1-x)2O3Annealing the material layer to form the (In)xGa1-x)2O3A buffer layer.
In one embodiment of the present invention, the (In)xGa1-x)2O3The value range of x in the buffer layer is 0.58-0.76.
In one embodiment of the present invention, a magnetron sputtering process is used to sputter Ga on the surface of the silicon carbide substrate layer2O3Target material and In2O3Target formation (In)xGa1-x)2O3A layer of material comprising:
under vacuum degree of 5X 10-4~7×10-4Sputtering Ga on the surface of the silicon carbide substrate layer by utilizing a magnetron sputtering process under the condition of Pa2O3Target material and In2O3Target formation (In)xGa1-x)2O3A material layer, wherein the Ga is sputtered2O3The sputtering power of the target is 60W, and the In is sputtered2O3Target materialThe sputtering power of (A) is 60W-80W.
In one embodiment of the present invention, the (In) is annealedxGa1-x)2O3The material layer is annealed to form (In)xGa1-x)2O3A buffer layer, comprising:
sequentially subjecting the (In) to oxygen, vacuum and nitrogen environmentsxGa1-x)2O3Annealing the material layer to form the (In)xGa1-x)2O3A buffer layer.
In one embodiment of the present invention, the (In)xGa1-x)2O3The thickness of the buffer layer is 100 +/-5 nm.
In one embodiment of the present invention, In (In) isxGa1-x)2O3Preparation of Ga on the surface of buffer layer2O3A film layer, comprising:
under the argon atmosphere, the (In) is treated by utilizing a magnetron sputtering processxGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3A thin film layer.
In one embodiment of the present invention, a magnetron sputtering process is used to form (In) InxGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3A film layer, comprising:
under vacuum degree of 5X 10-4~7×10-4Pa, using magnetron sputtering technology to process the (In)xGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3And the sputtering target material base distance is 5cm, and the working current is 2A.
An embodiment of the present invention further provides a semiconductor structure prepared by the method for preparing a semiconductor structure based on a silicon carbide substrate according to any one of the embodiments, wherein the semiconductor structure includes:
a silicon carbide substrate layer;
(InxGa1-x)2O3the buffer layer is positioned on the surface of the silicon carbide substrate layer;
Ga2O3a thin film layer located at the (In)xGa1-x)2O3On the surface of the buffer layer.
The invention has the beneficial effects that:
the preparation method of the semiconductor structure based on the silicon carbide substrate provided by the invention firstly forms (In) on the surface of the silicon carbide substrate layerxGa1-x)2O3Buffer layer to reduce dislocation defect caused by lattice mismatch, and then (In)xGa1-x)2O3Ga is formed on the surface of the buffer layer2O3Thin film layer to improve subsequent Ga growth2O3The crystallinity of the thin film layer finally realizes the preparation of high-crystalline Ga on the silicon carbide substrate layer2O3The structure of the film material.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic structural diagram of an apparatus for preparing a GaN epitaxial silicon carbide film according to an embodiment of the invention;
FIG. 2 is a schematic flow chart of a method for fabricating a semiconductor structure based on a silicon carbide substrate according to an embodiment of the present invention;
FIGS. 3 a-3 c are schematic diagrams of a method for fabricating a semiconductor structure based on a silicon carbide substrate according to an embodiment of the present invention;
FIG. 4 shows an In (I) diagram according to an embodiment of the present inventionxGa1-x)2O3Buffer layer annealing environment schematic diagram;
fig. 5 is a schematic diagram of a semiconductor structure according to an embodiment of the invention.
Description of reference numerals:
a silicon carbide substrate layer-1; (In)xGa1-x)2O3A buffer layer-2; ga2O3Film layer-3; a radio frequency power supply-4; a target material container-5; a target baffle-6; an air inlet-7; an air exhaust pipeline-8; a substrate baffle-9; a tray-10; the substrate is heated by the heating disc-11; a rotary machine-12; sputtering chamber-13.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Before describing the method for manufacturing a semiconductor structure based on a silicon carbide substrate provided in this embodiment, this embodiment first provides an apparatus for manufacturing a gallium oxide epitaxial film of silicon carbide, please refer to fig. 1, where fig. 1 is a schematic structural diagram of an apparatus for manufacturing a gallium oxide epitaxial film of silicon carbide provided in this embodiment of the present invention, and the apparatus includes a radio frequency power source 4, two target containers 5, two target baffles 6, a gas inlet 7, a gas exhaust duct 8, a substrate baffle 9, a tray 10, a substrate heating plate 11, a rotator 12, and a sputtering chamber 13. A radio frequency power supply 4 is connected to the target material container 5 through the sputtering chamber 13 for providing a power supply for the sputtering target material. The target container 5 is used for placing sputtering target materials, and the two target material baffle plates 6 are respectively arranged above the two target material containers 5. The gas inlet 7 can be provided with a plurality of gas pipelines respectively filled with different gases, and in the embodiment, the gas inlet 7 can be filled with sputtering gas oxygen and argon gas at the same time. The evacuation line 8 is connected to a vacuum system for evacuating the sputtering chamber 13. The lower end of the rotating machine 12 is sequentially connected with the substrate heating plate 11 and the tray 10, so that the substrate heating plate 11 and the tray 10 can rotate simultaneously, and the uniformity of a deposited film on the surface of the substrate in the sputtering process is guaranteed.
The method for manufacturing a semiconductor structure based on a silicon carbide substrate according to an embodiment of the present invention may be manufactured based on the above apparatus, and may also be manufactured based on other apparatuses, which is not specifically limited in this embodiment.
In order to better describe the method for preparing a semiconductor structure based on a silicon carbide substrate provided in this embodiment, the present embodiment describes a method for preparing a semiconductor structure based on a silicon carbide substrate on the basis of the above apparatus for preparing a gallium oxide epitaxial film of silicon carbide, please refer to fig. 2, where fig. 2 is a schematic flow chart of the method for preparing a semiconductor structure based on a silicon carbide substrate provided in the embodiment of the present invention, and the method for preparing a semiconductor structure based on a silicon carbide substrate specifically includes the following steps:
s1, please refer to fig. 3a, selecting a silicon carbide substrate layer 1;
specifically, the production technology of the silicon carbide substrate layer is mature, and the quality of the prepared device is good; in addition, the silicon carbide has high thermal conductivity and good stability, and can be applied to the high-temperature growth process; finally, silicon carbide has excellent physicochemical properties, and the combination with gallium oxide enables high-power electronic devices with high performance. Therefore, the substrate layer of the present embodiment is made of silicon carbide.
Further, the thickness of the silicon carbide substrate layer is 300-700 mu m, and preferably the thickness of the silicon carbide substrate layer is 500 mu m.
S2, please refer to FIG. 3b, prepared on the surface of the silicon carbide substrate layer 1 (In)xGa1-x)2O3 A buffer layer 2;
s21, sputtering Ga on the surface of the silicon carbide substrate layer by utilizing a magnetron sputtering process in an oxygen and argon environment2O3Target material and In2O3Target formation (In)xGa1-x)2O3The material layer, wherein the magnetron sputtering process utilizes the interaction of a magnetic field and an electric field to enable electrons to run spirally near the surface of the target, so that the probability that the electrons collide with argon gas to generate ions is increased, and the generated ions collide with the target surface under the action of the electric field so as to sputter out the target material. Since the radius of In atoms is smaller than that of Ga atoms, In is doped into Ga2O3In (In)xGa1-x)2O3Resulting In a decrease of the lattice constant, (In) In the case of an appropriate value of xxGa1-x)2O3With SiC and (In)xGa1-x)2O3And Ga2O3Has smaller lattice constant mismatching degreeThis can reduce the defect density caused by dislocations.
Specifically, firstly, oxygen and argon are used as sputtering gases and are simultaneously introduced into a sputtering cavity; then utilizing magnetron sputtering technology to simultaneously sputter Ga on the surface of the silicon carbide substrate layer2O3Target material and In2O3A target material to form (In) on the surface of the silicon carbide substrate layerxGa1-x)2O3A layer of material.
Preferably, (In)xGa1-x)2O3The value range of x in the material layer is 0.58-0.76. When the value range of x is 0.58-0.76, (In) can be ensuredxGa1-x)2O3With SiC and (In)xGa1-x)2O3And Ga2O3The mismatching degree of the lattice constant between the two is small, so that the defect density caused by dislocation can be reduced. If the value of X is too small, the effect of reducing the lattice constant is not achieved, but if the value of X is too large, phase transformation occurs due to limited saturation of the alloy compound, and the effect of reducing the lattice constant and reducing dislocation is not achieved.
Further, the purity of oxygen and argon in percentage by mass is 99.999%, and the flow rate of oxygen can be 2cm3A/second; the flow rate of argon gas may be 20cm3Second while Ga2O3Target material and In2O3The mass ratio purity of the target material is more than 99.99 percent.
In addition, this example is In preparation (In)xGa1-x)2O3The conditions of the magnetron sputtering process provided by the buffer layer comprise: substrate temperature (i.e., substrate layer heating temperature), degree of vacuum, Ga2O3Sputtering power of target material, In2O3Sputtering power of the target, sputtering target base distance and sputtering duration. Wherein the sputtering target base distance refers to the distance between the sputtering target and the silicon carbide substrate layer. The substrate temperature was room temperature. This example is to prepare (In)xGa1-x)2O3The magnetron sputtering process conditions for the buffer layer are preferably: the substrate temperature is 25 ℃; vacuum degree of 5X 10-4~7×10-4Pa, preferably 5.0X 10-4Pa;Ga2O3The sputtering power of the target is 60W; in2O3The sputtering power of the target is 60-80W; the sputtering target base distance is 5 cm; the sputtering time was 1 hour. In this embodiment, since (In) of a proper lattice constant is to be grownxGa1-x)2O3The crystal lattice constant of the SiC substrate can be similar to that of the SiC substrate, the range of x determines the change of the size of the crystal lattice constant, the value range of x is determined by experimental growth conditions, and the proper crystal lattice constant (In) can be grown only under the conditions through a large number of experimentsxGa1-x)2O3That is, the value of x can be set to 0.58-0.76 only under the above conditions.
This embodiment is implemented by setting different In2O3The sputtering power of the target can obtain (In) with different In compositionsxGa1-x)2O3A material. When In2O3(In) generated when the sputtering power of the target is adjusted within a range of 60W to 80WxGa1-x)2O3The value range of x in the material is 0.18-0.26. For example, when In2O3When the sputtering power of the target is 65W, x is 0.21; when In2O3When the sputtering power of the target is 70W, x is 0.24; when In2O3When the target sputtering power was 80W, x was 0.26.
S22, annealing process pair (In)xGa1-x)2O3The material layer is annealed to form (In)xGa1-x)2O3A buffer layer.
Specifically, referring to fig. 4, the (In) is sequentially aligned In an oxygen, vacuum and nitrogen atmospherexGa1-x)2O3The material layer is annealed to (In)xGa1-x)2O3The material layer becomes (In)xGa1-x)2O3Buffer layer of (In)xGa1-x)2O3The buffer layer has amorphous and nanocrystalline structureIs characterized in that. Annealing first under oxygen mainly for the purpose of reduction (In)xGa1-x)2O3Concentration of oxygen vacancies In the film and then annealing In vacuum mainly for increasing (In)xGa1-x)2O3The final annealing In nitrogen is mainly to improve (In)xGa1-x)2O3The conductivity of (1).
Further, the temperature of the annealing treatment in the embodiment is 600 ± 5 ℃, preferably 600 ℃, the annealing time in oxygen is 2 hours, the annealing time in vacuum is 1 hour, the annealing time in nitrogen is 2 hours, and when the annealing time is short, the film cannot fully react and is not beneficial to recrystallization; when the time is longer, the internal stress of the film is larger, so that the film is broken, and therefore, the proper annealing time is required.
Preferably, (In)xGa1-x)2O3The thickness of the buffer layer is 100 +/-5 nm. (In)xGa1-x)2O3If the thickness of the buffer layer is too small, Ga tends to be adversely affected due to large crystal grains2O3Growth of thin film layers, and if too thick, SiC/Ga is affected2O3Performance of heterojunction devices.
S3, please see 3c, In (In)xGa1-x)2O3Preparation of Ga on the surface of buffer layer 22O3A thin film layer 3;
specifically, under the argon environment, the (In) is processed by utilizing a magnetron sputtering processxGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3A thin film layer.
Further, argon gas is first introduced into the sputtering chamber as a sputtering gas, wherein the argon gas has a purity of 99.999% by mass and a flow rate of 20cm, for example3A/second; then utilizing magnetron sputtering process to (In)xGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3A thin film layer.
Preferably, the first and second electrodes are formed of a metal,Ga2O3the mass specific purity of the target material is more than 99.99 percent.
In addition, this example was carried out to prepare Ga2O3The conditions of the magnetron sputtering process provided by the film layer comprise: vacuum degree, sputtering target base distance and working current. This example is in the preparation of Ga2O3The magnetron sputtering process conditions for the thin film layer are preferably as follows: vacuum degree of 5X 10-4~7×10-4Pa, preferably 5.0X 10-4Pa, the sputtering target base distance is 5cm, and the working current is 2A. If the vacuum degree is lower, more impurity gas in the chamber can pollute the prepared Ga2O3And when the vacuum degree is higher, the required time is increased, which is not beneficial to the experiment.
Preferably, Ga2O3The thickness of the thin film layer is 220 +/-5 nm. Ga2O3Too thick a film thickness will result in SiC/Ga2O3The performance of the heterojunction device is affected.
The method for preparing the silicon carbide epitaxial gallium oxide film provided by the embodiment of the invention is to prepare the material (In) on the silicon carbide substrate layerxGa1-x)2O3The buffer layer can reduce the defects caused by lattice mismatch between the buffer layer and the silicon carbide substrate layer after annealing treatment is sequentially carried out in oxygen, vacuum and nitrogen environments, thereby being more beneficial to preparing Ga with high crystallization quality at proper temperature2O3A thin film layer.
Example two
Referring to fig. 5, fig. 5 is a schematic view of a semiconductor structure according to an embodiment of the invention. An embodiment of the present invention provides a semiconductor structure, including: silicon carbide substrate layer 1, (In)xGa1-x)2O3Buffer layer 2 and Ga2O3A thin film layer 3 of (In)xGa1-x)2O3A buffer layer 2 is arranged on the surface of the silicon carbide substrate layer 1, Ga2O3The thin film layer 3 is located at (In)xGa1-x)2O3Buffer layer2 on the surface.
The semiconductor structure of this embodiment is prepared by using the method for preparing a semiconductor structure based on a silicon carbide substrate provided in the above embodiments, and the implementation principle and technical effect are similar, and no further description is given here
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", and the like, indicate orientations and positional relationships based on those shown in the drawings, and are used only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples described in this specification can be combined and combined by those skilled in the art.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (10)

1. A method for preparing a semiconductor structure based on a silicon carbide substrate is characterized by comprising the following steps:
selecting a silicon carbide substrate layer;
preparing (In) on the surface of the silicon carbide substrate layerxGa1-x)2O3A buffer layer;
in the (In)xGa1-x)2O3Preparation of Ga on the surface of buffer layer2O3A thin film layer.
2. The method of claim 1, wherein the silicon carbide substrate layer has a thickness of 300 μm to 700 μm.
3. The method for preparing a semiconductor structure based on a silicon carbide substrate according to claim 1, wherein (In) is prepared on a surface of the silicon carbide substrate layerxGa1-x)2O3A buffer layer, comprising:
sputtering Ga on the surface of the silicon carbide substrate layer by utilizing a magnetron sputtering process in an oxygen and argon environment2O3Target material and In2O3Target formation (In)xGa1-x)2O3A layer of material;
subjecting the (In) to an annealing processxGa1-x)2O3Annealing the material layer to form the (In)xGa1-x)2O3A buffer layer.
4. The method for preparing a semiconductor structure based on a silicon carbide substrate according to claim 3, wherein the (In) isxGa1-x)2O3The value range of x in the buffer layer is 0.58-0.76.
5. The method of claim 4, wherein the magnetron sputtering process is used to fabricate the silicon carbide substrate-based semiconductor structureSputtering Ga on the surface of the silicon carbide substrate layer2O3Target material and In2O3Target formation (In)xGa1-x)2O3A layer of material comprising:
under vacuum degree of 5X 10-4~7×10-4Sputtering Ga on the surface of the silicon carbide substrate layer by utilizing a magnetron sputtering process under the condition of Pa2O3Target material and In2O3Target formation (In)xGa1-x)2O3A material layer, wherein the Ga is sputtered2O3The sputtering power of the target is 60W, and the In is sputtered2O3The sputtering power of the target is 60W-80W.
6. The method of claim 4, wherein said annealing process is used to anneal said (In) to said silicon carbide substratexGa1-x)2O3The material layer is annealed to form (In)xGa1-x)2O3A buffer layer, comprising:
sequentially subjecting the (In) to oxygen, vacuum and nitrogen environmentsxGa1-x)2O3Annealing the material layer to form the (In)xGa1-x)2O3A buffer layer.
7. The method for preparing a semiconductor structure based on a silicon carbide substrate according to claim 4, wherein the (In) isxGa1-x)2O3The thickness of the buffer layer is 100 +/-5 nm.
8. The method of claim 1, wherein the (In) is performed In a wafer processing chamberxGa1-x)2O3Preparation of Ga on the surface of buffer layer2O3A film layer, comprising:
under the argon atmosphere, the (In) is treated by utilizing a magnetron sputtering processxGa1-x)2O3BufferSputtering Ga on the surface of a layer2O3Target material generation of Ga2O3A thin film layer.
9. The method of claim 8, wherein the (In) is formed by magnetron sputteringxGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3A film layer, comprising:
under vacuum degree of 5X 10-4~7×10-4Pa, using magnetron sputtering technology to process the (In)xGa1-x)2O3Sputtering Ga on the surface of the buffer layer2O3Target material generation of Ga2O3And the sputtering target material base distance is 5cm, and the working current is 2A.
10. A semiconductor structure prepared by the method for preparing a semiconductor structure based on a silicon carbide substrate according to any one of claims 1 to 9, wherein the semiconductor structure comprises:
a silicon carbide substrate layer;
(InxGa1-x)2O3the buffer layer is positioned on the surface of the silicon carbide substrate layer;
Ga2O3a thin film layer located at the (In)xGa1-x)2O3On the surface of the buffer layer.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115094398A (en) * 2022-05-14 2022-09-23 东北师范大学 (In) x Ga 1-x ) 2 O 3 Preparation method and application of wide bandgap semiconductor material

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102668028A (en) * 2009-11-28 2012-09-12 株式会社半导体能源研究所 Stacked oxide material, semiconductor device, and method for manufacturing the semiconductor device
JP2014072463A (en) * 2012-09-28 2014-04-21 Roca Kk Semiconductor device and crystal
CN105742398A (en) * 2016-03-18 2016-07-06 浙江理工大学 Visible-blind ultraviolet detector based on Beta-Ga2O3/SiC heterojunction thin film and fabrication method of visible-blind ultraviolet detector
WO2016132681A1 (en) * 2015-02-18 2016-08-25 出光興産株式会社 Layered product and process for producing layered product

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102668028A (en) * 2009-11-28 2012-09-12 株式会社半导体能源研究所 Stacked oxide material, semiconductor device, and method for manufacturing the semiconductor device
JP2014072463A (en) * 2012-09-28 2014-04-21 Roca Kk Semiconductor device and crystal
CN104205296A (en) * 2012-09-28 2014-12-10 株式会社Flosfia Semiconductor device or crystal
WO2016132681A1 (en) * 2015-02-18 2016-08-25 出光興産株式会社 Layered product and process for producing layered product
TW201638363A (en) * 2015-02-18 2016-11-01 Idemitsu Kosan Co Layered product and process for producing layered product
CN105742398A (en) * 2016-03-18 2016-07-06 浙江理工大学 Visible-blind ultraviolet detector based on Beta-Ga2O3/SiC heterojunction thin film and fabrication method of visible-blind ultraviolet detector

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
RIENA JINNO ET AL: "Control of Crystal Structure of Ga2O3 on Sapphire Substrate by Introduction of α-(AlxGa1 x)2O3 Buffer Layer", 《PHYSICAL. STATUS SOLIDI B》 *
杨妮: "氧化镓薄膜的择优取向制备及其应用研究", 《中国优秀硕士学位论文全文数据库 (工程科技Ⅰ辑)》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115094398A (en) * 2022-05-14 2022-09-23 东北师范大学 (In) x Ga 1-x ) 2 O 3 Preparation method and application of wide bandgap semiconductor material

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