WO2017071658A1 - Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel - Google Patents

Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel Download PDF

Info

Publication number
WO2017071658A1
WO2017071658A1 PCT/CN2016/103831 CN2016103831W WO2017071658A1 WO 2017071658 A1 WO2017071658 A1 WO 2017071658A1 CN 2016103831 W CN2016103831 W CN 2016103831W WO 2017071658 A1 WO2017071658 A1 WO 2017071658A1
Authority
WO
WIPO (PCT)
Prior art keywords
channel region
layer
thin film
region
film transistor
Prior art date
Application number
PCT/CN2016/103831
Other languages
French (fr)
Chinese (zh)
Inventor
陆磊
王文
郭海成
Original Assignee
陆磊
王文
郭海成
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 陆磊, 王文, 郭海成 filed Critical 陆磊
Publication of WO2017071658A1 publication Critical patent/WO2017071658A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8236—Combination of enhancement and depletion transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to a circuit structure and a manufacturing method composed of a metal oxide thin film transistor, particularly a circuit used in a module of a display panel.
  • the performance of a thin film transistor directly affects the performance of the display.
  • thin film transistors composed of metal oxide active layers have many advantages, such as low temperature process, high transparency, high mobility, low leakage, etc., which are considered to be silicon-based devices in display panels. The most promising replacement.
  • conventional metal oxide thin film transistors have significant deficiencies in manufacturing processes, device structures, and circuit applications.
  • a conventional metal oxide thin film transistor is used as an electrode by depositing a metal on an active layer.
  • a Schottky barrier is usually formed at the contact interface between the electrode and the active layer, resulting in a high contact resistance between the oxide and the metal interface, and the eigenstate metal oxide semiconductor is usually high resistivity, which is carried
  • the problem of high source-drain parasitic resistance is to reduce the resistivity of the source and drain regions by making the source and drain regions cumbersome, but this is usually at the expense of process stability and increased manufacturing costs.
  • the source and drain regions can be mischarged into the source and drain regions by plasma treatment, but the effects are not stable.
  • Other filths, such as boron and phosphorus require extremely expensive ion implantation equipment and additional activation processes. For this reason, there is an urgent need in the thin film transistor manufacturing industry for a low cost, simple manufacturing process to reduce the resistivity of the metal oxide source and drain regions, thereby improving device performance.
  • the back channel etch structure and the etch barrier structure are two main structures of the back gate metal oxide thin film transistor.
  • the exposed interface on the channel is damaged at the time of etching the electrode, thereby affecting the performance of the device.
  • the etch barrier device structure needs to be extended. The length of the channel and the length of the gate electrode, which enlarges the area of the thin film transistor, thereby greatly limiting the display
  • the further increase in resolution deviates from the high resolution trend of the display.
  • the advantages of the back-channel etched device structure are that it provides a simple process, lower fabrication cost, and smaller device size, while the device structure of the etch barrier provides better device performance and Improved device stability, but increases the area of the device and increases manufacturing costs. For this reason, the metal oxide thin film transistor manufacturing industry urgently needs a novel thin film transistor structure, which can meet the multiple requirements of low cost, high performance, small size, and the like.
  • metal oxide thin film transistors also have a significant defect density compared to conventional silicon-based thin film transistors. Although the performance of metal oxide thin film transistors has been significantly improved over the years, the thin film transistor process and structure of the present invention can be further improved. However, current mainstream metal oxide thin film transistors are also n-type thin film transistors, and p-type metal oxide thin film transistors with excellent performance are still difficult to implement. Further improvements in power consumption and other performance parameters of the circuit can no longer rely solely on the performance improvement of the thin film transistor itself, but also require an active "pull-up" device.
  • this active "pull-up” device is a p-type thin film transistor, but for metal oxide thin film transistors the situation is completely different. Since circuits composed of metal oxide thin film transistors can only be based on n-type devices, it is difficult to prepare high-performance circuits in a complementary manner to n-type and p-type thin film transistors like silicon-based devices. In order to achieve a relatively good performance circuit, a widely used alternative is to use a depletion type n-type metal oxide thin film transistor as an active "pull-up" device, and an enhanced n-type thin film transistor as an active "pull-down". Device. Wherein, the threshold voltage of the depletion thin film transistor is lower than the threshold voltage of the enhancement type thin film transistor.
  • the method for realizing the monolithic integration of the depletion mode and the enhancement type thin film transistor mainly includes: adjusting the material composition of the metal oxide active layer, adjusting the thickness of the active layer, using an active layer of a multilayer structure, or the like.
  • the above method is very limited in adjusting the threshold voltage of the thin film transistor, and the process is complicated, and the device performance is severely limited by the preparation process.
  • Another way to adjust the threshold voltage to form depletion mode and enhancement thin film transistors is by introducing an additional gate stack to form a double gate structure.
  • the additional gate stack is specifically responsible for adjusting the threshold voltage of the thin film transistor, so the adjustment range is larger.
  • this additional gate stack requires additional control circuitry, which greatly increases the complexity and cost of the fabrication circuitry, and is not compatible with existing device architectures, deviating from the current high resolution trends in display panels.
  • display panel manufacturing urgently needs a new The method of adjusting the threshold voltage of the metal oxide thin film transistor can increase the modulation range of the threshold voltage of the device under the premise of ensuring the high performance index of the thin film transistor, and maintain the simple and easy-to-cost manufacturing process.
  • the technical problem to be solved by the present invention is to overcome the above-mentioned deficiencies of the prior art, and provide a circuit structure for effectively adjusting a threshold voltage of a metal oxide thin film transistor, an integrated enhancement thin film transistor and a depletion thin film transistor, Increasing the modulation range of the threshold voltage of the thin film transistor also maintains the high performance of the thin film transistor, simplifies the existing manufacturing process, and reduces the manufacturing cost, and can be effectively applied to an integrated circuit, particularly a circuit in a display panel. .
  • the present invention provides a thin film transistor circuit structure, the structure of the thin film transistor includes: a substrate and an active layer made of a metal oxide on the substrate; the active layer and the gate a portion of the active layer is covered with a first conditioning layer, the first conditioning layer having a thickness greater than a diffusion length of the oxygen-containing material in the first conditioning layer; Forming a source region and a drain region in a region covered by the first adjustment layer, and forming a channel region in a region not covered by the first adjustment layer; the source region, the drain region, and the The channel regions are connected to each other and are respectively located at two ends of the channel region, the channel region is adjacent to the gate stack; the source region, the drain region and the channel region
  • the connection surface is self-aligned with a vertical surface of a boundary of the first adjustment layer within a projected area of the active layer; the resistivity of the source region and the drain region is smaller than a resistivity of the channel region a second adjustment layer is disposed over the entire channel region of the partial thin film
  • a depletion mode channel region under the cover of the second adjustment layer Forming a depletion mode channel region under the cover of the second adjustment layer, forming an enhancement channel region under the cover of the second adjustment layer, the depletion mode channel region having a resistivity less than a resistivity of the enhanced channel region; a thickness of the second conditioning layer being greater than a diffusion length of the oxygen-containing material in the second conditioning layer; and a thin film transistor having the depletion channel region
  • a depletion thin film transistor, the thin film transistor having the enhanced channel region is an enhancement thin film transistor; and the depletion thin film transistor and the enhancement thin film transistor are electrically connected to each other to constitute a circuit.
  • a preferred method as the above circuit structure [0010] a distance between a connection surface of the source region, the drain region and the channel region, and a vertical plane of a boundary of the first adjustment layer within a projected area of the active layer is smaller than the 100 times the thickness of the source layer.
  • a ratio of resistivity of the channel region to the source region and the drain region is greater than 1000 times; a resistivity of the enhanced channel region is 2 of a resistivity of the depletion channel region Up to 100 times.
  • the active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide
  • the thickness of the first adjustment layer is between 2 and 100 times the diffusion length of the oxygen-containing substance in the first adjustment layer
  • the thickness of the second adjustment layer is the The substance of the oxygen element is between 2 and 100 times the diffusion length in the second conditioning layer.
  • the first conditioning layer and the second conditioning layer comprise a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, silicon, gallium arsenide, titanium , molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy; wherein, the nitridation in the silicon oxynitride The silicon ratio is greater than 20%.
  • the first conditioning layer has a thickness of 10 to 3000 nm
  • the second conditioning layer has a thickness of 10 to 3000 nm.
  • the gate stack may be disposed between the active layer and the substrate;
  • the active layer is disposed between the gate stack and the substrate.
  • the gate stack includes a gate electrode and a gate insulating layer, the gate electrode has a thickness smaller than a diffusion length of the oxygen-containing material in the gate electrode, and the gate insulating layer The thickness of the layer is less than the diffusion length of the oxygen-containing material in the gate insulating layer.
  • the gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or indium zinc oxide; the gate insulating layer comprises one of the following materials Or a combination of a plurality of: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm.
  • the oxygen element-containing substance includes: plasma of oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and the like.
  • the present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the circuit structure described above.
  • the present invention further provides another display panel, including a plurality of sets of display modules, the display module includes: a thin film transistor, an intermediate insulating layer, and a pixel electrode; the thin film transistor is electrically connected to the pixel electrode, The intermediate insulating layer is located between the thin film transistor and the pixel electrode, the projected area of the second adjusting layer and the projected area of the intermediate insulating layer completely overlap, and the thin film transistors are electrically connected to each other to form a pixel circuit and display
  • the driving circuit, the structure of the pixel circuit and the display driving circuit include the circuit structure described above.
  • the present invention further provides a display panel, comprising a plurality of sets of display modules, wherein the display module includes
  • the thin film transistor is electrically connected to the pixel electrode, the thin film transistors are electrically connected to each other to form a pixel circuit and a display driving circuit, and the structure of the pixel circuit and the display driving circuit includes the above The circuit structure described.
  • the present invention also provides a method for fabricating a thin film transistor circuit, comprising:
  • an active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
  • a first annealing process forms a channel region, the channel region is adjacent to the gate stack, the source region, the drain region and the channel region are connected to each other, and are respectively located in the channel region
  • the connecting surface formed by the first annealing process between the source region, the drain region and the channel region is self-aligned with the projected area of the active layer in the active layer a vertical plane of a boundary within the boundary, wherein a resistivity of the source region and the drain region is less than a resistivity of the channel region;
  • a second adjustment layer is disposed over a portion of the entire channel region of the thin film transistor, such that a thickness of the second adjustment layer is greater than a diffusion length of the oxygen-containing material in the adjustment layer;
  • Performing a second annealing process to form a depletion channel region by a second annealing process in the channel region covered by the conditioning layer, and a second region annealing in a channel region not covered by the second conditioning layer Processing to form an enhanced channel region, wherein the depletion mode channel region formed by the second annealing process has a resistivity less than the second annealing treatment a resistivity of the enhanced channel region formed;
  • the thin film transistor having the depletion channel region is a depletion thin film transistor, and the thin film transistor having the enhancement channel region is an enhancement thin film transistor; electrically connecting the depletion thin film transistor and the The enhanced thin film transistor constitutes a circuit.
  • the first annealing process and the second annealing process include heating the circuit structure with heat, light, laser, or microwave.
  • the first annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is between 100 ° C and 600 ° C; the second annealing treatment is continued under the oxidizing atmosphere 5 seconds to 5 hours, temperature between 100 ° C and 400 ° C.
  • the oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above substances.
  • the present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the circuit manufactured by the circuit manufacturing method described above.
  • the thin film transistor of the present invention has the following advantages: First, the present scheme directly forms a source region and a drain region in the active layer by annealing treatment, which is both maintained and backed.
  • the device size of the channel etch structure achieves high performance of the etch barrier structure device.
  • the advantages of high performance and small size are taken into account, which is in line with the current development trend of displays, especially in the development of augmented reality and virtual reality.
  • the annealing treatment reduces the resistivity of the source and drain regions, thereby reducing the parasitic contact resistance between the electrode and the active layer, and significantly improving the germanium performance of the thin film transistor.
  • the annealing treatment maintains or even increases the high resistivity of the channel region, the off-state current of the thin film transistor is remarkably lowered. More importantly, the annealing process will largely eliminate the defect density in the channel region and greatly improve the reliability of the device.
  • Second insulation above the channel region The channel region of the layer protection thin film transistor is protected from the external environment, and the environmental reliability of the device can be further enhanced.
  • the invention directly covers part of the active layer region with an electrode, and reduces the resistivity of the source region and the drain region under the electrode coverage by annealing treatment, and omits the complicated steps and the photolithography step in the conventional semiconductor process, thereby saving the preparation cost.
  • the same kind ensures the low resistivity stability of the source and drain regions. Therefore, the invention has the advantages of high performance, small size, high reliability, low cost, and the like.
  • a depletion type and enhancement type metal oxide thin film type thin film transistor is formed, and a method of forming an integrated circuit is based on using a specific adjustment layer metal oxide channel region, and an annealing treatment is used to adjust the resistivity of the channel region.
  • the threshold voltage of the thin film transistor is further adjusted. Since the adjustment layer is disposed only above the channel region of a portion of the thin film transistor, the device structure itself does not change much, and the method not only greatly simplifies the process, greatly reduces the cost, but also prepares with the existing metal oxide thin film transistor. The process is fully compatible, and the same can maximize the use of existing research results, and more importantly, to maintain the high performance of the device to the greatest extent, and to improve the performance of the constructed circuit.
  • the adjustment of the resistivity of the channel region is not only large in range but also high in precision, which is advantageous for accurately modulating the threshold voltage to further optimize the circuit performance in a targeted manner.
  • the overlying conditioning layer also enhances the protection of the channel region, further protecting it from the environment and enhancing device stability.
  • the intermediate insulating layer inherent in the display panel can be directly used as an adjustment layer covering the channel region or the intermediate insulating layer and the adjustment layer are patterned together to avoid additional lithography steps. Optimize the preparation process of the circuit. Brief description of the drawing
  • FIG. 1 is a cross-sectional view showing a first embodiment of a circuit structure in the present invention.
  • FIG. 2 is a cross-sectional view showing a second embodiment of the circuit structure of the present invention.
  • FIG 3 is a cross-sectional view showing a third embodiment of the circuit structure in the present invention.
  • FIG. 4 is a cross-sectional view showing a fourth embodiment of the circuit structure of the present invention.
  • FIG. 5 is a cross-sectional view showing a fifth embodiment of the circuit structure of the present invention.
  • FIG. 6 is a cross-sectional view showing a first embodiment of a display panel structure in accordance with the present invention.
  • FIG. 7 is a cross-sectional view showing a second embodiment of the structure of the display panel of the present invention.
  • FIG. 8 is a cross-sectional view showing a third embodiment of the structure of the display panel of the present invention.
  • FIG. 1 is a cross-sectional view showing a first embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting the electrode 4, the electrode 4 and the portion of the active layer from the through hole The regions are electrically connected; a third insulating layer 8 is disposed on the electrode 4. The projection area of the third insulating layer 8 and the projected area of the electrode 4 completely overlap.
  • the projected area is the projection area in the vertical direction shown in the drawings in the specific embodiment.
  • the substance containing oxygen when the thickness of the insulating layer or the conductor layer is smaller than the diffusion length of the substance containing oxygen in the insulating layer or the conductor layer, the substance containing oxygen can pass through the insulating layer in the annealing process or The conductor layer enters the active layer of the metal oxide to maintain, or even increase, the resistivity of the metal oxide.
  • the insulating layer or the conductor layer is an oxygen permeable layer; when an insulating layer or a conductor layer is thicker than the substance containing oxygen
  • the diffusion length ⁇ in the insulating layer, the insulating layer or the conductor layer can block the oxygen-containing material, thereby reducing the electrical resistivity of the metal oxide, and the insulating layer or the conductor layer is an oxygen-impermeable layer.
  • the oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
  • the substrate 1 includes, but is not limited to, the following materials: glass, polymer substrate, flexible material, and the like.
  • the active layer includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, cerium oxide, indium zinc oxide , zinc tin oxide, aluminum oxide tin, indium tin oxide, indium gallium zinc oxide, indium tin zinc zinc, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
  • the second insulating layer 7, the electrode 4, and the third insulating layer 8 collectively constitute the first conditioning layer 5.
  • the thickness of the first conditioning layer 5 is greater than the diffusion length of the oxygen-containing element in the first conditioning layer 5, and the first conditioning layer 5 is capable of blocking the oxygen-containing material, and thus the first conditioning layer 5 is Impervious to the oxygen layer.
  • the thickness of the first conditioning layer 5 is 2 to 100 times the diffusion length of the oxygen-containing substance in the first conditioning layer 5.
  • the thickness of the first insulating layer 6 is smaller than the diffusion length of the substance containing the oxygen element in the first insulating layer 6, and the substance containing the oxygen element can pass through the first annealing process.
  • An insulating layer 6 enters the channel region 22, and thus the first insulating layer 6 is an oxygen permeable layer.
  • the first insulating layer 6 comprises one or more of the following materials: silicon oxide, silicon oxynitride; further, the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the first insulating layer 6 has a thickness of 10 to 3000 nm. Preferably, the thickness of the first insulating layer 6 is between 200 nm and 50 nm.
  • the resistivity of the active layer under the coverage of the first adjustment layer 5 is lowered by the first annealing treatment to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing material can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in a region not covered by the first conditioning layer 5 The rate is maintained or even increased to form the channel region 22.
  • the resistivity of the channel region can be changed, thereby controlling the current passing through the channel region, thereby achieving the switching of the thin film transistor device.
  • the off-state current of a thin film transistor is highly dependent on the resistivity and defect density of the channel region. Higher resistivity and less defect density result in lower off-state current and better device performance.
  • the zeta current of the thin film transistor is limited by the resistivity of the source and drain regions, and the lower resistivity of the source and drain regions is beneficial to reduce parasitic resistance and increase the zeta current.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the first annealing treatment reduces the resistivity of the source region 21 and the drain region 23 while maintaining or even increasing the high resistivity of the channel region 22.
  • the source region 21, the drain region 23, and the channel region 22 in the active layer are connected to each other.
  • the connection surface between the source region 21, the drain region 23, and the channel region 22 formed by the first annealing process is automatically aligned with the first adjustment layer 5 covering the active layer without any photolithography alignment process. Border This is similar to the existing silicon-based FET process, in which the connection regions of the source region, the drain region and the channel region are automatically aligned to the gate electrode boundary. This self-alignment usually has a certain range of deviation.
  • connection faces of the source region, the drain region and the channel region are self-aligned with the vertical plane of the boundary of the first adjustment layer within the projected area of the active layer, and the alignment deviation is smaller than the thickness of the active layer. 100 times.
  • the first annealing treatment includes heating using heat, light, laser, or microwave.
  • the first annealing treatment is carried out under an oxidizing atmosphere for 10 seconds to 10 hours and at a temperature greater than 100 °C.
  • the temperature of the first annealing treatment is between 100 ° C and 600 ° C.
  • the temperature of the first annealing treatment is between 100 ° C and 500 ° C.
  • the oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide and a plasma of the above substances.
  • the resistivity ratio of the source region and the drain region obtained by the first annealing treatment in the present invention is complicated.
  • the resulting resistivity is lower, and the low resistivity of the source and drain regions under electrode protection is more stable.
  • the process of the present invention is simpler and less expensive than conventionally cumbersome methods.
  • the present invention is not limited to the cumbersome one or more of the following impurities in the active layer: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminum or antimony. This does not prevent the formation of source, channel and drain regions of the device. Therefore, the present invention is fully compatible with the existing complicated processes and has high scalability.
  • the annealing process in the present invention maintains and even improves the high resistivity of the channel region, thereby greatly reducing the off-state current of the thin film transistor, which is far lower than the current mainstream 10- 1 3 amps per micron, even down to very low 10-18 amps per micron. More importantly, annealing also largely eliminates the defect density in the channel region, such as oxygen vacancy defect density, metal interstitial defect density, etc. These defect densities are widely present in metal oxides and are considered It is an important factor in reducing the performance and reliability of thin film transistors, but it is difficult to completely eliminate them in the conventional device structure.
  • the thin film transistor structure disclosed in the present invention greatly enhances the performance and long-term reliability of the thin film transistor.
  • the current-to-voltage ratio of metal oxide thin film transistors is greatly increased, even higher than 1011; the threshold voltage drift caused by the common hysteresis effect is suppressed to within 0.15 V; a certain voltage is applied to the gate electrode.
  • the drift of the threshold voltage is degraded to around 0 V.
  • the first insulating layer covering the upper portion of the channel region can not only completely protect the channel region from the damage caused by the electrode etching like the etch barrier layer, but also protect the thin film transistor from the external environment.
  • Increase Environmental stability of strong thin film transistors for example, the problem of performance degradation such as threshold voltage drift caused by storing 10 small turns at 80 degrees Celsius and 80% relative humidity can be greatly improved by the structure of the thin film transistor of the present invention.
  • the novel thin film transistor of the present invention has many advantages over the conventional thin film transistor structure, including: a simpler manufacturing process, lower fabrication cost, higher process scalability, and better device performance. , reliability and environmental stability.
  • a circuit structure includes a substrate 1 and a plurality of thin film transistors formed of a metal oxide on the substrate 1 and constituting the active layer.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91.
  • the oxygen-containing material can enter the channel region 22 through the first insulating layer 6.
  • the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel.
  • the enhancement channel region 222 has a resistivity of 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is an enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement type thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • the thickness of the second insulation adjusting layer 91 is greater than the diffusion length of the oxygen-containing material in the second insulating adjustment layer 91, which can block the oxygen-containing substance, and thus the second insulation
  • the adjustment layer 91 is an oxygen-impermeable layer; preferably, the thickness of the second insulation adjustment layer 91 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second insulation adjustment layer 91.
  • the second insulation adjusting layer 91 includes a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is greater than 20% .
  • the second insulating adjustment layer 91 has a thickness of 10 to 3000 nm.
  • the second insulating adjustment layer 91 has a thickness of between 200 nm and 500 nm.
  • the second annealing treatment includes heating using heat, light, laser, or microwave.
  • the second annealing treatment is performed under the oxidizing atmosphere for between 5 seconds and 5 hours, and between 100 ° C and 500 ° C.
  • the temperature of the second annealing treatment is at 100 ° C and 400 Between °C.
  • the metal oxide material constituting the active layer of the depletion thin film transistor has a lower resistivity than the material constituting the active layer of the enhancement type thin film transistor.
  • the metal oxide constituting the active layer of the depletion thin film transistor has more conductive impurities such as indium or aluminum than the metal oxide constituting the active layer of the enhancement type thin film transistor.
  • the thickness of the metal oxide constituting the active layer of the thin film transistor is larger than the thickness of the metal oxide constituting the active layer of the enhancement type thin film transistor.
  • the active layer of the thin film transistor is composed of a laminate of a plurality of metal oxides, and the metal oxide of the stacked structure close to the gate insulating layer has a specific thin film transistor in the depletion thin film transistor.
  • these methods require separate adjustments of the active layers of the two modes of thin film transistors, and the material adjustment and process adjustment involved are relatively complicated. More importantly, all adjustments to the material, composition, thickness and stack of the active layer not only adjust the threshold voltage of the device, but also seriously affect other performance specifications of the device, so it is difficult to guarantee the same A high performance depletion thin film transistor and an enhancement thin film transistor are prepared. What's more, the adjustment of the material, composition, thickness and lamination of the active layer is bound to be limited without severely degrading the performance of the device. It is difficult to achieve a precise and wide range adjustment of the threshold voltage. .
  • the method of the present embodiment is based on controlling the structure of the cap layer on the channel region of the metal oxide, and adjusting the resistivity of the channel region by annealing treatment, thereby adjusting the threshold voltage of the thin film transistor. Since only the adjustment layer is disposed above part of the channel region, the device structure itself is completely unchanged, which not only greatly simplifies the process, greatly reduces the cost, but also is fully compatible with the existing metal oxide thin film transistor structure, and can maximize the use of existing The research results, more importantly, the high performance of the device is guaranteed to the greatest extent.
  • the adjustment of the resistivity of the channel region is not only large in scope but also high in precision, which is advantageous for accurately adjusting the threshold voltage to specifically optimize circuit performance.
  • the adjustment layer can also enhance the protection of the channel region, further protecting it from the environment and enhancing the stability of the device.
  • FIG. 2 is a cross-sectional view showing a second embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; above different regions of the active layer
  • the first insulating layer 6 and the oxygen-impermeable second insulating layer 71 are respectively covered; the second insulating layer 71 is formed with a through hole deep into the active layer, and a conductor is deposited in the through hole. Thereby extracting the electrode 4 from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer;
  • the thickness of the oxygen-impermeable second insulating layer 71 is greater than the diffusion length of the oxygen-containing element in the oxygen-impermeable second insulating layer 71, which can block the oxygen-containing substance
  • the oxygen impermeable second insulating layer 71 is an oxygen-impermeable layer; preferably, the thickness of the oxygen-impermeable second insulating layer 71 is 2 to the diffusion length of the oxygen-containing substance in the oxygen-impermeable second insulating layer 71 Between 100 times.
  • the oxygen impermeable second insulating layer 71 may be made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is more than 20%.
  • the oxygen impermeable second insulating layer 71 has a thickness of 10 to 3000 nm. Preferably, the thickness of the oxygen impermeable second insulating layer 71 is between 200 nm and 500 nm.
  • the resistivity of the active layer under the coverage of the oxygen-impermeable second insulating layer 71 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing element can enter the active layer through the first insulating layer 6, and thus the active layer is in the non-oxygen-free second insulating layer 71.
  • the resistivity of the area underlying is maintained even increased, forming channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of thin film transistors formed of a metal oxide on the substrate 1 over the substrate 1.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91.
  • the oxygen-containing material can enter the channel region 22 through the first insulating layer 6.
  • the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel.
  • the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221.
  • Thin film crystal having depletion channel region 221 The transistor is a depletion thin film transistor 121, and the thin film transistor having the enhancement type channel region 222 is an enhancement type thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • FIG. 3 is a cross-sectional view showing a third embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting the electrode 4, the electrode 4 and the portion of the active layer from the through hole The regions are electrically connected; the third insulating layer 8 is disposed on the electrode 4, the first insulating layer 6, and the second insulating layer 7; the projected area of the third insulating layer 8 completely overlaps the projected area of the second insulating layer 7.
  • the thickness of the third insulating layer 8 is greater than the diffusion length of the oxygen-containing material in the third insulating layer 8, which can block the oxygen-containing material, and the third insulating layer 8 is Oxygen-impermeable layer; Preferably, the thickness of the third insulating layer 8 is between 2 and 100 times the diffusion length of the oxygen-containing material in the third insulating layer 8.
  • the third insulating layer 8 may be made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is more than 20%.
  • the third insulating layer 8 has a thickness of 10 to 3000 nm. Preferably, the thickness of the third insulating layer 8 is between 200 nm and 500 nm.
  • the resistivity of the active layer under the coverage of the third insulating layer 8 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in a region covered by the non-third insulating layer 8 The rate is maintained or even increased to form the channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of thin film transistors on the substrate 1 which are composed of a metal oxide.
  • the entire channel region of a portion of the thin film transistor It is completely covered by the second adjustment layer 9. Performing a second annealing process on the thin film transistor structure.
  • the oxygen-containing material can pass through the first insulating layer 6 into the channel region 22, and further The resistivity of the channel region 22 is maintained, or even increased, to form the enhanced channel region 222; conversely, the second conditioning layer 9 can block the oxygen-containing species for the channel region 22, thereby reducing the channel region 22
  • the resistivity is such that a depletion channel region 221 is formed, and the resistivity of the depletion channel region 221 is smaller than that of the enhancement channel region 222.
  • the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is the enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • the thickness of the second conditioning layer 9 is greater than the diffusion length of the oxygen-containing material in the second conditioning layer 9, which blocks the oxygen-containing material, and the second conditioning layer 9 is Oxygen-impermeable layer; Preferably, the thickness of the second conditioning layer 9 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second conditioning layer 9.
  • the second conditioning layer 9 comprises a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, silicon, gallium arsenide, titanium, molybdenum, aluminum, copper, silver, gold, Nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy, wherein the proportion of silicon nitride in the silicon oxynitride is greater than 20%.
  • the second conditioning layer 9 has a thickness of 10 to 3000 nm. Preferably, the thickness of the second conditioning layer 9 is between 200 nm and 500 nm.
  • FIG. 4 is a cross-sectional view showing a fourth embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting an oxygen-impermeable electrode 41 from the through hole, and the oxygen-impermeable electrode 41 and the Portions of the active layer are electrically connected; the projected area of the oxygen-impermeable electrode 41 completely overlaps with the projected area of the second insulating layer 7.
  • the thickness of the oxygen-impermeable electrode 41 is greater than the diffusion length of the oxygen-containing element in the oxygen-impermeable electrode 41, and the oxygen-impermeable electrode 41 can block the substance containing the oxygen element, and thus Oxygen permeable electrode 41 is not Oxygen permeable layer.
  • the thickness of the oxygen-impermeable electrode 41 is between 2 and 100 times the diffusion length of the oxygen-containing element in the oxygen-impermeable electrode 41.
  • the oxygen-impermeable electrode 41 comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, niobium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, Molybdenum copper alloy or copper aluminum alloy.
  • the oxygen-impermeable electrode 41 has a thickness of 10 to 3000 nm. Preferably, the thickness of the oxygen-impermeable electrode 41 is between 200 nm and 500 nm.
  • the resistivity of the active layer under the area covered by the oxygen-impermeable electrode 41 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in the region covered by the non-oxygen-impermeable electrode 41 The rate is maintained or even increased to form the channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of thin film transistors on the substrate 1 which are composed of a metal oxide to form the active layer.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91.
  • the oxygen-containing material can enter the channel region 22 through the first insulating layer 6.
  • the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel.
  • the enhancement channel region 222 has a resistivity of 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is an enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement type thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • FIG. 5 is a cross-sectional view showing a fifth embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; An oxygen permeable gate electrode 311 and an oxygen permeable gate insulating layer 321 disposed between the oxygen permeable gate electrode 311 and the active layer are disposed between the active layers; the active layer is different A first insulating layer 6 and a second insulating layer 7 are respectively covered on the upper portion of the region; a through hole deep to the active layer is formed on the second insulating layer 7 and the oxygen permeable gate insulating layer 321 A conductor is accumulated so that the electrode 4 is drawn from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer.
  • the third insulating layer 8 is also covered on the electrode 4; the projected area of the third insulating layer 8 and the projected area of the second insulating layer 7 completely overlap.
  • the thickness of the oxygen permeable gate electrode 311 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate electrode 31 1 , and the oxygen-containing substance can be in the first annealing process.
  • the oxygen permeable gate electrode 311 enters the channel region 22, and thus the oxygen permeable gate electrode 311 is an oxygen permeable layer.
  • the oxygen permeable gate electrode 311 comprises one or more combinations of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium zinc oxide.
  • the oxygen permeable gate electrode 311 has a thickness of 10 to 3000 nm.
  • the oxygen permeable gate electrode 311 has a thickness between 200 nm and 500 nm.
  • the thickness of the oxygen permeable gate insulating layer 321 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate insulating layer 321, and the oxygen-containing substance is in the first annealing process.
  • the channel region 22 can be accessed through the oxygen permeable gate insulating layer 321, so that the oxygen permeable gate insulating layer 321 is an oxygen permeable layer.
  • the oxygen permeable gate insulating layer 321 includes one or more combinations of the following materials: silicon oxide, silicon oxynitride; and the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the oxygen permeable gate insulating layer 321 has a thickness of 10 to 3000 nm.
  • the oxygen permeable gate insulating layer 321 has a thickness of between 200 nm and 500 nm.
  • the resistivity of the active layer under the coverage of the third insulating layer 8 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer through the first insulating layer 6, the oxygen-permeable gate insulating layer 321, and the oxygen-permeable gate electrode 311, so The resistivity of the region of the source layer covered by the non-third insulating layer 8 is maintained or even increased to form the channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of the metal oxide oxides on the substrate 1 Thin film transistor of the active layer.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second adjustment layer 9. Performing a second annealing process on the thin film transistor structure.
  • the oxygen-containing material can pass through the first insulating layer 6 into the channel region 22, and further The resistivity of the channel region 22 is maintained, or even increased, to form the enhanced channel region 222; conversely, the second conditioning layer 9 can block the oxygen-containing species for the channel region 22, thereby reducing the channel region 22
  • the resistivity is such that a depletion channel region 221 is formed, and the resistivity of the depletion channel region 221 is smaller than that of the enhancement channel region 222.
  • the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is the enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power supply electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form a circuit.
  • FIG. 6 is a cross-sectional view showing a first embodiment of a display panel structure in accordance with the present invention.
  • the display panel is composed of a plurality of display modules, and the display module includes: a thin film transistor disposed on the substrate 1; an intermediate insulating layer 13 disposed on the thin film transistor; a second insulating adjustment layer 91 and an intermediate insulating layer 13 a through hole deep in the electrode 4 is formed, and a conductor is deposited in the through hole, thereby extracting the pixel electrode 14 from the through hole, and the pixel electrode 14 is electrically connected to the thin film transistor; the intermediate insulating layer 13 and A photovoltaic material 15 and a common electrode 16 are disposed over the pixel electrode 14.
  • the photoelectric material 15 includes, but is not limited to, a liquid crystal, a light emitting diode, an organic light emitting diode, and a quantum dot light emitting diode.
  • the circuit structure shown in FIG. 2 is used to form the pixel circuit and the driving circuit.
  • FIG. 7 is a cross-sectional view showing a second embodiment of the structure of the display panel of the present invention.
  • the display panel is composed of a plurality of display modules, and the display module includes: a thin film transistor disposed on the substrate 1; an intermediate insulating layer 13 disposed on the thin film transistor; a second insulating adjustment layer 91 and an intermediate insulating layer 13 a through hole deep in the electrode 4 is formed, and a conductor is deposited in the through hole, thereby extracting the pixel electrode 14 from the through hole, and the pixel electrode 14 is electrically connected to the thin film transistor; the intermediate insulating layer 13 and A photovoltaic material 15 and a common electrode 16 are disposed over the pixel electrode 14.
  • the display panel in this embodiment is similar to the circuit structure shown in FIG. 2 to form a pixel circuit and a driving circuit.
  • the difference between this embodiment and the embodiment shown in FIG. 6 is that the portion of the second insulating adjustment layer 91 on the enhancement type channel region 222 does not need to be removed by a separate photolithography step, but the light of the intermediate insulating layer 13 Engraved together.
  • this embodiment section A lithography step is saved, which greatly simplifies the process and reduces costs.
  • the projected area of the second insulating adjustment layer 91 completely overlaps with the projected area of the intermediate insulating layer 13.
  • FIG. 8 is a cross-sectional view showing a third embodiment of the display panel structure of the present invention.
  • the display module of this embodiment is similar to the display module shown in FIG. The difference is that the display module of the present embodiment has no intermediate insulating layer 13, and the function of the intermediate insulating layer 13 is taken care of by the second insulating regulating layer 91.
  • this embodiment also saves a lithography step, greatly simplifying the process and reducing the cost.

Abstract

A circuit structure comprising multiple thin-film transistors (TFTs), the structure of said TFTs comprising: a substrate (1) and an active layer consisting of metal oxide on said substrate (1); the active layer adjoins a gate stack (3), and some regions of the active layer are covered by a first adjustment layer (5); the regions of the active layer covered by the first adjustment layer (5) are formed into a source region (21) and a drain region (23) respectively, and regions not covered by the first adjustment layer (5) form a channel region (22); the source region (21) and drain region (23) are connected to the channel region (22), being positioned on either side thereof, and the channel region (22) adjoins the gate stack (3); a second adjustment layer (91) is provided above the entirety of the channel region (22) of some TFTs, the region under the second adjustment layer forming a depletion channel region (221) and the region not covered by the second adjustment layer (91) forming an enhancement channel region; TFTs having said depletion channel region are depletion mode TFTs (121), and TFTs having said enhancement channel regions are enhancement mode TFTs; depletion mode TFTs (121) and enhancement mode TFTs (122) are electrically connected to each other to form the circuit.

Description

一种薄膜晶体管构成的电路结构及制造方法和显示器面 板  Circuit structure and manufacturing method composed of thin film transistor and display panel
技术领域  Technical field
[0001] 本发明涉及一种由金属氧化物薄膜晶体管构成的电路结构和制造方法， 尤其是 用于显示器面板的模块中的电路。  [0001] The present invention relates to a circuit structure and a manufacturing method composed of a metal oxide thin film transistor, particularly a circuit used in a module of a display panel.
背景技术  Background technique
[0002] 作为构成显示器面板中电路不可或缺的有源器件， 薄膜晶体管的性能直接影响 显示器的性能。 相比于传统的硅基薄膜晶体管， 由金属氧化物构成有源层的薄 膜晶体管具有诸多优势， 比如低温工艺、 高透明度、 高迁移率、 低漏电等， 其 被认为是显示器面板中硅基器件的最有希望替代者。 但是， 传统的金属氧化物 薄膜晶体管在制造工艺、 器件结构和电路应用方面还存在明显的不足。  [0002] As an active device that is indispensable for constituting a circuit in a display panel, the performance of a thin film transistor directly affects the performance of the display. Compared to conventional silicon-based thin film transistors, thin film transistors composed of metal oxide active layers have many advantages, such as low temperature process, high transparency, high mobility, low leakage, etc., which are considered to be silicon-based devices in display panels. The most promising replacement. However, conventional metal oxide thin film transistors have significant deficiencies in manufacturing processes, device structures, and circuit applications.
[0003] 传统的金属氧化物薄膜晶体管通过在有源层上淀积金属来作为电极。 在电极和 有源层的接触界面处通常会形成肖特基势垒， 造成氧化物和金属界面的高接触 电阻， 同吋本征态的金属氧化物半导体通常是高电阻率的， 这会带来高的源漏 寄生电阻的问题。 现有的解决办法是通过对源区、 漏区进行惨杂来降低源区、 漏区的电阻率， 但这通常以牺牲工艺稳定性和增加制备成本为代价。 例如， 源 漏区域可以通过等离子处理将氢离子惨杂到源区、 漏区中， 但惨杂效果并不稳 定。 其他惨杂物， 例如硼和磷， 则需要极为昂贵的离子注入设备以及额外的激 活过程。 为此， 在薄膜晶体管制造行业急需要一种成本低廉、 制造工艺简单的 方法来降低金属氧化物源漏区域的电阻率， 从而提高器件性能。  A conventional metal oxide thin film transistor is used as an electrode by depositing a metal on an active layer. A Schottky barrier is usually formed at the contact interface between the electrode and the active layer, resulting in a high contact resistance between the oxide and the metal interface, and the eigenstate metal oxide semiconductor is usually high resistivity, which is carried The problem of high source-drain parasitic resistance. The existing solution is to reduce the resistivity of the source and drain regions by making the source and drain regions cumbersome, but this is usually at the expense of process stability and increased manufacturing costs. For example, the source and drain regions can be mischarged into the source and drain regions by plasma treatment, but the effects are not stable. Other filths, such as boron and phosphorus, require extremely expensive ion implantation equipment and additional activation processes. For this reason, there is an urgent need in the thin film transistor manufacturing industry for a low cost, simple manufacturing process to reduce the resistivity of the metal oxide source and drain regions, thereby improving device performance.
[0004] 另一方面， 背沟道刻蚀结构和刻蚀阻挡层结构是背栅金属氧化物薄膜晶体管的 两种主流结构。 在传统背沟道刻蚀结构的薄膜晶体管中， 暴露的沟道上界面会 在刻蚀电极的吋候受到损害， 进而影响到器件的性能。 虽然这样的损害可以通 过在沟道区上添加一层刻蚀阻挡层来避免， 但是这样不仅会增加一步额外的光 刻过程、 从而增加制备成本， 更重要的是刻蚀阻挡层器件结构需要延长沟道长 度和栅极电极的长度， 这样会扩大薄膜晶体管的面积、 进而极大地限制显示器 的分辨率的进一步提升， 背离了显示器的高分辨率发展趋势。 归纳而言， 背沟 道刻蚀的器件结构的优势在于提供了简单的工艺过程、 较低的制备成本和较小 的器件尺寸， 而刻蚀阻挡层的器件结构提供了更优的器件性能和改善的器件稳 定性， 但扩大了器件的面积， 增加了制造成本。 为此， 金属氧化物薄膜晶体管 制造业急需一种新型的薄膜晶体管结构， 能够同吋满足低成本、 高性能、 小尺 寸等多重要求。 [0004] On the other hand, the back channel etch structure and the etch barrier structure are two main structures of the back gate metal oxide thin film transistor. In a thin film transistor of a conventional back channel etch structure, the exposed interface on the channel is damaged at the time of etching the electrode, thereby affecting the performance of the device. Although such damage can be avoided by adding an etch stop layer to the channel region, this not only adds an additional lithography process, but also increases the fabrication cost. More importantly, the etch barrier device structure needs to be extended. The length of the channel and the length of the gate electrode, which enlarges the area of the thin film transistor, thereby greatly limiting the display The further increase in resolution deviates from the high resolution trend of the display. In summary, the advantages of the back-channel etched device structure are that it provides a simple process, lower fabrication cost, and smaller device size, while the device structure of the etch barrier provides better device performance and Improved device stability, but increases the area of the device and increases manufacturing costs. For this reason, the metal oxide thin film transistor manufacturing industry urgently needs a novel thin film transistor structure, which can meet the multiple requirements of low cost, high performance, small size, and the like.
[0005] 在显示面板的电路应用方面， 金属氧化物薄膜晶体管相比于传统硅基薄膜晶体 管也还存在一个明显的缺陷密度。 虽然金属氧化物薄膜晶体管的性能经历了多 年发展已经有了显著提升， 特别是借助本发明的薄膜晶体管工艺和结构能得到 进一步的提升。 但是， 目前主流的金属氧化物薄膜晶体管还都是 n型薄膜晶体管 ， 性能优良的 p型金属氧化物薄膜晶体管还很难实现。 而对电路的功耗和其它性 能参数的进一步改良， 不再能够单独依赖于薄膜晶体管自身性能的提升， 而且 还需要一种有源"上拉"器件。 对于传统的硅基薄膜晶体管， 这种有源"上拉"器件 就是 p型薄膜晶体管， 但是对于金属氧化物薄膜晶体管来说情况完全不同。 鉴于 金属氧化物薄膜晶体管构成的电路目前只能基于 n型器件， 因此很难像硅基器件 一样采用 n型和 p型薄膜晶体管互补的方式制备高性能的电路。 为了实现性能相 对良好的电路， 广泛采用的替代方法是利用耗尽型的 n型金属氧化物薄膜晶体管 作为有源"上拉"器件， 而用增强型的 n型薄膜晶体管作为有源"下拉"器件。 其中 ， 耗尽型薄膜晶体管的阈值电压比增强型薄膜晶体管的阈值电压低。  [0005] In terms of circuit applications of display panels, metal oxide thin film transistors also have a significant defect density compared to conventional silicon-based thin film transistors. Although the performance of metal oxide thin film transistors has been significantly improved over the years, the thin film transistor process and structure of the present invention can be further improved. However, current mainstream metal oxide thin film transistors are also n-type thin film transistors, and p-type metal oxide thin film transistors with excellent performance are still difficult to implement. Further improvements in power consumption and other performance parameters of the circuit can no longer rely solely on the performance improvement of the thin film transistor itself, but also require an active "pull-up" device. For conventional silicon-based thin film transistors, this active "pull-up" device is a p-type thin film transistor, but for metal oxide thin film transistors the situation is completely different. Since circuits composed of metal oxide thin film transistors can only be based on n-type devices, it is difficult to prepare high-performance circuits in a complementary manner to n-type and p-type thin film transistors like silicon-based devices. In order to achieve a relatively good performance circuit, a widely used alternative is to use a depletion type n-type metal oxide thin film transistor as an active "pull-up" device, and an enhanced n-type thin film transistor as an active "pull-down". Device. Wherein, the threshold voltage of the depletion thin film transistor is lower than the threshold voltage of the enhancement type thin film transistor.
[0006] 采用这种方式制备的反向器电路已有很多报道。 实现耗尽型的和增强型的薄膜 晶体管的单片集成的方法主要包括： 调整金属氧化物有源层的材料成分、 调节 有源层的厚度、 采用多层结构的有源层等。 然而上述方法对薄膜晶体管阈值电 压的调节十分受限， 并且其工艺复杂， 器件性能严重受限于制备过程。 另外一 类调节阈值电压形成耗尽型和增强型薄膜晶体管的方式是通过引入一个额外的 栅极叠层， 从而形成双栅结构。 额外的栅极叠层专门负责调节薄膜晶体管的阈 值电压， 因此调节范围更大。 但是， 这额外的栅极叠层需要配置额外的控制电 路， 极大地增加了制备电路的复杂度和成本， 与现有的器件结构也不兼容， 背 离了目前显示器面板高分辨率的发展趋势。 为此， 显示面板制造业急需一种新 型的调节金属氧化物薄膜晶体管阈值电压的方法， 能够在保证薄膜晶体管的高 性能指标的前提下增加了器件阈值电压的调制范围， 同吋保持了简单易行， 成 本低廉的制造工艺。 [0006] There have been many reports on inverter circuits prepared in this manner. The method for realizing the monolithic integration of the depletion mode and the enhancement type thin film transistor mainly includes: adjusting the material composition of the metal oxide active layer, adjusting the thickness of the active layer, using an active layer of a multilayer structure, or the like. However, the above method is very limited in adjusting the threshold voltage of the thin film transistor, and the process is complicated, and the device performance is severely limited by the preparation process. Another way to adjust the threshold voltage to form depletion mode and enhancement thin film transistors is by introducing an additional gate stack to form a double gate structure. The additional gate stack is specifically responsible for adjusting the threshold voltage of the thin film transistor, so the adjustment range is larger. However, this additional gate stack requires additional control circuitry, which greatly increases the complexity and cost of the fabrication circuitry, and is not compatible with existing device architectures, deviating from the current high resolution trends in display panels. To this end, display panel manufacturing urgently needs a new The method of adjusting the threshold voltage of the metal oxide thin film transistor can increase the modulation range of the threshold voltage of the device under the premise of ensuring the high performance index of the thin film transistor, and maintain the simple and easy-to-cost manufacturing process.
技术问题  technical problem
[0007] 本发明所要解决的技术问题在于克服上述现有技术之不足， 提供一种有效调节 金属氧化物薄膜晶体管的阈值电压， 集成增强型薄膜晶体管和耗尽型薄膜晶体 管的电路结构， 可在增加薄膜晶体管阈值电压的调制范围的同吋还保持了薄膜 晶体管的高性能， 并简化了现有的制造工艺， 降低了制造成本， 其可以有效地 应用于集成电路， 特别是显示器面板中的电路。  [0007] The technical problem to be solved by the present invention is to overcome the above-mentioned deficiencies of the prior art, and provide a circuit structure for effectively adjusting a threshold voltage of a metal oxide thin film transistor, an integrated enhancement thin film transistor and a depletion thin film transistor, Increasing the modulation range of the threshold voltage of the thin film transistor also maintains the high performance of the thin film transistor, simplifies the existing manufacturing process, and reduces the manufacturing cost, and can be effectively applied to an integrated circuit, particularly a circuit in a display panel. .
问题的解决方案  Problem solution
技术解决方案  Technical solution
[0008] 本发明提供的一种薄膜晶体管电路结构， 所述薄膜晶体管的结构包括： 衬底和 位于所述衬底之上的由金属氧化物构成的有源层； 所述有源层与栅极叠层相毗 令 所述有源层的部分区域上覆盖有第一调节层， 所述第一调节层的厚度大于 含氧元素的物质在所述第一调节层中的扩散长度； 所述有源层在所述第一调节 层覆盖下的区域分别形成源区、 漏区， 在非所述第一调节层覆盖下的区域形成 沟道区； 所述源区、 所述漏区与所述沟道区相互连接， 且分别位于所述沟道区 的两端， 所述沟道区与所述栅极叠层相毗邻； 所述源区、 所述漏区和所述沟道 区的连接面自对准于所述第一调节层在所述有源层投影面积之内的边界的铅垂 面； 所述源区、 所述漏区的电阻率小于所述沟道区的电阻率； 部分薄膜晶体管 的整个沟道区上方设置有第二调节层， 在所述第二调节层覆盖下的形成耗尽型 沟道区， 在非所述第二调节层覆盖下的形成增强型沟道区， 所述耗尽型沟道区 的电阻率小于所述增强型沟道区的电阻率； 所述第二调节层的厚度大于所述含 氧元素的物质在所述第二调节层中的扩散长度； 具有所述耗尽型沟道区的薄膜 晶体管为耗尽型薄膜晶体管， 具有所述增强型沟道区的薄膜晶体管为增强型薄 膜晶体管； 所述耗尽型薄膜晶体管和所述增强型薄膜晶体管相互电连接构成电 路。  [0008] The present invention provides a thin film transistor circuit structure, the structure of the thin film transistor includes: a substrate and an active layer made of a metal oxide on the substrate; the active layer and the gate a portion of the active layer is covered with a first conditioning layer, the first conditioning layer having a thickness greater than a diffusion length of the oxygen-containing material in the first conditioning layer; Forming a source region and a drain region in a region covered by the first adjustment layer, and forming a channel region in a region not covered by the first adjustment layer; the source region, the drain region, and the The channel regions are connected to each other and are respectively located at two ends of the channel region, the channel region is adjacent to the gate stack; the source region, the drain region and the channel region The connection surface is self-aligned with a vertical surface of a boundary of the first adjustment layer within a projected area of the active layer; the resistivity of the source region and the drain region is smaller than a resistivity of the channel region a second adjustment layer is disposed over the entire channel region of the partial thin film transistor. Forming a depletion mode channel region under the cover of the second adjustment layer, forming an enhancement channel region under the cover of the second adjustment layer, the depletion mode channel region having a resistivity less than a resistivity of the enhanced channel region; a thickness of the second conditioning layer being greater than a diffusion length of the oxygen-containing material in the second conditioning layer; and a thin film transistor having the depletion channel region A depletion thin film transistor, the thin film transistor having the enhanced channel region is an enhancement thin film transistor; and the depletion thin film transistor and the enhancement thin film transistor are electrically connected to each other to constitute a circuit.
[0009] 作为上述电路结构优选的方式： [0010] 所述源区、 所述漏区与所述沟道区的连接面和所述第一调节层在所述有源层投 影面积之内的边界的铅垂面的间距小于所述有源层厚度的 100倍。 [0009] A preferred method as the above circuit structure: [0010] a distance between a connection surface of the source region, the drain region and the channel region, and a vertical plane of a boundary of the first adjustment layer within a projected area of the active layer is smaller than the 100 times the thickness of the source layer.
[0011] 所述沟道区与所述源区、 所述漏区的电阻率比值大于 1000倍； 所述增强型沟道 区的电阻率为所述耗尽型沟道区的电阻率的 2至 100倍。  [0011] a ratio of resistivity of the channel region to the source region and the drain region is greater than 1000 times; a resistivity of the enhanced channel region is 2 of a resistivity of the depletion channel region Up to 100 times.
[0012] 所述有源层包括以下材料中的一种或多种的组合： 氧化锌、 氮氧化锌、 氧化锡 [0012] The active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide
、 氧化铟、 氧化镓、 氧化铜、 氧化铋、 氧化铟锌、 氧化锌锡、 氧化铝锡、 氧化 铟锡、 氧化铟镓锌、 氧化铟锡锌、 氧化铝铟锡锌、 硫化锌、 钛酸钡、 钛酸锶或 铌酸锂。 , indium oxide, gallium oxide, copper oxide, antimony oxide, indium zinc oxide, zinc tin oxide, aluminum oxide tin, indium tin oxide, indium gallium zinc oxide, indium tin zinc, aluminum oxide indium tin zinc, zinc sulfide, titanic acid Barium, barium titanate or lithium niobate.
[0013] 所述第一调节层的厚度为所述含氧元素的物质在所述第一调节层中的扩散长度 的 2至 100倍之间， 所述第二调节层的厚度为所述含氧元素的物质在所述第二调 节层中的扩散长度的 2至 100倍之间。  [0013] The thickness of the first adjustment layer is between 2 and 100 times the diffusion length of the oxygen-containing substance in the first adjustment layer, and the thickness of the second adjustment layer is the The substance of the oxygen element is between 2 and 100 times the diffusion length in the second conditioning layer.
[0014] 所述第一调节层和所述第二调节层包括以下材料中的一种或多种的组合： 氮化 硅、 氮氧化硅、 氧化铝、 氧化铪、 硅、 砷化镓， 钛、 钼、 铝、 铜、 银、 金、 镍 、 钨、 铬、 铪、 铂、 铁、 钛钨合金、 钼铝合金、 钼铜合金或铜铝合金； 其中， 所述氮氧化硅中的氮化硅比例大于 20%。 所述第一调节层的厚度为 10至 3000纳米 ， 所述第二调节层的厚度为 10至 3000纳米。  [0014] The first conditioning layer and the second conditioning layer comprise a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, silicon, gallium arsenide, titanium , molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy; wherein, the nitridation in the silicon oxynitride The silicon ratio is greater than 20%. The first conditioning layer has a thickness of 10 to 3000 nm, and the second conditioning layer has a thickness of 10 to 3000 nm.
[0015] 所述栅极叠层可设置在所述有源层与所述衬底之间； 或者，  [0015] the gate stack may be disposed between the active layer and the substrate; or
[0016] 将所述有源层设置在所述栅极叠层和所述衬底之间。 进一步地， 所述栅极叠层 包括栅极电极和栅极绝缘层， 所述栅极电极的厚度小于所述含氧元素的物质在 所述栅极电极中的扩散长度， 所述栅极绝缘层的厚度小于所述含氧元素的物质 在所述栅极绝缘层中的扩散长度。 所述栅极电极包含以下材料中的一种或多种 的组合： 氧化锌、 氧化铟锡、 氧化铝锌、 氧化铟铝或氧化铟锌； 所述栅极绝缘 层包含以下材料中的一种或多种的组合： 氧化硅、 氮氧化硅， 其中所述氮氧化 硅中氮化硅的比例小于 20%。 所述栅极电极的厚度为 10至 3000纳米； 所述栅极绝 缘层的厚度为 10至 3000纳米。  [0016] The active layer is disposed between the gate stack and the substrate. Further, the gate stack includes a gate electrode and a gate insulating layer, the gate electrode has a thickness smaller than a diffusion length of the oxygen-containing material in the gate electrode, and the gate insulating layer The thickness of the layer is less than the diffusion length of the oxygen-containing material in the gate insulating layer. The gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or indium zinc oxide; the gate insulating layer comprises one of the following materials Or a combination of a plurality of: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm.
[0017] 所述含氧元素的物质包括： 氧气、 臭氧、 一氧化二氮、 水、 双氧水、 二氧化碳 和以上物质的等离子体。 本发明还提供了一种显示器面板， 包括多组显示模块 ， 所述显示模块包括上述所述的电路结构。 [0018] 本发明还提供了另一种显示器面板， 包括多组显示模块， 所述显示模块包含： 薄膜晶体管、 中间绝缘层以及像素电极； 所述薄膜晶体管与所述像素电极相电 连接， 所述中间绝缘层位于所述薄膜晶体管和所述像素电极之间， 所述第二调 节层的投影面积和所述中间绝缘层的投影面积完全重叠， 所述薄膜晶体管相互 电连接构成像素电路和显示驱动电路， 所述像素电路和所述显示驱动电路的结 构包括上述所述的电路结构。 [0017] The oxygen element-containing substance includes: plasma of oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and the like. The present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the circuit structure described above. [0018] The present invention further provides another display panel, including a plurality of sets of display modules, the display module includes: a thin film transistor, an intermediate insulating layer, and a pixel electrode; the thin film transistor is electrically connected to the pixel electrode, The intermediate insulating layer is located between the thin film transistor and the pixel electrode, the projected area of the second adjusting layer and the projected area of the intermediate insulating layer completely overlap, and the thin film transistors are electrically connected to each other to form a pixel circuit and display The driving circuit, the structure of the pixel circuit and the display driving circuit include the circuit structure described above.
[0019] 本发明还提供了再一种显示器面板， 包括多组显示模块， 所述显示模块中包含 [0019] The present invention further provides a display panel, comprising a plurality of sets of display modules, wherein the display module includes
： 薄膜晶体管、 以及像素电极； 所述薄膜晶体管与所述像素电极相电连接， 所 述薄膜晶体管相互电连接构成像素电路和显示驱动电路， 所述像素电路和所述 显示驱动电路的结构包括上述所述的电路结构。 a thin film transistor and a pixel electrode; the thin film transistor is electrically connected to the pixel electrode, the thin film transistors are electrically connected to each other to form a pixel circuit and a display driving circuit, and the structure of the pixel circuit and the display driving circuit includes the above The circuit structure described.
[0020] 本发明还提供了一种薄膜晶体管电路制造方法， 包含： [0020] The present invention also provides a method for fabricating a thin film transistor circuit, comprising:
[0021] 准备一个衬底； [0021] preparing a substrate;
[0022] 在所述衬底之上设置有源层和与所述有源层相毗邻的栅极叠层， 所述有源层由 金属氧化物构成；  [0022] an active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
[0023] 在所述有源层的部分区域上设置第一调节层， 使所述第一调节层的厚度大于含 氧元素的物质在所述第一调节层中的扩散长度；  [0023] providing a first adjustment layer on a partial region of the active layer, such that a thickness of the first adjustment layer is greater than a diffusion length of a substance containing an oxygen element in the first adjustment layer;
[0024] 进行第一退火处理， 使所述有源层在所述第一调节层覆盖下的区域分别第一退 火处理形成源区、 漏区， 在非所述第一调节层覆盖下的区域第一退火处理形成 沟道区， 所述沟道区与所述栅极叠层相毗邻， 所述源区、 所述漏区与所述沟道 区相互连接， 且分别位于所述沟道区的两端， 所述源区、 所述漏区和所述沟道 区之间由所述第一退火处理形成的连接面自对准于所述第一调节层在所述有源 层投影面积之内的边界的铅垂面， 所述源区、 所述漏区的电阻率小于所述沟道 区的电阻率；  [0024] performing a first annealing process, so that the regions of the active layer covered by the first conditioning layer are respectively first annealed to form a source region and a drain region, and regions not covered by the first conditioning layer a first annealing process forms a channel region, the channel region is adjacent to the gate stack, the source region, the drain region and the channel region are connected to each other, and are respectively located in the channel region The connecting surface formed by the first annealing process between the source region, the drain region and the channel region is self-aligned with the projected area of the active layer in the active layer a vertical plane of a boundary within the boundary, wherein a resistivity of the source region and the drain region is less than a resistivity of the channel region;
[0025] 在部分所述薄膜晶体管的整个沟道区之上设置第二调节层， 使所述第二调节层 的厚度大于所述含氧元素的物质在所述调节层中的扩散长度；  [0025] a second adjustment layer is disposed over a portion of the entire channel region of the thin film transistor, such that a thickness of the second adjustment layer is greater than a diffusion length of the oxygen-containing material in the adjustment layer;
[0026] 进行第二退火处理， 使在所述调节层覆盖下的沟道区第二退火处理形成耗尽型 沟道区， 在非所述第二调节层覆盖下的沟道区第二退火处理形成增强型沟道区 ， 所述第二退火处理形成的所述耗尽型沟道区的电阻率小于所述第二退火处理 形成的所述增强型沟道区的电阻率； Performing a second annealing process to form a depletion channel region by a second annealing process in the channel region covered by the conditioning layer, and a second region annealing in a channel region not covered by the second conditioning layer Processing to form an enhanced channel region, wherein the depletion mode channel region formed by the second annealing process has a resistivity less than the second annealing treatment a resistivity of the enhanced channel region formed;
[0027] 具有所述耗尽型沟道区的薄膜晶体管为耗尽型薄膜晶体管， 具有所述增强型沟 道区的薄膜晶体管为增强型薄膜晶体管； 电连接所述耗尽型薄膜晶体管和所述 增强型薄膜晶体管， 即构成电路。 [0027] The thin film transistor having the depletion channel region is a depletion thin film transistor, and the thin film transistor having the enhancement channel region is an enhancement thin film transistor; electrically connecting the depletion thin film transistor and the The enhanced thin film transistor constitutes a circuit.
[0028] 作为本发明上述所述的电路制作方法优选的方式： [0028] A preferred method of the above-described circuit fabrication method of the present invention:
[0029] 所述源区、 所述漏区和所述沟道区之间由所述第一退火处理形成的连接面和所 述第一调节层在所述有源层投影面积之内的边界的铅垂面的间距小于所述有源 层厚度的 100倍。  [0029] a boundary between the source region, the drain region, and the channel region formed by the first annealing process and a boundary of the first adjustment layer within a projected area of the active layer The pitch of the vertical plane is less than 100 times the thickness of the active layer.
[0030] 所述第一退火处理和所述第二退火处理包括利用热、 光、 激光、 微波对所述电 路结构进行加热。  [0030] The first annealing process and the second annealing process include heating the circuit structure with heat, light, laser, or microwave.
[0031] 所述第一退火处理是在氧化气氛下， 持续 10秒至 10小吋， 温度在 100°C和 600°C 之间； 所述第二退火处理是在所述氧化气氛下， 持续 5秒至 5小吋， 温度在 100°C 和 400°C之间。  [0031] the first annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is between 100 ° C and 600 ° C; the second annealing treatment is continued under the oxidizing atmosphere 5 seconds to 5 hours, temperature between 100 ° C and 400 ° C.
[0032] 所述氧化气氛包括： 氧气、 臭氧、 一氧化二氮、 水、 二氧化碳和以上物质的等 离子体。  [0032] The oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above substances.
[0033] 根据上述方法， 本发明还提供了一种显示器面板， 包括多组显示模块， 所述显 示模块包括上述所述的电路制造方法所制造的电路。  [0033] According to the above method, the present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the circuit manufactured by the circuit manufacturing method described above.
发明的有益效果  Advantageous effects of the invention
有益效果  Beneficial effect
[0034] 相对于传统结构的金属氧化物薄膜晶体管， 本发明中的薄膜晶体管具有以下优 点： 首先， 本方案直接通过退火处理在有源层中形成了源区、 漏区， 既保持了 和背沟道刻蚀结构一样的器件尺寸， 又实现了刻蚀阻挡层结构器件的高性能。 同吋兼顾了高性能和小尺寸的优点， 非常符合目前显示器的发展趋势， 特别是 在增强现实、 虚拟现实方面的发展应用。 其次， 退火处理减小了源漏区域的电 阻率， 进而降低了电极与有源层之间的寄生接触电阻， 显著提升了薄膜晶体管 的幵态性能。 同吋， 由于退火处理还保持甚至提高了沟道区的高电阻率， 从而 显著地降低了薄膜晶体管的关态电流。 更重要的是， 退火处理会在很大程度上 消除沟道区中的缺陷密度， 极大地提升器件的可靠性。 沟道区上方的第二绝缘 层保护薄膜晶体管的沟道区免受外界环境的影响， 器件的环境可靠性能得到进 一步加强。 本发明直接以电极覆盖部分有源层区域， 通过退火处理来降低电极 覆盖下的源区、 漏区的电阻率， 在省略了传统半导体工艺中的惨杂步骤和光刻 步骤， 节省了制备成本的同吋， 保证了源漏区域的低电阻率的稳定性。 因此， 此发明， 兼具高性能、 小尺寸、 高可靠性、 低成本等优点。 [0034] Compared with the metal oxide thin film transistor of the conventional structure, the thin film transistor of the present invention has the following advantages: First, the present scheme directly forms a source region and a drain region in the active layer by annealing treatment, which is both maintained and backed. The device size of the channel etch structure achieves high performance of the etch barrier structure device. The advantages of high performance and small size are taken into account, which is in line with the current development trend of displays, especially in the development of augmented reality and virtual reality. Secondly, the annealing treatment reduces the resistivity of the source and drain regions, thereby reducing the parasitic contact resistance between the electrode and the active layer, and significantly improving the germanium performance of the thin film transistor. At the same time, since the annealing treatment maintains or even increases the high resistivity of the channel region, the off-state current of the thin film transistor is remarkably lowered. More importantly, the annealing process will largely eliminate the defect density in the channel region and greatly improve the reliability of the device. Second insulation above the channel region The channel region of the layer protection thin film transistor is protected from the external environment, and the environmental reliability of the device can be further enhanced. The invention directly covers part of the active layer region with an electrode, and reduces the resistivity of the source region and the drain region under the electrode coverage by annealing treatment, and omits the complicated steps and the photolithography step in the conventional semiconductor process, thereby saving the preparation cost. The same kind ensures the low resistivity stability of the source and drain regions. Therefore, the invention has the advantages of high performance, small size, high reliability, low cost, and the like.
[0035] 本发明中形成耗尽型和增强型金属氧化物薄膜式薄膜晶体管， 构成集成电路的 方法是基于使用特定调节层金属氧化物沟道区， 利用退火处理调节沟道区的电 阻率， 进而调节薄膜晶体管的阈值电压。 因为只在部分薄膜晶体管沟道区上方 设置调节层， 器件结构本身不会有太大的改变， 此方法不仅大大简化了工艺、 极大降低了成本， 而且与现有金属氧化物薄膜晶体管的制备工艺完全兼容， 同 吋能够最大化地利用既有的研究成果， 更重要的是在最大程度地保持器件的高 性能， 有利于提高构成的电路的性能。 同吋， 通过此方法， 沟道区的电阻率的 调节不仅范围大、 而且精度高， 有利于精确调制阈值电压以进一步针对性地优 化电路性能。 覆盖的调节层还可以增强对沟道区保护， 使其进一步免受环境的 影响， 增强了器件的稳定性。 更进一步， 在显示器面板电路中， 可以利用显示 器面板中固有的中间绝缘层直接作为覆盖沟道区上的调节层或者中间绝缘层和 调节层一起图形化的方式免去额外的光刻步骤， 大大优化电路的制备工艺。 对附图的简要说明  [0035] In the present invention, a depletion type and enhancement type metal oxide thin film type thin film transistor is formed, and a method of forming an integrated circuit is based on using a specific adjustment layer metal oxide channel region, and an annealing treatment is used to adjust the resistivity of the channel region. The threshold voltage of the thin film transistor is further adjusted. Since the adjustment layer is disposed only above the channel region of a portion of the thin film transistor, the device structure itself does not change much, and the method not only greatly simplifies the process, greatly reduces the cost, but also prepares with the existing metal oxide thin film transistor. The process is fully compatible, and the same can maximize the use of existing research results, and more importantly, to maintain the high performance of the device to the greatest extent, and to improve the performance of the constructed circuit. At the same time, by this method, the adjustment of the resistivity of the channel region is not only large in range but also high in precision, which is advantageous for accurately modulating the threshold voltage to further optimize the circuit performance in a targeted manner. The overlying conditioning layer also enhances the protection of the channel region, further protecting it from the environment and enhancing device stability. Further, in the display panel circuit, the intermediate insulating layer inherent in the display panel can be directly used as an adjustment layer covering the channel region or the intermediate insulating layer and the adjustment layer are patterned together to avoid additional lithography steps. Optimize the preparation process of the circuit. Brief description of the drawing
附图说明  DRAWINGS
[0036] 图 1为本发明中电路结构的第一种实施例的剖视图。  1 is a cross-sectional view showing a first embodiment of a circuit structure in the present invention.
[0037] 图 2为本发明中电路结构的第二种实施例的剖视图。 2 is a cross-sectional view showing a second embodiment of the circuit structure of the present invention.
[0038] 图 3为本发明中电路结构的第三种实施例的剖视图。 3 is a cross-sectional view showing a third embodiment of the circuit structure in the present invention.
[0039] 图 4为本发明中电路结构的第四种实施例的剖视图。 4 is a cross-sectional view showing a fourth embodiment of the circuit structure of the present invention.
[0040] 图 5为本发明中电路结构的第五种实施例的剖视图。 5 is a cross-sectional view showing a fifth embodiment of the circuit structure of the present invention.
[0041] 图 6为本发明中显示面板结构的第一种实施例的剖视图。 6 is a cross-sectional view showing a first embodiment of a display panel structure in accordance with the present invention.
[0042] 图 7为本发明中显示面板结构的第二种实施例的剖视图。 7 is a cross-sectional view showing a second embodiment of the structure of the display panel of the present invention.
[0043] 图 8为本发明中显示面板结构的第三种实施例的剖视图。 本发明的实施方式 8 is a cross-sectional view showing a third embodiment of the structure of the display panel of the present invention. Embodiments of the invention
[0044] 下面结合附图及实施例详细描述本发明。 应当理解， 此处所描述的具体实施例 为非限制性示例实施例， 且附图示出的特征不是必须按比例绘制。 所给出的示 例仅旨在有利于解释本发明， 不应被理解为对本发明的限定。  [0044] The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are non-limiting exemplary embodiments, and the features of the drawings are not necessarily to scale. The examples are given only to facilitate the explanation of the invention and are not to be construed as limiting the invention.
[0045] 参照图 1， 图 1为本发明中由金属氧化物薄膜晶体管构成的电路的第一种实施例 的剖视图。 本实施例中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的有源层； 所述有源层与衬底 1之间设置有栅极叠层 3， 栅极叠层 3则包括栅极电极 31和设置 在栅极电极 31和所述有源层之间的栅极绝缘层 32; 所述有源层的不同区域上方 分别覆盖有第一绝缘层 6和第二绝缘层 7； 第二绝缘层 7上形成有深至所述有源层 的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出电极 4， 电极 4与所述 有源层的部分区域电相连； 电极 4上设置有第三绝缘层 8。 第三绝缘层 8的投影面 积和电极 4的投影面积完全重叠。  1, FIG. 1 is a cross-sectional view showing a first embodiment of a circuit composed of a metal oxide thin film transistor in the present invention. In this embodiment, the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting the electrode 4, the electrode 4 and the portion of the active layer from the through hole The regions are electrically connected; a third insulating layer 8 is disposed on the electrode 4. The projection area of the third insulating layer 8 and the projected area of the electrode 4 completely overlap.
[0046] 在本发明中， 所述的投影面积为具体实施例中的附图所示的垂直方向的投影面 积。  In the present invention, the projected area is the projection area in the vertical direction shown in the drawings in the specific embodiment.
[0047] 本发明中， 当绝缘层或导体层的厚度小于含氧元素的物质在该绝缘层或导体层 中的扩散长度吋， 含氧元素的物质能在退火处理中透过该绝缘层或导体层进入 金属氧化物有源层， 从而保持、 甚至提高金属氧化物的电阻率， 此吋该绝缘层 或导体层是透氧层； 当一个绝缘层或导体层的厚度大于含氧元素的物质在该绝 缘层中的扩散长度吋， 该绝缘层或导体层能阻挡含氧元素的物质， 从而降低金 属氧化物的电阻率， 此吋该绝缘层或导体层是不透氧层。  [0047] In the present invention, when the thickness of the insulating layer or the conductor layer is smaller than the diffusion length of the substance containing oxygen in the insulating layer or the conductor layer, the substance containing oxygen can pass through the insulating layer in the annealing process or The conductor layer enters the active layer of the metal oxide to maintain, or even increase, the resistivity of the metal oxide. The insulating layer or the conductor layer is an oxygen permeable layer; when an insulating layer or a conductor layer is thicker than the substance containing oxygen The diffusion length 吋 in the insulating layer, the insulating layer or the conductor layer can block the oxygen-containing material, thereby reducing the electrical resistivity of the metal oxide, and the insulating layer or the conductor layer is an oxygen-impermeable layer.
[0048] 所述含氧元素的物质包括： 氧气、 臭氧、 一氧化二氮、 水、 双氧水、 二氧化碳 和上述物质的等离子体。  [0048] The oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
[0049] 参照图 1， 衬底 1包括但不限于以下材料： 玻璃、 聚合物衬底、 柔性材料等。  Referring to FIG. 1, the substrate 1 includes, but is not limited to, the following materials: glass, polymer substrate, flexible material, and the like.
[0050] 参照图 1， 所述有源层包括以下材料中的一种或多种的组合： 氧化锌、 氮氧化 锌、 氧化锡、 氧化铟、 氧化镓、 氧化铜、 氧化铋、 氧化铟锌、 氧化锌锡、 氧化 铝锡、 氧化铟锡、 氧化铟镓锌、 氧化铟锡锌、 氧化铝铟锡锌、 硫化锌、 钛酸钡 、 钛酸锶或铌酸锂。  Referring to FIG. 1, the active layer includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, cerium oxide, indium zinc oxide , zinc tin oxide, aluminum oxide tin, indium tin oxide, indium gallium zinc oxide, indium tin zinc zinc, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
[0051] 参照图 1， 第二绝缘层 7、 电极 4和第三绝缘层 8共同组成第一调节层 5。 其中， 第一调节层 5的厚度大于所述含氧元素的物质在所述第一调节层 5中的扩散长度 ， 第一调节层 5能够阻挡所述含氧元素的物质， 因而第一调节层 5是不透氧层。 优选地， 第一调节层 5的厚度是所述含氧元素的物质在第一调节层 5中扩散长度 的 2至 100倍。 Referring to FIG. 1, the second insulating layer 7, the electrode 4, and the third insulating layer 8 collectively constitute the first conditioning layer 5. among them, The thickness of the first conditioning layer 5 is greater than the diffusion length of the oxygen-containing element in the first conditioning layer 5, and the first conditioning layer 5 is capable of blocking the oxygen-containing material, and thus the first conditioning layer 5 is Impervious to the oxygen layer. Preferably, the thickness of the first conditioning layer 5 is 2 to 100 times the diffusion length of the oxygen-containing substance in the first conditioning layer 5.
[0052] 参照图 1， 第一绝缘层 6的厚度小于所述含氧元素的物质在第一绝缘层 6中的扩 散长度， 所述含氧元素的物质在第一退火处理中能够透过第一绝缘层 6进入沟道 区 22， 因而第一绝缘层 6是透氧层。 第一绝缘层 6包含以下材料的一种或多种组 合： 氧化硅、 氮氧化硅； 进一步地， 所述氮氧化硅中氮化硅的比例小于 20%。 第 一绝缘层 6的厚度为 10至 3000纳米。 优选地， 第一绝缘层 6的厚度在 200纳米到 50 0纳米之间。  Referring to FIG. 1, the thickness of the first insulating layer 6 is smaller than the diffusion length of the substance containing the oxygen element in the first insulating layer 6, and the substance containing the oxygen element can pass through the first annealing process. An insulating layer 6 enters the channel region 22, and thus the first insulating layer 6 is an oxygen permeable layer. The first insulating layer 6 comprises one or more of the following materials: silicon oxide, silicon oxynitride; further, the proportion of silicon nitride in the silicon oxynitride is less than 20%. The first insulating layer 6 has a thickness of 10 to 3000 nm. Preferably, the thickness of the first insulating layer 6 is between 200 nm and 50 nm.
[0053] 参照图 1， 通过第一退火处理， 所述有源层在第一调节层 5覆盖下的区域的电阻 率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 23的电阻率有利于 降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜晶体管的幵态性能 。 与第一调节层 5的特性相反， 所述含氧元素的物质能够通过第一绝缘层 6进入 所述有源层， 因此所述有源层在非第一调节层 5覆盖下的区域的电阻率得到保持 甚至提高， 形成沟道区 22。 在薄膜晶体管工作过程中， 通过对栅极电极施加一 定的电压， 能够改变沟道区的电阻率， 进而控制通过沟道区的电流， 从而实现 薄膜晶体管器件的幵关。 薄膜晶体管的关态电流很大程度上取决于沟道区的电 阻率和缺陷密度， 更高的电阻率和更少的缺陷密度可以带来更低的关态电流和 更好的器件性能。 薄膜晶体管的幵态电流受限于源区、 漏区的电阻率， 更低的 源区、 漏区的电阻率有利于降低寄生电阻， 提高幵态电流。 在沟道区 22上方的 第一绝缘层 6还能提高沟道区 22的电阻率、 降低沟道区 22的缺陷密度， 从而改善 薄膜晶体管的关态特性， 并且第一绝缘层 6还能保护沟道区 22免受外界环境的影 响， 提高薄膜晶体管的稳定性和可靠性。  Referring to FIG. 1, the resistivity of the active layer under the coverage of the first adjustment layer 5 is lowered by the first annealing treatment to form the source region 21 and the drain region 23. The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. In contrast to the characteristics of the first conditioning layer 5, the oxygen-containing material can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in a region not covered by the first conditioning layer 5 The rate is maintained or even increased to form the channel region 22. During the operation of the thin film transistor, by applying a certain voltage to the gate electrode, the resistivity of the channel region can be changed, thereby controlling the current passing through the channel region, thereby achieving the switching of the thin film transistor device. The off-state current of a thin film transistor is highly dependent on the resistivity and defect density of the channel region. Higher resistivity and less defect density result in lower off-state current and better device performance. The zeta current of the thin film transistor is limited by the resistivity of the source and drain regions, and the lower resistivity of the source and drain regions is beneficial to reduce parasitic resistance and increase the zeta current. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected. The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0054] 参照图 1， 本实施例中， 第一退火处理降低源区 21和漏区 23的电阻率， 同吋保 持甚至提高沟道区 22的高电阻率。 所述有源层中的源区 21、 漏区 23和沟道区 22 相互连接。 由第一退火处理形成的源区 21、 漏区 23和沟道区 22之间的连接面无 需借助任何光刻对准工艺， 而自动对准于覆盖所述有源层的第一调节层 5的边界 ， 这类似于现有硅基场效应晶体管工艺中， 惨杂形成的源区、 漏区和沟道区的 连接面自动对准于栅极电极边界。 这种自对准通常都存在一定的偏差范围。 本 发明中， 源区、 漏区和沟道区的连接面自对准于第一调节层在有源层投影面积 之内的边界的铅垂面， 其对准的偏差小于有源层厚度的 100倍。 Referring to FIG. 1, in the present embodiment, the first annealing treatment reduces the resistivity of the source region 21 and the drain region 23 while maintaining or even increasing the high resistivity of the channel region 22. The source region 21, the drain region 23, and the channel region 22 in the active layer are connected to each other. The connection surface between the source region 21, the drain region 23, and the channel region 22 formed by the first annealing process is automatically aligned with the first adjustment layer 5 covering the active layer without any photolithography alignment process. Border This is similar to the existing silicon-based FET process, in which the connection regions of the source region, the drain region and the channel region are automatically aligned to the gate electrode boundary. This self-alignment usually has a certain range of deviation. In the present invention, the connection faces of the source region, the drain region and the channel region are self-aligned with the vertical plane of the boundary of the first adjustment layer within the projected area of the active layer, and the alignment deviation is smaller than the thickness of the active layer. 100 times.
[0055] 参照图 1， 本发明中， 所述第一退火处理包括利用热、 光、 激光、 微波进行加 热。 所述第一退火处理是在氧化气氛下， 持续 10秒至 10小吋， 温度大于 100°C。 在另一个方面， 第一退火处理的温度在 100°C和 600°C之间。 在另一个方面， 第一 退火处理的温度在 100°C和 500°C之间。 其中， 所述氧化气氛包括： 氧气、 臭氧、 一氧化二氮、 水、 二氧化碳和上述物质的等离子体。 Referring to FIG. 1, in the present invention, the first annealing treatment includes heating using heat, light, laser, or microwave. The first annealing treatment is carried out under an oxidizing atmosphere for 10 seconds to 10 hours and at a temperature greater than 100 °C. In another aspect, the temperature of the first annealing treatment is between 100 ° C and 600 ° C. In another aspect, the temperature of the first annealing treatment is between 100 ° C and 500 ° C. Wherein, the oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide and a plasma of the above substances.
[0056] 相对于传统的通过对源区和漏区进行惨杂的方式来降低源区和漏区的电阻率， 本发明中第一退火处理所得的源区和漏区的电阻率比惨杂所得的电阻率更低， 且电极保护下的源区和漏区的低电阻率更稳定。 相对于传统惨杂方式， 本发明 的工艺更简单、 成本也更低。 但本发明不限制惨杂， 有源层中可以惨入以下一 种或多种杂质： 氢、 氮、 氟、 硼、 磷、 砷、 硅、 铟、 铝或锑。 这不妨碍器件的 源区、 沟道区和漏区的形成。 也因此， 本发明和现有惨杂工艺完全兼容， 具有 高可扩展性。  [0056] Compared with the conventional method of reducing the source region and the drain region in a complicated manner to reduce the resistivity of the source region and the drain region, the resistivity ratio of the source region and the drain region obtained by the first annealing treatment in the present invention is complicated. The resulting resistivity is lower, and the low resistivity of the source and drain regions under electrode protection is more stable. The process of the present invention is simpler and less expensive than conventionally cumbersome methods. However, the present invention is not limited to the cumbersome one or more of the following impurities in the active layer: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminum or antimony. This does not prevent the formation of source, channel and drain regions of the device. Therefore, the present invention is fully compatible with the existing complicated processes and has high scalability.
[0057] 相对于传统薄膜晶体管的方法， 本发明中退火处理还保持、 甚至提高了沟道区 的高电阻率， 从而极大地降低了薄膜晶体管的关态电流， 远低于目前主流的 10-1 3安每微米， 甚至降低到极低的 10-18安每微米。 更重要的是， 退火还在很大程度 上消除了沟道区中的缺陷密度， 比如， 氧空位缺陷密度、 金属填隙缺陷密度等 ， 这些缺陷密度广泛地存在于金属氧化物中， 被认为是降低薄膜晶体管的性能 和可靠性的重要因素， 但在传统的器件结构中又很难彻底地消除。 因为消除了 这些缺陷密度， 本发明中所公幵的薄膜晶体管结构极大地增强了薄膜晶体管的 性能和长期可靠性。 比如， 金属氧化物薄膜晶体管的电流幵关比极大地提高、 甚至高于 1011 ; 常见的回滞效应引起的阈值电压漂移被抑制到 0.15 V之内； 栅极 电极上施加一定的电压吋所产生的阈值电压的漂移退化消除到 0 V左右。 其次， 沟道区上方覆盖的第一绝缘层不仅能够像刻蚀阻挡层一样完全保护沟道区免受 电极刻蚀带来的损害， 还能够很好地保护薄膜晶体管免受外界环境的影响、 增 强薄膜晶体管的环境稳定性。 比如， 在 80摄氏度、 80%相对湿度下保存 10个小吋 所引起的阈值电压漂移等性能退化的问题， 通过本发明中薄膜晶体管结构可以 得到大大改善。 Compared with the conventional thin film transistor method, the annealing process in the present invention maintains and even improves the high resistivity of the channel region, thereby greatly reducing the off-state current of the thin film transistor, which is far lower than the current mainstream 10- 1 3 amps per micron, even down to very low 10-18 amps per micron. More importantly, annealing also largely eliminates the defect density in the channel region, such as oxygen vacancy defect density, metal interstitial defect density, etc. These defect densities are widely present in metal oxides and are considered It is an important factor in reducing the performance and reliability of thin film transistors, but it is difficult to completely eliminate them in the conventional device structure. Since these defect densities are eliminated, the thin film transistor structure disclosed in the present invention greatly enhances the performance and long-term reliability of the thin film transistor. For example, the current-to-voltage ratio of metal oxide thin film transistors is greatly increased, even higher than 1011; the threshold voltage drift caused by the common hysteresis effect is suppressed to within 0.15 V; a certain voltage is applied to the gate electrode. The drift of the threshold voltage is degraded to around 0 V. Secondly, the first insulating layer covering the upper portion of the channel region can not only completely protect the channel region from the damage caused by the electrode etching like the etch barrier layer, but also protect the thin film transistor from the external environment. Increase Environmental stability of strong thin film transistors. For example, the problem of performance degradation such as threshold voltage drift caused by storing 10 small turns at 80 degrees Celsius and 80% relative humidity can be greatly improved by the structure of the thin film transistor of the present invention.
[0058] 总结来说， 本发明的新型薄膜晶体管相较于传统薄膜晶体管结构拥有诸多优点 ， 包括： 更简单的制造工艺， 更低的制备成本， 更高的工艺扩展性， 更优的器 件性能， 可靠性和环境稳定性。  [0058] In summary, the novel thin film transistor of the present invention has many advantages over the conventional thin film transistor structure, including: a simpler manufacturing process, lower fabrication cost, higher process scalability, and better device performance. , reliability and environmental stability.
[0059] 参照图 1， 电路结构包含衬底 1和多个位于衬底 1之上的由金属氧化物构成所述 有源层的薄膜晶体管。 所述薄膜晶体管结构中， 部分薄膜晶体管的整个沟道区 被第二绝缘调节层 91完全覆盖。 对所述薄膜晶体管结构进行第二退火处理， 当 沟道区 22在非第二绝缘调节层 91覆盖下吋， 所述含氧元素的物质能够透过第一 绝缘层 6进入沟道区 22， 进而保持、 甚至提高沟道区 22的电阻率， 从而形成增强 型沟道区 222; 相反地， 第二绝缘调节层 91能够为沟道区 22阻挡所述含氧元素的 物质， 进而降低沟道区 22的电阻率， 从而形成耗尽型沟道区 221， 耗尽型沟道区 221的电阻率小于增强型沟道区 222的电阻率。 优选地， 增强型沟道区 222的电阻 率为耗尽型沟道区 221的电阻率的 2至 100倍。 具有耗尽型沟道区 221的薄膜晶体 管为耗尽型薄膜晶体管 121， 具有增强型沟道区 222的薄膜晶体管为增强型薄膜 晶体管 122。 耗尽型薄膜晶体管 121和增强型薄膜晶体管 122相互通过导线、 电源 电极 111、 接地电极 112、 输入电极 113以及输出电极 114电连接形成电路。  Referring to FIG. 1, a circuit structure includes a substrate 1 and a plurality of thin film transistors formed of a metal oxide on the substrate 1 and constituting the active layer. In the thin film transistor structure, the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91. Performing a second annealing process on the thin film transistor structure. When the channel region 22 is covered by the non-second insulating adjustment layer 91, the oxygen-containing material can enter the channel region 22 through the first insulating layer 6. Further, the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel. The resistivity of the region 22, thereby forming the depletion channel region 221, the resistivity of the depletion channel region 221 being smaller than the resistivity of the enhancement channel region 222. Preferably, the enhancement channel region 222 has a resistivity of 2 to 100 times the resistivity of the depletion channel region 221. The thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121, and the thin film transistor having the enhancement channel region 222 is an enhancement thin film transistor 122. The depletion thin film transistor 121 and the enhancement type thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
[0060] 参照图 1， 第二绝缘调节层 91的厚度大于所述含氧元素的物质在第二绝缘调节 层 91中的扩散长度， 其能阻挡所述含氧元素的物质， 因而第二绝缘调节层 91为 不透氧层； 优选地， 第二绝缘调节层 91的厚度为所述含氧元素的物质在第二绝 缘调节层 91中扩散长度的 2至 100倍之间。 第二绝缘调节层 91包括以下材料中的 一种或多种的组合： 氮化硅、 氮氧化硅、 氧化铝、 氧化铪； 进一步地， 所述氮 氧化硅中的氮化硅比例大于 20%。 第二绝缘调节层 91的厚度为 10至 3000纳米。 优 选地， 第二绝缘调节层 91的厚度在 200纳米到 500纳米之间。  1, the thickness of the second insulation adjusting layer 91 is greater than the diffusion length of the oxygen-containing material in the second insulating adjustment layer 91, which can block the oxygen-containing substance, and thus the second insulation The adjustment layer 91 is an oxygen-impermeable layer; preferably, the thickness of the second insulation adjustment layer 91 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second insulation adjustment layer 91. The second insulation adjusting layer 91 includes a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is greater than 20% . The second insulating adjustment layer 91 has a thickness of 10 to 3000 nm. Preferably, the second insulating adjustment layer 91 has a thickness of between 200 nm and 500 nm.
[0061] 参照图 1， 本发明中， 所述第二退火处理包括利用热、 光、 激光、 微波进行加 热。 其中， 第二退火处理是在所述氧化气氛下进行， 持续吋间 5秒至 5小吋之间 ， 温度在 100°C和 500°C之间。 在另一个方面， 第二退火处理的温度在 100°C和 400 °C之间。 Referring to FIG. 1, in the present invention, the second annealing treatment includes heating using heat, light, laser, or microwave. Wherein, the second annealing treatment is performed under the oxidizing atmosphere for between 5 seconds and 5 hours, and between 100 ° C and 500 ° C. In another aspect, the temperature of the second annealing treatment is at 100 ° C and 400 Between °C.
[0062] 为了单片集成耗尽型薄膜晶体管和增强型薄膜晶体管、 进而实现电路， 传统的 做法是调节有源层的材料、 组分、 厚度和叠层。 比如， 构成耗尽型薄膜晶体管 的有源层的金属氧化物材料比构成增强型薄膜晶体管有源层的材料有更低的电 阻率。 再比如， 构成耗尽型薄膜晶体管有源层的金属氧化物比构成增强型薄膜 晶体管有源层的金属氧化物拥有更多的导电杂质， 如铟、 铝。 再比如， 构成耗 尽型薄膜晶体管有源层的金属氧化物的厚度大于构成增强型薄膜晶体管有源层 的金属氧化物的厚度。 再比如， 薄膜晶体管的有源层由多种金属氧化物的叠层 构成， 叠层结构中靠近栅极绝缘层的那层金属氧化物， 在耗尽型薄膜晶体管中 拥有比在增强型薄膜晶体管中更低的电阻率。 然而这些方法都需要对两种模式 的薄膜晶体管的有源层做分别的调整， 涉及到的材料调整和工艺调整都相对复 杂。 更重要的是， 所有针对有源层的材料、 组分、 厚度和叠层的调整都不仅仅 调节了器件的阈值电压、 也必然会严重地影响器件的其它性能指标， 因此很难 保证同吋制备出高性能的耗尽型薄膜晶体管和增强型薄膜晶体管。 更甚者， 在 不严重退化器件性能的前提下， 针对有源层的材料、 组分、 厚度和叠层的调整 必然都很有限， 很难做到对阈值电压的精确的较大范围的调节。  [0062] In order to monolithically integrate a depletion thin film transistor and an enhancement thin film transistor, and thereby implement a circuit, it is conventional to adjust the material, composition, thickness, and lamination of the active layer. For example, the metal oxide material constituting the active layer of the depletion thin film transistor has a lower resistivity than the material constituting the active layer of the enhancement type thin film transistor. As another example, the metal oxide constituting the active layer of the depletion thin film transistor has more conductive impurities such as indium or aluminum than the metal oxide constituting the active layer of the enhancement type thin film transistor. For another example, the thickness of the metal oxide constituting the active layer of the thin film transistor is larger than the thickness of the metal oxide constituting the active layer of the enhancement type thin film transistor. For example, the active layer of the thin film transistor is composed of a laminate of a plurality of metal oxides, and the metal oxide of the stacked structure close to the gate insulating layer has a specific thin film transistor in the depletion thin film transistor. Medium lower resistivity. However, these methods require separate adjustments of the active layers of the two modes of thin film transistors, and the material adjustment and process adjustment involved are relatively complicated. More importantly, all adjustments to the material, composition, thickness and stack of the active layer not only adjust the threshold voltage of the device, but also seriously affect other performance specifications of the device, so it is difficult to guarantee the same A high performance depletion thin film transistor and an enhancement thin film transistor are prepared. What's more, the adjustment of the material, composition, thickness and lamination of the active layer is bound to be limited without severely degrading the performance of the device. It is difficult to achieve a precise and wide range adjustment of the threshold voltage. .
[0063] 相比于传统的方法， 本实施例的方法是基于控制金属氧化物沟道区上的覆盖层 结构， 利用退火处理调节沟道区的电阻率， 进而调节薄膜晶体管的阈值电压。 因为只需要在部分沟道区上方设置调节层， 器件结构本身完全不变， 不仅工艺 大大简化、 成本极大降低， 而且与现有金属氧化物薄膜晶体管结构完全兼容、 能够最大化地利用既有的研究成果， 更重要的是器件的高性能得以最大程度地 保证。 同吋， 沟道区的电阻率的调节不仅范围大、 而且精度高， 有利于精确调 整阈值电压以针对性地优化电路性能。 其次， 调节层还可以增强对沟道区保护 ， 使其进一步免受环境的影响， 增强了器件的稳定性。  Compared with the conventional method, the method of the present embodiment is based on controlling the structure of the cap layer on the channel region of the metal oxide, and adjusting the resistivity of the channel region by annealing treatment, thereby adjusting the threshold voltage of the thin film transistor. Since only the adjustment layer is disposed above part of the channel region, the device structure itself is completely unchanged, which not only greatly simplifies the process, greatly reduces the cost, but also is fully compatible with the existing metal oxide thin film transistor structure, and can maximize the use of existing The research results, more importantly, the high performance of the device is guaranteed to the greatest extent. At the same time, the adjustment of the resistivity of the channel region is not only large in scope but also high in precision, which is advantageous for accurately adjusting the threshold voltage to specifically optimize circuit performance. Secondly, the adjustment layer can also enhance the protection of the channel region, further protecting it from the environment and enhancing the stability of the device.
[0064] 参照图 2， 图 2为本发明中由金属氧化物薄膜晶体管构成的电路的第二种实施例 的剖视图。 本实施例中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的有源层； 所述有源层与衬底 1之间设置有栅极叠层 3， 栅极叠层 3则包括栅极电极 31和设置 在栅极电极 31和所述有源层之间的栅极绝缘层 32; 所述有源层的不同区域上方 分别覆盖有第一绝缘层 6和不透氧第二绝缘层 71 ; 不透氧第二绝缘层 71上形成有 深至所述有源层的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出电极 4 ， 电极 4与所述有源层的部分区域电相连； 2, FIG. 2 is a cross-sectional view showing a second embodiment of a circuit composed of a metal oxide thin film transistor in the present invention. In this embodiment, the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; above different regions of the active layer The first insulating layer 6 and the oxygen-impermeable second insulating layer 71 are respectively covered; the second insulating layer 71 is formed with a through hole deep into the active layer, and a conductor is deposited in the through hole. Thereby extracting the electrode 4 from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer;
[0065] 参照图 2， 不透氧第二绝缘层 71的厚度大于所述含氧元素的物质在不透氧第二 绝缘层 71中的扩散长度， 其能阻挡所述含氧元素的物质， 不透氧第二绝缘层 71 为不透氧层； 优选地， 不透氧第二绝缘层 71的厚度为所述含氧元素的物质在不 透氧第二绝缘层 71中扩散长度的 2至 100倍之间。 不透氧第二绝缘层 71可以由以 下材料制成： 氮化硅、 氮氧化硅、 氧化铝、 氧化铪； 进一步地， 所述氮氧化硅 中的氮化硅比例大于 20%。 不透氧第二绝缘层 71的厚度为 10至 3000纳米。 优选地 ， 不透氧第二绝缘层 71的厚度在 200纳米到 500纳米之间。  Referring to FIG. 2, the thickness of the oxygen-impermeable second insulating layer 71 is greater than the diffusion length of the oxygen-containing element in the oxygen-impermeable second insulating layer 71, which can block the oxygen-containing substance, The oxygen impermeable second insulating layer 71 is an oxygen-impermeable layer; preferably, the thickness of the oxygen-impermeable second insulating layer 71 is 2 to the diffusion length of the oxygen-containing substance in the oxygen-impermeable second insulating layer 71 Between 100 times. The oxygen impermeable second insulating layer 71 may be made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is more than 20%. The oxygen impermeable second insulating layer 71 has a thickness of 10 to 3000 nm. Preferably, the thickness of the oxygen impermeable second insulating layer 71 is between 200 nm and 500 nm.
[0066] 参照图 2， 通过第一退火处理， 所述有源层在不透氧第二绝缘层 71覆盖下的区 域的电阻率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 23的电阻 率有利于降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜晶体管的 幵态性能。 与不透氧第二绝缘层 71的特性相反， 所述含氧元素的物质能够通过 第一绝缘层 6进入所述有源层， 因此所述有源层在非不透氧第二绝缘层 71覆盖下 的区域的电阻率保持甚至提高了， 形成沟道区 22。 在沟道区 22上方的第一绝缘 层 6还能提高沟道区 22的电阻率、 降低沟道区 22的缺陷密度， 从而改善薄膜晶体 管的关态特性， 并且第一绝缘层 6还能保护沟道区 22免受外界环境的影响， 提高 薄膜晶体管的稳定性和可靠性。  Referring to FIG. 2, by the first annealing treatment, the resistivity of the active layer under the coverage of the oxygen-impermeable second insulating layer 71 is lowered to form the source region 21 and the drain region 23. The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. In contrast to the characteristics of the oxygen-impermeable second insulating layer 71, the oxygen-containing element can enter the active layer through the first insulating layer 6, and thus the active layer is in the non-oxygen-free second insulating layer 71. The resistivity of the area underlying is maintained even increased, forming channel region 22. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected. The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0067] 参照图 2， 电路结构包含衬底 1和多个位于衬底 1之上的由金属氧化物构成所述 有源层的薄膜晶体管。 所述薄膜晶体管结构中， 部分薄膜晶体管的整个沟道区 被第二绝缘调节层 91完全覆盖。 对所述薄膜晶体管结构进行第二退火处理， 当 沟道区 22在非第二绝缘调节层 91覆盖下吋， 所述含氧元素的物质能够透过第一 绝缘层 6进入沟道区 22， 进而保持、 甚至提高沟道区 22的电阻率， 从而形成增强 型沟道区 222; 相反地， 第二绝缘调节层 91能够为沟道区 22阻挡所述含氧元素的 物质， 进而降低沟道区 22的电阻率， 从而形成耗尽型沟道区 221， 耗尽型沟道区 221的电阻率小于增强型沟道区 222的电阻率。 优选地， 增强型沟道区 222的电阻 率为耗尽型沟道区 221的电阻率的 2至 100倍。 具有耗尽型沟道区 221的薄膜晶体 管为耗尽型薄膜晶体管 121， 具有增强型沟道区 222的薄膜晶体管为增强型薄膜 晶体管 122。 耗尽型薄膜晶体管 121和增强型薄膜晶体管 122相互通过导线、 电源 电极 111、 接地电极 112、 输入电极 113以及输出电极 114电连接形成电路。 Referring to FIG. 2, the circuit structure includes a substrate 1 and a plurality of thin film transistors formed of a metal oxide on the substrate 1 over the substrate 1. In the thin film transistor structure, the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91. Performing a second annealing process on the thin film transistor structure. When the channel region 22 is covered by the non-second insulating adjustment layer 91, the oxygen-containing material can enter the channel region 22 through the first insulating layer 6. Further, the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel. The resistivity of the region 22, thereby forming the depletion channel region 221, the resistivity of the depletion channel region 221 being smaller than the resistivity of the enhancement channel region 222. Preferably, the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221. Thin film crystal having depletion channel region 221 The transistor is a depletion thin film transistor 121, and the thin film transistor having the enhancement type channel region 222 is an enhancement type thin film transistor 122. The depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
[0068] 参照图 3， 图 3为本发明中由金属氧化物薄膜晶体管构成的电路的第三种实施例 的剖视图。 本实施例中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的有源层； 所述有源层与衬底 1之间设置有栅极叠层 3， 栅极叠层 3则包括栅极电极 31和设置 在栅极电极 31和所述有源层之间的栅极绝缘层 32; 所述有源层的不同区域上方 分别覆盖有第一绝缘层 6和第二绝缘层 7； 第二绝缘层 7上形成有深至所述有源层 的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出电极 4， 电极 4与所述 有源层的部分区域电相连； 电极 4、 第一绝缘层 6和第二绝缘层 7上面设置有第三 绝缘层 8; 第三绝缘层 8的投影面积与第二绝缘层 7的投影面积完全重叠。  Referring to FIG. 3, FIG. 3 is a cross-sectional view showing a third embodiment of a circuit composed of a metal oxide thin film transistor in the present invention. In this embodiment, the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting the electrode 4, the electrode 4 and the portion of the active layer from the through hole The regions are electrically connected; the third insulating layer 8 is disposed on the electrode 4, the first insulating layer 6, and the second insulating layer 7; the projected area of the third insulating layer 8 completely overlaps the projected area of the second insulating layer 7.
[0069] 参照图 3， 第三绝缘层 8的厚度大于所述含氧元素的物质在第三绝缘层 8中的扩 散长度， 其能阻挡所述含氧元素的物质， 第三绝缘层 8为不透氧层； 优选地， 第 三绝缘层 8的厚度为所述含氧元素的物质在第三绝缘层 8中扩散长度的 2至 100倍 之间。 第三绝缘层 8可以由以下材料制成： 氮化硅、 氮氧化硅、 氧化铝、 氧化铪 ； 进一步地， 所述氮氧化硅中的氮化硅比例大于 20%。 第三绝缘层 8的厚度为 10 至 3000纳米。 优选地， 第三绝缘层 8的厚度在 200纳米到 500纳米之间。  Referring to FIG. 3, the thickness of the third insulating layer 8 is greater than the diffusion length of the oxygen-containing material in the third insulating layer 8, which can block the oxygen-containing material, and the third insulating layer 8 is Oxygen-impermeable layer; Preferably, the thickness of the third insulating layer 8 is between 2 and 100 times the diffusion length of the oxygen-containing material in the third insulating layer 8. The third insulating layer 8 may be made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is more than 20%. The third insulating layer 8 has a thickness of 10 to 3000 nm. Preferably, the thickness of the third insulating layer 8 is between 200 nm and 500 nm.
[0070] 参照图 3， 通过第一退火处理， 所述有源层在第三绝缘层 8覆盖下的区域的电阻 率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 23的电阻率有利于 降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜晶体管的幵态性能 。 与第三绝缘层 8的特性相反， 所述含氧元素的物质能够通过第一绝缘层 6进入 所述有源层， 因此所述有源层在非第三绝缘层 8覆盖下的区域的电阻率得到保持 甚至提高， 形成沟道区 22。 在沟道区 22上方的第一绝缘层 6还能提高沟道区 22的 电阻率、 降低沟道区 22的缺陷密度， 从而改善薄膜晶体管的关态特性， 并且第 一绝缘层 6还能保护沟道区 22免受外界环境的影响， 提高薄膜晶体管的稳定性和 可靠性。  Referring to FIG. 3, by the first annealing treatment, the resistivity of the active layer under the coverage of the third insulating layer 8 is lowered to form the source region 21 and the drain region 23. The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. In contrast to the characteristics of the third insulating layer 8, the oxygen-containing substance can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in a region covered by the non-third insulating layer 8 The rate is maintained or even increased to form the channel region 22. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected. The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0071] 参照图 3， 电路结构包含衬底 1和多个位于衬底 1之上的由金属氧化物构成所述 有源层的薄膜晶体管。 所述薄膜晶体管结构中， 部分薄膜晶体管的整个沟道区 被第二调节层 9完全覆盖。 对所述薄膜晶体管结构进行第二退火处理， 当沟道区 22在非第二调节层 9覆盖下吋， 所述含氧元素的物质能够透过第一绝缘层 6进入 沟道区 22， 进而保持、 甚至提高沟道区 22的电阻率， 从而形成增强型沟道区 222 ； 相反地， 第二调节层 9能够为沟道区 22阻挡所述含氧元素的物质， 进而降低沟 道区 22的电阻率， 从而形成耗尽型沟道区 221， 耗尽型沟道区 221的电阻率小于 增强型沟道区 222的电阻率。 优选地， 增强型沟道区 222的电阻率为耗尽型沟道 区 221的电阻率的 2至 100倍。 具有耗尽型沟道区 221的薄膜晶体管为耗尽型薄膜 晶体管 121， 具有增强型沟道区 222的薄膜晶体管为增强型薄膜晶体管 122。 耗尽 型薄膜晶体管 121和增强型薄膜晶体管 122相互通过导线、 电源电极 111、 接地电 极 112、 输入电极 113以及输出电极 114电连接形成电路。 Referring to FIG. 3, the circuit structure includes a substrate 1 and a plurality of thin film transistors on the substrate 1 which are composed of a metal oxide. In the thin film transistor structure, the entire channel region of a portion of the thin film transistor It is completely covered by the second adjustment layer 9. Performing a second annealing process on the thin film transistor structure. When the channel region 22 is covered by the non-second adjustment layer 9, the oxygen-containing material can pass through the first insulating layer 6 into the channel region 22, and further The resistivity of the channel region 22 is maintained, or even increased, to form the enhanced channel region 222; conversely, the second conditioning layer 9 can block the oxygen-containing species for the channel region 22, thereby reducing the channel region 22 The resistivity is such that a depletion channel region 221 is formed, and the resistivity of the depletion channel region 221 is smaller than that of the enhancement channel region 222. Preferably, the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221. The thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121, and the thin film transistor having the enhancement channel region 222 is the enhancement thin film transistor 122. The depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
[0072] 参照图 3， 第二调节层 9的厚度大于所述含氧元素的物质在第二调节层 9中的扩 散长度， 其能阻挡所述含氧元素的物质， 第二调节层 9为不透氧层； 优选地， 第 二调节层 9的厚度为所述含氧元素的物质在第二调节层 9中扩散长度的 2至 100倍 之间。 第二调节层 9包括以下材料中的一种或多种的组合： 氮化硅、 氮氧化硅、 氧化铝、 氧化铪、 硅、 砷化镓， 钛、 钼、 铝、 铜、 银、 金、 镍、 钨、 铬、 铪、 铂、 铁、 钛钨合金、 钼铝合金、 钼铜合金或铜铝合金， 其中所述氮氧化硅中的 氮化硅比例大于 20%。 第二调节层 9的厚度为 10至 3000纳米。 优选地， 第二调节 层 9的厚度在 200纳米到 500纳米之间。  [0072] Referring to FIG. 3, the thickness of the second conditioning layer 9 is greater than the diffusion length of the oxygen-containing material in the second conditioning layer 9, which blocks the oxygen-containing material, and the second conditioning layer 9 is Oxygen-impermeable layer; Preferably, the thickness of the second conditioning layer 9 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second conditioning layer 9. The second conditioning layer 9 comprises a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, silicon, gallium arsenide, titanium, molybdenum, aluminum, copper, silver, gold, Nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy, wherein the proportion of silicon nitride in the silicon oxynitride is greater than 20%. The second conditioning layer 9 has a thickness of 10 to 3000 nm. Preferably, the thickness of the second conditioning layer 9 is between 200 nm and 500 nm.
[0073] 参照图 4， 图 4为本发明中由金属氧化物薄膜晶体管构成的电路的第四种实施例 的剖视图。 本实施例中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的有源层； 所述有源层与衬底 1之间设置有栅极叠层 3， 栅极叠层 3则包括栅极电极 31和设置 在栅极电极 31和所述有源层之间的栅极绝缘层 32; 所述有源层的不同区域上方 分别覆盖有第一绝缘层 6和第二绝缘层 7； 第二绝缘层 7上形成有深至所述有源层 的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出不透氧电极 41， 不透 氧电极 41与所述有源层的部分区域电相连； 不透氧电极 41的投影面积与第二绝 缘层 7的投影面积完全重叠。  Referring to FIG. 4, FIG. 4 is a cross-sectional view showing a fourth embodiment of a circuit composed of a metal oxide thin film transistor in the present invention. In this embodiment, the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting an oxygen-impermeable electrode 41 from the through hole, and the oxygen-impermeable electrode 41 and the Portions of the active layer are electrically connected; the projected area of the oxygen-impermeable electrode 41 completely overlaps with the projected area of the second insulating layer 7.
[0074] 参照图 4， 不透氧电极 41的厚度大于所述含氧元素的物质在不透氧电极 41中的 扩散长度， 不透氧电极 41能阻挡所述含氧元素的物质， 因而不透氧电极 41是不 透氧层。 优选地， 不透氧电极 41的厚度为所述含氧元素的物质在不透氧电极 41 中扩散长度的 2至 100倍之间。 不透氧电极 41包括以下材料中的一种或多种的组 合： 钛、 钼、 铝、 铜、 银、 金、 镍、 钨、 铬、 铪、 铂、 铁、 钛钨合金、 钼铝合 金、 钼铜合金或铜铝合金。 不透氧电极 41的厚度为 10至 3000纳米。 优选地， 不 透氧电极 41的厚度在 200纳米到 500纳米之间。 Referring to FIG. 4, the thickness of the oxygen-impermeable electrode 41 is greater than the diffusion length of the oxygen-containing element in the oxygen-impermeable electrode 41, and the oxygen-impermeable electrode 41 can block the substance containing the oxygen element, and thus Oxygen permeable electrode 41 is not Oxygen permeable layer. Preferably, the thickness of the oxygen-impermeable electrode 41 is between 2 and 100 times the diffusion length of the oxygen-containing element in the oxygen-impermeable electrode 41. The oxygen-impermeable electrode 41 comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, niobium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, Molybdenum copper alloy or copper aluminum alloy. The oxygen-impermeable electrode 41 has a thickness of 10 to 3000 nm. Preferably, the thickness of the oxygen-impermeable electrode 41 is between 200 nm and 500 nm.
[0075] 参照图 4， 第一退火处理中， 所述有源层在不透氧电极 41覆盖下的区域的电阻 率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 23的电阻率有利于 降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜晶体管的幵态性能 。 与不透氧电极 41的特性相反， 所述含氧元素的物质能够通过第一绝缘层 6进入 所述有源层， 因此所述有源层在非不透氧电极 41覆盖下的区域的电阻率得到了 保持甚至提高， 形成沟道区 22。 在沟道区 22上方的第一绝缘层 6还能提高沟道区 22的电阻率、 降低沟道区 22的缺陷密度， 从而改善薄膜晶体管的关态特性， 并 且第一绝缘层 6还能保护沟道区 22免受外界环境的影响， 提高薄膜晶体管的稳定 性和可靠性。 Referring to FIG. 4, in the first annealing process, the resistivity of the active layer under the area covered by the oxygen-impermeable electrode 41 is lowered to form the source region 21 and the drain region 23. The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. In contrast to the characteristics of the oxygen-impermeable electrode 41, the oxygen-containing substance can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in the region covered by the non-oxygen-impermeable electrode 41 The rate is maintained or even increased to form the channel region 22. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected. The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0076] 参照图 4， 电路结构包含衬底 1和多个位于衬底 1之上的由金属氧化物构成所述 有源层的薄膜晶体管。 所述薄膜晶体管结构中， 部分薄膜晶体管的整个沟道区 被第二绝缘调节层 91完全覆盖。 对所述薄膜晶体管结构进行第二退火处理， 当 沟道区 22在非第二绝缘调节层 91覆盖下吋， 所述含氧元素的物质能够透过第一 绝缘层 6进入沟道区 22， 进而保持、 甚至提高沟道区 22的电阻率， 从而形成增强 型沟道区 222; 相反地， 第二绝缘调节层 91能够为沟道区 22阻挡所述含氧元素的 物质， 进而降低沟道区 22的电阻率， 从而形成耗尽型沟道区 221， 耗尽型沟道区 221的电阻率小于增强型沟道区 222的电阻率。 优选地， 增强型沟道区 222的电阻 率为耗尽型沟道区 221的电阻率的 2至 100倍。 具有耗尽型沟道区 221的薄膜晶体 管为耗尽型薄膜晶体管 121， 具有增强型沟道区 222的薄膜晶体管为增强型薄膜 晶体管 122。 耗尽型薄膜晶体管 121和增强型薄膜晶体管 122相互通过导线、 电源 电极 111、 接地电极 112、 输入电极 113以及输出电极 114电连接形成电路。  Referring to FIG. 4, the circuit structure includes a substrate 1 and a plurality of thin film transistors on the substrate 1 which are composed of a metal oxide to form the active layer. In the thin film transistor structure, the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91. Performing a second annealing process on the thin film transistor structure. When the channel region 22 is covered by the non-second insulating adjustment layer 91, the oxygen-containing material can enter the channel region 22 through the first insulating layer 6. Further, the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel. The resistivity of the region 22, thereby forming the depletion channel region 221, the resistivity of the depletion channel region 221 being smaller than the resistivity of the enhancement channel region 222. Preferably, the enhancement channel region 222 has a resistivity of 2 to 100 times the resistivity of the depletion channel region 221. The thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121, and the thin film transistor having the enhancement channel region 222 is an enhancement thin film transistor 122. The depletion thin film transistor 121 and the enhancement type thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
[0077] 参照图 5， 图 5为本发明中由金属氧化物薄膜晶体管构成的电路的第五种实施例 的剖视图。 本实施例中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的有源层； 所述有源层之上之间设置有透氧栅极电极 311和设置在透氧栅极电极 311和所述 有源层之间的透氧栅极绝缘层 321 ; 所述有源层的不同区域上方分别覆盖有第一 绝缘层 6和第二绝缘层 7; 第二绝缘层 7和透氧栅极绝缘层 321上形成有深至所述 有源层的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出电极 4， 电极 4 与所述有源层的部分区域电相连。 电极 4之上还覆盖有第三绝缘层 8; 第三绝缘 层 8的投影面积和第二绝缘层 7的投影面积完全重叠。 Referring to FIG. 5, FIG. 5 is a cross-sectional view showing a fifth embodiment of a circuit composed of a metal oxide thin film transistor in the present invention. In this embodiment, the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; An oxygen permeable gate electrode 311 and an oxygen permeable gate insulating layer 321 disposed between the oxygen permeable gate electrode 311 and the active layer are disposed between the active layers; the active layer is different A first insulating layer 6 and a second insulating layer 7 are respectively covered on the upper portion of the region; a through hole deep to the active layer is formed on the second insulating layer 7 and the oxygen permeable gate insulating layer 321 A conductor is accumulated so that the electrode 4 is drawn from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer. The third insulating layer 8 is also covered on the electrode 4; the projected area of the third insulating layer 8 and the projected area of the second insulating layer 7 completely overlap.
[0078] 参照图 5， 透氧栅极电极 311的厚度小于所述含氧元素的物质在透氧栅极电极 31 1中的扩散长度， 所述含氧元素的物质在第一退火处理中能够透过透氧栅极电极 311进入沟道区 22， 因此透氧栅极电极 311是透氧层。 透氧栅极电极 311包含以下 材料的一种或多种组合： 氧化锌、 氧化铟锡、 氧化铝锌、 氧化铟锌。 透氧栅极 电极 311的厚度为 10至 3000纳米。 优选地， 透氧栅极电极 311的厚度在 200纳米到 500纳米之间。 Referring to FIG. 5, the thickness of the oxygen permeable gate electrode 311 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate electrode 31 1 , and the oxygen-containing substance can be in the first annealing process. The oxygen permeable gate electrode 311 enters the channel region 22, and thus the oxygen permeable gate electrode 311 is an oxygen permeable layer. The oxygen permeable gate electrode 311 comprises one or more combinations of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium zinc oxide. The oxygen permeable gate electrode 311 has a thickness of 10 to 3000 nm. Preferably, the oxygen permeable gate electrode 311 has a thickness between 200 nm and 500 nm.
[0079] 参照图 5， 透氧栅极绝缘层 321的厚度小于所述含氧元素的物质在透氧栅极绝缘 层 321中的扩散长度， 所述含氧元素的物质在第一退火处理中能够透过透氧栅极 绝缘层 321进入沟道区 22， 因此透氧栅极绝缘层 321是透氧层。 透氧栅极绝缘层 3 21包含以下材料的一种或多种组合： 氧化硅、 氮氧化硅； 所述氮氧化硅中氮化 硅的比例小于 20%。 透氧栅极绝缘层 321的厚度为 10至 3000纳米。 优选地， 透氧 栅极绝缘层 321的厚度在 200纳米到 500纳米之间。  Referring to FIG. 5, the thickness of the oxygen permeable gate insulating layer 321 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate insulating layer 321, and the oxygen-containing substance is in the first annealing process. The channel region 22 can be accessed through the oxygen permeable gate insulating layer 321, so that the oxygen permeable gate insulating layer 321 is an oxygen permeable layer. The oxygen permeable gate insulating layer 321 includes one or more combinations of the following materials: silicon oxide, silicon oxynitride; and the proportion of silicon nitride in the silicon oxynitride is less than 20%. The oxygen permeable gate insulating layer 321 has a thickness of 10 to 3000 nm. Preferably, the oxygen permeable gate insulating layer 321 has a thickness of between 200 nm and 500 nm.
[0080] 参照图 5， 通过第一退火处理， 所述有源层在第三绝缘层 8覆盖下的区域的电阻 率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 23的电阻率有利于 降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜晶体管的幵态性能 。 与第三绝缘层 8的特性相反， 所述含氧元素的物质能够通过第一绝缘层 6、 透 氧栅极绝缘层 321和透氧栅极电极 311进入所述有源层， 因此所述有源层在非第 三绝缘层 8覆盖下的区域的电阻率得到保持甚至提高， 形成沟道区 22。 在沟道区 22上方的第一绝缘层 6还能提高沟道区 22的电阻率、 降低沟道区 22的缺陷密度， 从而改善薄膜晶体管的关态特性， 并且第一绝缘层 6还能保护沟道区 22免受外界 环境的影响， 提高薄膜晶体管的稳定性和可靠性。  Referring to FIG. 5, by the first annealing treatment, the resistivity of the active layer under the coverage of the third insulating layer 8 is lowered to form the source region 21 and the drain region 23. The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. In contrast to the characteristics of the third insulating layer 8, the oxygen-containing substance can enter the active layer through the first insulating layer 6, the oxygen-permeable gate insulating layer 321, and the oxygen-permeable gate electrode 311, so The resistivity of the region of the source layer covered by the non-third insulating layer 8 is maintained or even increased to form the channel region 22. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected. The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0081] 参照图 5， 电路结构包含衬底 1和多个位于衬底 1之上的由金属氧化物构成所述 有源层的薄膜晶体管。 所述薄膜晶体管结构中， 部分薄膜晶体管的整个沟道区 被第二调节层 9完全覆盖。 对所述薄膜晶体管结构进行第二退火处理， 当沟道区 22在非第二调节层 9覆盖下吋， 所述含氧元素的物质能够透过第一绝缘层 6进入 沟道区 22， 进而保持、 甚至提高沟道区 22的电阻率， 从而形成增强型沟道区 222 ； 相反地， 第二调节层 9能够为沟道区 22阻挡所述含氧元素的物质， 进而降低沟 道区 22的电阻率， 从而形成耗尽型沟道区 221， 耗尽型沟道区 221的电阻率小于 增强型沟道区 222的电阻率。 优选地， 增强型沟道区 222的电阻率为耗尽型沟道 区 221的电阻率的 2至 100倍。 具有耗尽型沟道区 221的薄膜晶体管为耗尽型薄膜 晶体管 121， 具有增强型沟道区 222的薄膜晶体管为增强型薄膜晶体管 122。 耗尽 型薄膜晶体管 121和增强型薄膜晶体管 122相互通过导线、 电源电极 111、 接地电 极 112、 输入电极 113以及输出电极 114电连接形成电路 [0081] Referring to FIG. 5, the circuit structure includes a substrate 1 and a plurality of the metal oxide oxides on the substrate 1 Thin film transistor of the active layer. In the thin film transistor structure, the entire channel region of a portion of the thin film transistor is completely covered by the second adjustment layer 9. Performing a second annealing process on the thin film transistor structure. When the channel region 22 is covered by the non-second adjustment layer 9, the oxygen-containing material can pass through the first insulating layer 6 into the channel region 22, and further The resistivity of the channel region 22 is maintained, or even increased, to form the enhanced channel region 222; conversely, the second conditioning layer 9 can block the oxygen-containing species for the channel region 22, thereby reducing the channel region 22 The resistivity is such that a depletion channel region 221 is formed, and the resistivity of the depletion channel region 221 is smaller than that of the enhancement channel region 222. Preferably, the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221. The thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121, and the thin film transistor having the enhancement channel region 222 is the enhancement thin film transistor 122. The depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power supply electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form a circuit.
[0082] 参照图 6， 图 6为本发明中显示面板结构的第一种实施例的剖视图。 显示器面板 由多个显示模块组成， 显示模块中包括： 设置于衬底 1之上的薄膜晶体管； 设置 于所述薄膜晶体管之上的中间绝缘层 13; 第二绝缘调节层 91和中间绝缘层 13上 形成有深至电极 4的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出像素 电极 14， 像素电极 14与所述薄膜晶体管相电连接； 中间绝缘层 13和像素电极 14 之上设置光电材料 15和公共电极 16。 其中， 光电材料 15包括但不限于： 液晶、 发光二极管、 有机发光二极管、 量子点发光二极管。 其中， 本实施例中显示面 板采用图 2所示电路结构形成像素电路和驱动电路。  6, FIG. 6 is a cross-sectional view showing a first embodiment of a display panel structure in accordance with the present invention. The display panel is composed of a plurality of display modules, and the display module includes: a thin film transistor disposed on the substrate 1; an intermediate insulating layer 13 disposed on the thin film transistor; a second insulating adjustment layer 91 and an intermediate insulating layer 13 a through hole deep in the electrode 4 is formed, and a conductor is deposited in the through hole, thereby extracting the pixel electrode 14 from the through hole, and the pixel electrode 14 is electrically connected to the thin film transistor; the intermediate insulating layer 13 and A photovoltaic material 15 and a common electrode 16 are disposed over the pixel electrode 14. The photoelectric material 15 includes, but is not limited to, a liquid crystal, a light emitting diode, an organic light emitting diode, and a quantum dot light emitting diode. Wherein, in the display panel of the embodiment, the circuit structure shown in FIG. 2 is used to form the pixel circuit and the driving circuit.
[0083] 参照图 7， 图 7为本发明中显示面板结构的第二种实施例的剖视图。 显示器面板 由多个显示模块组成， 显示模块中包括： 设置于衬底 1之上的薄膜晶体管； 设置 于所述薄膜晶体管之上的中间绝缘层 13; 第二绝缘调节层 91和中间绝缘层 13上 形成有深至电极 4的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出像素 电极 14， 像素电极 14与所述薄膜晶体管相电连接； 中间绝缘层 13和像素电极 14 之上设置光电材料 15和公共电极 16。 其中， 本实施例中显示面板类似图 2所示电 路结构形成像素电路和驱动电路。 本实施例和图 6所示实施例的区别在于， 第二 绝缘调节层 91在增强型沟道区 222上的部分无需通过单独的光刻步骤来移除， 而 是和中间绝缘层 13的光刻一起完成。 因而， 相对于图 6所示实施例， 本实施例节 省了一道光刻步骤， 极大地简化了工艺、 降低了成本。 第二绝缘调节层 91的投 影面积与中间绝缘层 13的投影面积完全重叠。 Referring to FIG. 7, FIG. 7 is a cross-sectional view showing a second embodiment of the structure of the display panel of the present invention. The display panel is composed of a plurality of display modules, and the display module includes: a thin film transistor disposed on the substrate 1; an intermediate insulating layer 13 disposed on the thin film transistor; a second insulating adjustment layer 91 and an intermediate insulating layer 13 a through hole deep in the electrode 4 is formed, and a conductor is deposited in the through hole, thereby extracting the pixel electrode 14 from the through hole, and the pixel electrode 14 is electrically connected to the thin film transistor; the intermediate insulating layer 13 and A photovoltaic material 15 and a common electrode 16 are disposed over the pixel electrode 14. The display panel in this embodiment is similar to the circuit structure shown in FIG. 2 to form a pixel circuit and a driving circuit. The difference between this embodiment and the embodiment shown in FIG. 6 is that the portion of the second insulating adjustment layer 91 on the enhancement type channel region 222 does not need to be removed by a separate photolithography step, but the light of the intermediate insulating layer 13 Engraved together. Thus, with respect to the embodiment shown in Figure 6, this embodiment section A lithography step is saved, which greatly simplifies the process and reduces costs. The projected area of the second insulating adjustment layer 91 completely overlaps with the projected area of the intermediate insulating layer 13.
[0084] 参照图 8， 图 8为本发明中显示面板结构的第三种实施例的剖视图。 本实施例的 显示模块类似于图 7所示显示模块。 区别在于， 本实施例的显示模块中没有中间 绝缘层 13， 中间绝缘层 13的功能由第二绝缘调节层 91兼顾承担。 因而， 相对于 图 6所示实施例， 本实施例也同样节省了一道光刻步骤， 极大地简化了工艺、 降 低了成本。  Referring to FIG. 8, FIG. 8 is a cross-sectional view showing a third embodiment of the display panel structure of the present invention. The display module of this embodiment is similar to the display module shown in FIG. The difference is that the display module of the present embodiment has no intermediate insulating layer 13, and the function of the intermediate insulating layer 13 is taken care of by the second insulating regulating layer 91. Thus, with respect to the embodiment shown in Fig. 6, this embodiment also saves a lithography step, greatly simplifying the process and reducing the cost.
[0085] 最后应当说明的是， 以上实施例仅为本发明的较佳实施例而已， 而非对本发明 保护范围的限制， 本领域的普通技术人员应当理解， 凡在本发明的精神和原则 之内所作的任何修改、 等同替换或改进等， 均应包含在本发明的保护范围之内  It should be noted that the above embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Those skilled in the art should understand that the spirit and principles of the present invention. Any modifications, equivalent substitutions or improvements made therein shall be included in the scope of protection of the present invention.

Claims

权利要求书 Claim
[权利要求 1] 一种电路结构， 包含多个薄膜晶体管， 其特征在于， 所述薄膜晶体管 结构包括： 衬底和位于所述衬底之上的由金属氧化物构成的有源层； 所述有源层与栅极叠层相毗邻， 所述有源层的部分区域上覆盖有第一 调节层， 所述第一调节层的厚度大于含氧元素的物质在所述第一调节 层中的扩散长度； 所述有源层在所述第一调节层覆盖下的区域分别形 成源区、 漏区， 在非所述第一调节层覆盖下的区域形成沟道区； 所述 源区、 所述漏区与所述沟道区相互连接， 且分别位于所述沟道区的两 端， 所述沟道区与所述栅极叠层相毗邻； 所述源区、 所述漏区和所述 沟道区的连接面自对准于所述第一调节层在所述有源层投影面积之内 的边界的铅垂面； 所述源区、 所述漏区的电阻率小于所述沟道区的电 阻率； 部分薄膜晶体管的整个沟道区上方设置有第二调节层， 在所述 第二调节层覆盖下的形成耗尽型沟道区， 在非所述第二调节层覆盖下 的形成增强型沟道区， 所述耗尽型沟道区的电阻率小于所述增强型沟 道区的电阻率； 所述第二调节层的厚度大于所述含氧元素的物质在所 述第二调节层中的扩散长度； 具有所述耗尽型沟道区的薄膜晶体管为 耗尽型薄膜晶体管， 具有所述增强型沟道区的薄膜晶体管为增强型薄 膜晶体管； 所述耗尽型薄膜晶体管和所述增强型薄膜晶体管相互电连 接构成电路。  [Claim 1] A circuit structure comprising a plurality of thin film transistors, wherein the thin film transistor structure comprises: a substrate and an active layer made of a metal oxide over the substrate; The active layer is adjacent to the gate stack, and a portion of the active layer is covered with a first adjustment layer, and the first adjustment layer has a thickness greater than that of the oxygen-containing material in the first adjustment layer. Diffusion length; a region of the active layer covered by the first adjustment layer respectively forms a source region and a drain region, and a region not covered by the first adjustment layer forms a channel region; the source region and the The drain region and the channel region are interconnected, and are respectively located at two ends of the channel region, the channel region is adjacent to the gate stack; the source region, the drain region, and the a connection surface of the channel region is self-aligned with a vertical surface of a boundary of the first adjustment layer within a projected area of the active layer; and a resistivity of the source region and the drain region is smaller than the trench Resistivity of the track region; above the entire channel region of a portion of the thin film transistor a second adjustment layer is disposed, a depletion-type channel region is formed under the cover of the second adjustment layer, and an enhancement channel region is formed under the cover of the second adjustment layer, the depletion channel The resistivity of the region is less than the resistivity of the enhanced channel region; the thickness of the second conditioning layer is greater than the diffusion length of the oxygen-containing material in the second conditioning layer; The thin film transistor of the channel region is a depletion thin film transistor, and the thin film transistor having the enhanced channel region is an enhancement thin film transistor; the depletion thin film transistor and the enhancement thin film transistor are electrically connected to each other to constitute a circuit.
[权利要求 2] 根据权利要求 1所述的电路结构， 其特征在于， 所述源区、 所述漏区 与所述沟道区的连接面和所述第一调节层在所述有源层投影面积之内 的边界的铅垂面的间距小于所述有源层厚度的 100倍。  [Claim 2] The circuit structure according to claim 1, wherein the source region, a connection surface of the drain region and the channel region, and the first adjustment layer are in the active layer The pitch of the vertical plane of the boundary within the projected area is less than 100 times the thickness of the active layer.
[权利要求 3] 根据权利要求 1所述的电路结构， 其特征在于， 所述沟道区与所述源 区、 所述漏区的电阻率比值大于 1000倍； 所述增强型沟道区的电阻率 为所述耗尽型沟道区的电阻率的 2至 100倍。  [Claim 3] The circuit structure according to claim 1, wherein a ratio of resistivity of the channel region to the source region and the drain region is greater than 1000 times; The resistivity is 2 to 100 times the resistivity of the depletion mode channel region.
[权利要求 4] 根据权利要求 1所述的电路结构， 其特征在于， 所述有源层包括以下 材料中的一种或多种的组合： 氧化锌、 氮氧化锌、 氧化锡、 氧化铟、 氧化镓、 氧化铜、 氧化铋、 氧化铟锌、 氧化锌锡、 氧化铝锡、 氧化铟 锡、 氧化铟镓锌、 氧化铟锡锌、 氧化铝铟锡锌、 硫化锌、 钛酸钡、 钛 酸锶或铌酸锂。 [Claim 4] The circuit structure according to claim 1, wherein the active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, Gallium oxide, copper oxide, cerium oxide, indium zinc oxide, zinc tin oxide, aluminum oxide tin, indium oxide Tin, indium gallium zinc oxide, indium tin zinc oxide, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
根据权利要求 1所述的电路结构， 其特征在于， 所述第一调节层的厚 度为所述含氧元素的物质在所述第一调节层中的扩散长度的 2至 100倍 之间， 所述第二调节层的厚度为所述含氧元素的物质在所述第二调节 层中的扩散长度的 2至 100倍之间。 The circuit structure according to claim 1, wherein the thickness of the first adjustment layer is between 2 and 100 times the diffusion length of the oxygen-containing substance in the first adjustment layer. The thickness of the second conditioning layer is between 2 and 100 times the diffusion length of the oxygen-containing material in the second conditioning layer.
根据权利要求 1所述的电路结构， 其特征在于， 所述第一调节层和所 述第二调节层包括以下材料中的一种或多种的组合： 氮化硅、 氮氧化 硅、 氧化铝、 氧化铪、 硅、 砷化镓， 钛、 钼、 铝、 铜、 银、 金、 镍、 钨、 铬、 铪、 铂、 铁、 钛钨合金、 钼铝合金、 钼铜合金或铜铝合金； 进一步地， 所述氮氧化硅中的氮化硅比例大于 20%。 The circuit structure according to claim 1, wherein said first conditioning layer and said second conditioning layer comprise a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide , yttria, silicon, gallium arsenide, titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, niobium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy; Further, the proportion of silicon nitride in the silicon oxynitride is greater than 20%.
根据权利要求 6所述的电路结构， 其特征在于， 所述第一调节层的厚 度为 10至 3000纳米， 所述第二调节层的厚度为 10至 3000纳米。 The circuit structure according to claim 6, wherein the first adjustment layer has a thickness of 10 to 3000 nm, and the second adjustment layer has a thickness of 10 to 3000 nm.
根据权利要求 1所述的电路结构， 其特征在于， 所述栅极叠层设置在 所述有源层与所述衬底之间。 The circuit structure according to claim 1, wherein said gate stack is disposed between said active layer and said substrate.
根据权利要求 1所述的电路结构， 其特征在于， 所述有源层设置在所 述栅极叠层和所述衬底之间。 The circuit structure according to claim 1, wherein said active layer is disposed between said gate stack and said substrate.
根据权利要求 9所述的电路结构， 其特征在于， 所述栅极叠层包括栅 极电极和栅极绝缘层， 所述栅极电极的厚度小于所述含氧元素的物质 在所述栅极电极中的扩散长度， 所述栅极绝缘层的厚度小于所述含氧 元素的物质在所述栅极绝缘层中的扩散长度。 The circuit structure according to claim 9, wherein the gate stack comprises a gate electrode and a gate insulating layer, and a thickness of the gate electrode is smaller than a substance of the oxygen-containing element at the gate a diffusion length in the electrode, the thickness of the gate insulating layer being smaller than a diffusion length of the oxygen-containing material in the gate insulating layer.
根据权利要求 10所述的电路结构， 其特征在于， 所述栅极电极包含以 下材料中的一种或多种的组合： 氧化锌、 氧化铟锡、 氧化铝锌、 氧化 铟铝、 氧化铟锌； 所述栅极绝缘层包含以下材料中的一种或多种的组 合： 氧化硅、 氮氧化硅， 其中所述氮氧化硅中氮化硅的比例小于 20% 根据权利要求 10所述的电路结构， 其特征在于， 所述栅极电极的厚度 为 10至 3000纳米； 所述栅极绝缘层的厚度为 10至 3000纳米。 [权利要求 13] 根据权利要求 1所述的电路结构， 其特征在于， 所述含氧元素的物质 包括： 氧气、 臭氧、 一氧化二氮、 水、 双氧水、 二氧化碳和以上物质 的等离子体。 The circuit structure according to claim 10, wherein the gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide, indium zinc oxide The gate insulating layer comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%, the circuit according to claim 10 The structure is characterized in that the gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm. [Claim 13] The circuit structure according to claim 1, wherein the oxygen-containing substance comprises: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
[权利要求 14] 一种显示器面板， 其特征在于， 包括多组显示模块， 所述显示模块包 括权利要求 1至 13任一所述的电路结构。  [Claim 14] A display panel comprising a plurality of sets of display modules, the display module comprising the circuit structure of any one of claims 1 to 13.
[权利要求 15] —种薄膜晶体管电路制造方法， 其特征在于， 包括： [Claim 15] A method of manufacturing a thin film transistor circuit, comprising:
准备一个衬底；  Preparing a substrate;
在所述衬底之上设置有源层和与所述有源层相毗邻的栅极叠层， 所述 有源层由金属氧化物构成；  An active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
在所述有源层的部分区域上设置第一调节层， 使所述第一调节层的厚 度大于含氧元素的物质在所述第一调节层中的扩散长度；  Providing a first adjustment layer on a partial region of the active layer such that a thickness of the first adjustment layer is greater than a diffusion length of a substance containing an oxygen element in the first adjustment layer;
进行第一退火处理， 使所述有源层在所述第一调节层覆盖下的区域分 别第一退火处理形成源区、 漏区， 在非所述第一调节层覆盖下的区域 第一退火处理形成沟道区， 所述沟道区与所述栅极叠层相毗邻， 所述 源区、 所述漏区与所述沟道区相互连接， 且分别位于所述沟道区的两 端， 所述源区、 所述漏区和所述沟道区之间由所述第一退火处理形成 的连接面自对准于所述第一调节层在所述有源层投影面积之内的边界 的铅垂面， 所述源区、 所述漏区的电阻率小于所述沟道区的电阻率； 在部分所述薄膜晶体管的整个沟道区之上设置第二调节层， 使所述第 二调节层的厚度大于所述含氧元素的物质在所述调节层中的扩散长度 进行第二退火处理， 使在所述调节层覆盖下的沟道区第二退火处理形 成耗尽型沟道区， 在非所述第二调节层覆盖下的沟道区第二退火处理 形成增强型沟道区， 所述耗尽型沟道区的电阻率小于所述增强型沟道 区的电阻率；  Performing a first annealing process, wherein the active layer is first annealed to form a source region and a drain region in a region covered by the first conditioning layer, and a first annealing is performed in a region not covered by the first conditioning layer Forming a channel region, the channel region is adjacent to the gate stack, the source region, the drain region and the channel region are connected to each other, and are respectively located at both ends of the channel region a connection surface formed by the first annealing process between the source region, the drain region, and the channel region is self-aligned with the first adjustment layer within a projected area of the active layer a vertical plane of the boundary, a resistivity of the source region and the drain region is smaller than a resistivity of the channel region; and a second adjustment layer is disposed over a portion of the entire channel region of the thin film transistor, a thickness of the second conditioning layer is greater than a diffusion length of the oxygen-containing material in the conditioning layer, and a second annealing treatment is performed to form a depletion trench in the second annealing process of the channel region covered by the conditioning layer Channel region, in a channel region not covered by the second adjustment layer Annealing the channel region formed in an enhanced resistance of the depletion-type channel region is smaller than the resistivity enhancement type channel region;
具有所述耗尽型沟道区的薄膜晶体管为耗尽型薄膜晶体管， 具有所述 增强型沟道区的薄膜晶体管为增强型薄膜晶体管， 电连接所述耗尽型 薄膜晶体管和所述增强型薄膜晶体管， 即构成电路。 [权利要求 16] 根据权利要求 15所述的电路制造方法， 其特征在于， 所述源区、 所述 漏区和所述沟道区之间由所述第一退火处理形成的连接面和所述第一 调节层在所述有源层投影面积之内的边界的铅垂面的间距小于所述有 源层厚度的 100倍。 The thin film transistor having the depletion channel region is a depletion thin film transistor, and the thin film transistor having the enhancement channel region is an enhancement thin film transistor electrically connecting the depletion thin film transistor and the enhancement type A thin film transistor constitutes a circuit. [Claim 16] The circuit manufacturing method according to claim 15, wherein a connection surface formed by the first annealing process between the source region, the drain region, and the channel region is The pitch of the vertical plane of the boundary of the first adjustment layer within the projected area of the active layer is less than 100 times the thickness of the active layer.
[权利要求 17] 根据权利要求 15所述的电路制造方法， 其特征在于， 所述第一退火处 理和所述第二退火处理包括利用热、 光、 激光、 微波加热。  [Claim 17] The circuit manufacturing method according to claim 15, wherein the first annealing treatment and the second annealing treatment comprise heating with heat, light, laser, or microwave.
[权利要求 18] 根据权利要求 15所述的电路制造方法， 其特征在于， 所述第一退火处 理是在氧化气氛下， 持续 10秒至 10小吋， 温度在 100°C和 600°C之间； 所述第二退火处理是在所述氧化气氛下， 持续 5秒至 5小吋， 温度在 10 0°C和 400°C之间。 [Claim 18] The circuit manufacturing method according to claim 15, wherein the first annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is 100 ° C and 600 ° C. The second annealing treatment is performed under the oxidizing atmosphere for 5 seconds to 5 hours, and the temperature is between 10 ° C and 400 ° C.
[权利要求 19] 根据权利要求 18所述的电路制造方法中， 其特征在于， 所述氧化气氛 包括： 氧气、 臭氧、 一氧化二氮、 水、 二氧化碳和以上物质的等离子 体。  [Claim 19] The circuit manufacturing method according to claim 18, wherein the oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above substances.
[权利要求 20] 一种显示器面板， 其特征在于， 包括多组显示模块， 所述显示模块包 括权利要求 15至 19任一所述的电路制造方法所制造的电路。  [Claim 20] A display panel comprising a plurality of sets of display modules, the display module comprising the circuit manufactured by the circuit manufacturing method according to any one of claims 15 to 19.
PCT/CN2016/103831 2015-10-29 2016-10-28 Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel WO2017071658A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562285436P 2015-10-29 2015-10-29
US62/285,436 2015-10-29

Publications (1)

Publication Number Publication Date
WO2017071658A1 true WO2017071658A1 (en) 2017-05-04

Family

ID=57956711

Family Applications (5)

Application Number Title Priority Date Filing Date
PCT/CN2016/103832 WO2017071659A1 (en) 2015-10-29 2016-10-28 Circuit structure composed of thin film transistors and manufacturing method thereof, and display panel
PCT/CN2016/103835 WO2017071661A1 (en) 2015-10-29 2016-10-28 Thin film transistor, manufacturing method therefor, and display panel
PCT/CN2016/103836 WO2017071662A1 (en) 2015-10-29 2016-10-28 Thin film transistor, manufacturing method therefore, and display panel
PCT/CN2016/103833 WO2017071660A1 (en) 2015-10-29 2016-10-28 Display panel and manufacturing method thereof
PCT/CN2016/103831 WO2017071658A1 (en) 2015-10-29 2016-10-28 Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel

Family Applications Before (4)

Application Number Title Priority Date Filing Date
PCT/CN2016/103832 WO2017071659A1 (en) 2015-10-29 2016-10-28 Circuit structure composed of thin film transistors and manufacturing method thereof, and display panel
PCT/CN2016/103835 WO2017071661A1 (en) 2015-10-29 2016-10-28 Thin film transistor, manufacturing method therefor, and display panel
PCT/CN2016/103836 WO2017071662A1 (en) 2015-10-29 2016-10-28 Thin film transistor, manufacturing method therefore, and display panel
PCT/CN2016/103833 WO2017071660A1 (en) 2015-10-29 2016-10-28 Display panel and manufacturing method thereof

Country Status (2)

Country Link
CN (6) CN106449763B (en)
WO (5) WO2017071659A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107425049A (en) * 2017-05-23 2017-12-01 华南理工大学 The thin film transistor (TFT) and preparation method of one species island electric transmission
CN107546259A (en) * 2017-09-06 2018-01-05 深圳市华星光电技术有限公司 IGZO thin film transistor (TFT)s and preparation method thereof
CN109273352B (en) * 2018-10-25 2021-03-30 山东大学 Preparation method of high-performance multi-element amorphous metal oxide thin film transistor
CN109817723B (en) * 2019-01-24 2022-07-05 北京京东方技术开发有限公司 Thin film transistor, preparation method thereof, array substrate and display device
CN110161761A (en) * 2019-05-10 2019-08-23 香港科技大学 Liquid crystal display panel and preparation method thereof and display equipment
CN112802904A (en) * 2020-12-29 2021-05-14 重庆先进光电显示技术研究院 Manufacturing method of thin film transistor device, thin film transistor device and display device
CN113707724B (en) * 2021-07-14 2024-03-26 山东师范大学 Oxide thin film transistor and preparation method and application thereof
CN113745156A (en) * 2021-08-23 2021-12-03 Tcl华星光电技术有限公司 Display panel and preparation method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1155095A (en) * 1989-11-29 1997-07-23 纳幕尔杜邦公司 Photo-electric modulator
US20020197839A1 (en) * 2001-06-22 2002-12-26 International Business Machines Corporation Anti-spacer structure for self-aligned independent gate implantation
CN101506986A (en) * 2006-08-23 2009-08-12 佳能株式会社 Production method of thin film transistor using amorphous oxide semiconductor film
CN101546768A (en) * 2008-03-28 2009-09-30 三星电子株式会社 Inverter and logic circuit including an inverter
CN102646683A (en) * 2012-02-02 2012-08-22 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof
CN102683423A (en) * 2012-05-08 2012-09-19 东莞彩显有机发光科技有限公司 Metal oxide thin film transistor with top gate structure and manufacturing method thereof

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000311992A (en) * 1999-04-26 2000-11-07 Toshiba Corp Nonvolatile semiconductor memory device and manufacture thereof
KR100845557B1 (en) * 2002-02-20 2008-07-10 삼성전자주식회사 Active matrix organic light emitting device and method of manufacturing the same
KR100659759B1 (en) * 2004-10-06 2006-12-19 삼성에스디아이 주식회사 bottom-gate type thin film transistor, flat panel display including the same and fabrication method of the thin film transistor
US8222646B2 (en) * 2005-07-08 2012-07-17 The Hong Kong University Of Science And Technology Thin-film transistors with metal source and drain and methods of fabrication
KR101236427B1 (en) * 2006-05-10 2013-02-22 삼성디스플레이 주식회사 Method of manufacturing gate insulator and thin film transistor adopting the insulator
CN101217112A (en) * 2007-01-04 2008-07-09 中国科学院微电子研究所 A preparation method of nanometer scale W/TiN compound refractory metal bar
JP5213422B2 (en) * 2007-12-04 2013-06-19 キヤノン株式会社 Oxide semiconductor element having insulating layer and display device using the same
JP5331382B2 (en) * 2008-05-30 2013-10-30 富士フイルム株式会社 Manufacturing method of semiconductor device
KR100958006B1 (en) * 2008-06-18 2010-05-17 삼성모바일디스플레이주식회사 Thin film transistor, method of manufacturing the thin film transistor and flat panel display device having the thin film transistor
US8492756B2 (en) * 2009-01-23 2013-07-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN101478005B (en) * 2009-02-13 2010-06-09 北京大学深圳研究生院 Metal oxide thin-film transistor and manufacturing process thereof
KR101608887B1 (en) * 2009-04-17 2016-04-05 삼성전자주식회사 Inverter, method of manufacturing the same and logic circuit comprising inverter
WO2011034012A1 (en) * 2009-09-16 2011-03-24 Semiconductor Energy Laboratory Co., Ltd. Logic circuit, light emitting device, semiconductor device, and electronic device
JPWO2011039853A1 (en) * 2009-09-30 2013-02-21 キヤノン株式会社 Thin film transistor
KR20110093113A (en) * 2010-02-11 2011-08-18 삼성전자주식회사 Thin film transistor array substrate and method of fabricating the same
US9093539B2 (en) * 2011-05-13 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN104934481B (en) * 2014-03-21 2017-10-13 北京大学深圳研究生院 A kind of thin film transistor (TFT) and preparation method thereof
CN104157699B (en) * 2014-08-06 2019-02-01 北京大学深圳研究生院 A kind of back channel-etch type thin film transistor and preparation method thereof
CN104851809A (en) * 2015-04-09 2015-08-19 信利（惠州）智能显示有限公司 Thin-film transistor, producing method thereof, array substrate, and display device

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1155095A (en) * 1989-11-29 1997-07-23 纳幕尔杜邦公司 Photo-electric modulator
US20020197839A1 (en) * 2001-06-22 2002-12-26 International Business Machines Corporation Anti-spacer structure for self-aligned independent gate implantation
CN101506986A (en) * 2006-08-23 2009-08-12 佳能株式会社 Production method of thin film transistor using amorphous oxide semiconductor film
CN101546768A (en) * 2008-03-28 2009-09-30 三星电子株式会社 Inverter and logic circuit including an inverter
CN102646683A (en) * 2012-02-02 2012-08-22 京东方科技集团股份有限公司 Array substrate and manufacturing method thereof
CN102683423A (en) * 2012-05-08 2012-09-19 东莞彩显有机发光科技有限公司 Metal oxide thin film transistor with top gate structure and manufacturing method thereof

Also Published As

Publication number Publication date
CN106409841B (en) 2019-06-25
WO2017071660A1 (en) 2017-05-04
CN106449763A (en) 2017-02-22
WO2017071661A1 (en) 2017-05-04
CN106449763B (en) 2019-06-25
CN206505923U (en) 2017-09-19
WO2017071662A1 (en) 2017-05-04
CN106384735A (en) 2017-02-08
CN106384735B (en) 2020-04-21
CN106449732A (en) 2017-02-22
CN106409841A (en) 2017-02-15
WO2017071659A1 (en) 2017-05-04
CN106486499B (en) 2019-08-06
CN106449732B (en) 2020-04-21
CN106486499A (en) 2017-03-08

Similar Documents

Publication Publication Date Title
WO2017071658A1 (en) Circuit structure consisting of thin-film transistors and manufacturing method thereof, and display panel
USRE48290E1 (en) Thin film transistor array panel
US10192992B2 (en) Display device
US9184300B2 (en) Transistor, method of manufacturing the same, and electronic device including transistor
KR101675114B1 (en) Thin film transistor and manufacturing method of the same
US20150187948A1 (en) Semiconductor device and method for producing same
JP2014131047A (en) Thin-film transistor and thin-film transistor display board
JP2004273614A (en) Semiconductor device and its fabricating process
US9893203B2 (en) Thin film transistor array panel and method for manufacturing the same
US20180308870A1 (en) Semiconductor device, display device, and method for manufacturing the same
JP5442228B2 (en) Display device and manufacturing method of display device
US20150280002A1 (en) Metal oxide thin film transistor with channel, source and drain regions respectively capped with covers of different gas permeability
US10985281B2 (en) Transistor, thin film transistor array panel, and related manufacturing method
WO2019171505A1 (en) Thin film transistor, method for producing same and display device
TWI422035B (en) Semiconductor device structure and method for manufacturing the same
US8389310B2 (en) Method for manufacturing oxide thin film transistor and method for manufacturing display device
CN207517701U (en) A kind of thin film transistor (TFT) and display pannel
CN206259353U (en) A kind of display pannel
WO2023155091A1 (en) Metal oxide thin film transistor, array substrate, and display device
KR20240046023A (en) Semiconductor device
CN116529856A (en) Metal oxide thin film transistor, array substrate and preparation method thereof
CN110161761A (en) Liquid crystal display panel and preparation method thereof and display equipment
KR20050047429A (en) Polysilicone thin film transistor and flat panel display device using the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16859093

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

32PN Ep: public notification in the ep bulletin as address of the adressee cannot be established

Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 16/08/2018)

122 Ep: pct application non-entry in european phase

Ref document number: 16859093

Country of ref document: EP

Kind code of ref document: A1