CN106449763B - A kind of thin film transistor (TFT) and manufacturing method and display pannel - Google Patents

A kind of thin film transistor (TFT) and manufacturing method and display pannel Download PDF

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CN106449763B
CN106449763B CN201610964470.9A CN201610964470A CN106449763B CN 106449763 B CN106449763 B CN 106449763B CN 201610964470 A CN201610964470 A CN 201610964470A CN 106449763 B CN106449763 B CN 106449763B
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electrode
film transistor
tft
thin film
region
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CN106449763A (en
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陆磊
王文
郭海成
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Abstract

A kind of thin film transistor (TFT), it include: the active layer being made of metal oxide of substrate and setting over the substrate, the active layer mutually adjoins with gate stack, electrode is covered on the active layer partial region, it further include insulating layer between the electrode and the active layer, region of the active layer under electrode covering is respectively formed source region, drain region, and the region under the non-electrode covering forms channel region.The invention further relates to method for fabricating thin film transistor and the display pannel with above-mentioned thin film transistor (TFT).Above-mentioned thin film transistor (TFT) had not only had the small size of tradition back channel etching structure transistor, but also had performance more superior than conventional etch barrier layer structure transistor, including low source and drain dead resistance, better ON state and OFF state performance, the reliability of enhancing.Have many advantages, such as that the display pannel of above-mentioned thin film transistor (TFT) has both high-performance, high reliability, low cost, more meets the development trend of display pannel.

Description

A kind of thin film transistor (TFT) and manufacturing method and display pannel
Technical field
The present invention relates to a kind of metal oxide thin-film transistor structure and its manufacturing methods, in particular for display surface Thin-film transistor structure in plate.
Background technique
Traditional metal oxide thin-film transistor is by depositing metal on active layer as electrode.In electrode and have It usually will form Schottky barrier at the contact interface of active layer, so that the resistance value of contact interface is very high, and then increase film The parasitic contact resistance of transistor, while the metal-oxide semiconductor (MOS) of eigenstate is usually high resistivity, this can bring height The problem of source and drain resistance of resistivity.Existing solution is to reduce source region, drain region by being doped to source region, drain region Resistivity, but this usually using sacrifice technology stability and increase preparation cost as cost.For example, source and drain areas passes through plasma Processing is by hydrogen ion doped to source region, drain region, but whole process and unstable.Other dopants, such as boron and phosphorus, then need Prohibitively expensive ion implantation device and additional activation.For this purpose, wanting a kind of in thin film transistor (TFT) manufacturing urgent need Low in cost, the simple method of manufacturing process reduces the resistivity of metal oxide source and drain areas.
On the other hand, channel etching (back-channel etched BCE) structure and etching barrier layer (etch- are carried on the back Stop ES) structure be backgate metal oxide thin-film transistor two kinds of mainstream structures.In the thin of tradition back channel etching structure In film transistor, interface can be damaged when etching electrode on exposed channel, and then influence the performance of device.Though Such damage so is avoided that by adding one layer of etching barrier layer over the channel region, but it is additional not only to will increase a step in this way Photoetching process, to increasing preparation cost, it is often more important that etching barrier layer device architecture needs to extend channel length and grid The length of pole electrode can expand the area of thin film transistor (TFT) in this way and then greatly limit the further of the resolution ratio of display It is promoted, has deviated from the high-resolution development trend of display.For conclusion, the advantage for carrying on the back the device architecture of channel etching is to mention Simple technical process, lower preparation cost and lesser device size have been supplied, and the device architecture of etching barrier layer provides More preferably device performance and improved device stability, but the area of device is expanded, it increases manufacturing cost.For this purpose, golden Belong to oxide thin film transistor manufacturing industry and be badly in need of a kind of novel thin-film transistor structure, low cost, Gao Xing can be met simultaneously The multiple requestings such as energy, small size.
Summary of the invention
Technical problem to be solved by the present invention lies in the deficiencies for overcoming the above-mentioned prior art, provide a kind of source-drain area first Domain resistivity is small, but the high performance metal-oxide thin-film transistor structure that manufacturing cost is cheap.
A kind of thin film transistor (TFT) provided by the invention, comprising: substrate and setting over the substrate by metal oxide The active layer of composition；The active layer mutually adjoins with gate stack, and electrode, the electricity are covered on the active layer partial region The thickness of pole is greater than diffusion length of the substance containing oxygen element in the electrode, also wraps between the electrode and the active layer Include insulating layer；Part of the insulating layer under the non-electrode covering is the first insulating layer, the thickness of first insulating layer Less than diffusion length of the substance containing oxygen element in first insulating layer；The active layer is under electrode covering Region be respectively formed source region and drain region, the lower region formation channel region of the non-electrode covering；The source region, the drain region with The channel region is connected with each other, and is located at the both ends of the channel region, and the channel region mutually adjoins with the gate stack, Joint face between the source region, the drain region and the channel region is self-aligned to the electrode in the active layer projected area Within boundary vertical guide；The source region, the resistivity in the drain region are less than the resistivity of the channel region.
As the preferred mode of above-mentioned transistor arrangement:
The joint face and the electrode formed between the source region, the drain region and the channel region by annealing has described The spacing of the vertical guide on the boundary within active layer projected area is less than 100 times of the active layer thickness.
The channel region and the resistivity ratio of the source region, the drain region are greater than 1000 times.
The active layer includes one of following material or a variety of combinations: zinc oxide, nitrogen oxidation zinc, tin oxide, oxygen Change indium, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc-tin oxide, aluminium oxide tin, tin indium oxide, indium gallium zinc, oxidation Indium tin zinc, aluminum oxide indium tin zinc, zinc sulphide, barium titanate, strontium titanates or lithium niobate.
First insulating layer includes one of following material or a variety of combinations: silica, silicon oxynitride, wherein institute The ratio of silicon nitride in silicon oxynitride is stated less than 20%.Wherein, first insulating layer with a thickness of 10 to 3000 nanometers.
The electrode with a thickness of the substance containing oxygen element between 2 to 100 times of diffusion length in the electrode.
The electrode includes one of following material or a variety of combinations: titanium, molybdenum, aluminium, copper, silver, gold, nickel, tungsten, chromium, Hafnium, platinum, iron, titanium-tungsten, molybdenum aluminium alloy, molybdenum-copper or albronze.Wherein, the electrode is received with a thickness of 10 to 3000 Rice.
The gate stack may be provided between the active layer and the substrate；Alternatively,
The active layer is arranged between the gate stack and the substrate.Further, the gate stack packet Gate electrode and gate insulating layer are included, the thickness of the gate electrode is less than the substance containing oxygen element in the gate electrode In diffusion length, the thickness of the gate insulating layer is less than the expansion of the substance containing oxygen element in the gate insulating layer Dissipate length.The gate electrode includes one of following material or a variety of combinations: zinc oxide, tin indium oxide, aluminum zinc oxide, Indium oxide aluminium or indium zinc oxide；The gate insulating layer includes one of following material or a variety of combinations: silica, nitrogen oxygen SiClx, wherein the ratio of silicon nitride is less than 20% in the silicon oxynitride.The gate electrode with a thickness of 10 to 3000 nanometers； The gate insulating layer with a thickness of 10 to 3000 nanometers.
The substance containing oxygen element includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide and above-mentioned The plasma of substance.
Less than 10 ohmcms, the resistivity of the channel region is greater than 10 ohmcms for the source region, the resistivity in drain region.
The present invention also provides a kind of display pannel, including multiple groups display module, the display module includes above-mentioned institute The thin film transistor (TFT) stated.
The present invention also provides a kind of manufacturing methods of thin film transistor (TFT), comprising:
Prepare a substrate；
In the gate stack that the substrate is arranged active layer and mutually adjoins with the active layer, the active layer is by gold Belong to oxide to constitute；
It is covered with electrode on the partial region of the active layer, the thickness of the electrode is made to be greater than the substance containing oxygen element Diffusion length in the electrode；
It is provided with insulating layer between the electrode and the active layer, makes the insulating layer under the non-electrode covering Part be the first insulating layer, the thickness of first insulating layer is less than the substance containing oxygen element in first insulating layer In diffusion length；
It is made annealing treatment, region of the active layer under electrode covering is made to be respectively formed source region and drain region, it is non- Region under the electrode covering forms channel region, and the channel region mutually adjoins with the gate stack, the source region, the leakage Area and the channel region are connected with each other and are located at the both ends of the channel region, and make the source region, the drain region with it is described Joint face is formed by annealing between channel region, which is self-aligned to the electrode within the active layer projected area The resistivity in the vertical guide on boundary, the source region and the drain region is less than the resistivity of the channel region.
The preferred embodiment of the preparation method of transistor described above as the present invention:
The joint face and the electrode formed between the source region, the drain region and the channel region by the annealing is in institute The spacing for stating the vertical guide on the boundary within active layer projected area is less than 100 times of the active layer thickness.
The annealing is heated including the use of heat, light, laser, microwave.
The annealing is under oxidizing atmosphere, and for 10 seconds to 10 hours, temperature was between 100 DEG C and 600 DEG C.
The oxidizing atmosphere includes: the plasma of oxygen, ozone, nitrous oxide, water, carbon dioxide and above-mentioned substance Body.
According to the above method, the present invention also provides a kind of display pannel, including multiple groups display module, the display mould Block includes the thin film transistor (TFT) using method described above preparation.
Relative to traditional thin-film transistor structure, the invention has the following advantages that firstly, this programme directly passes through annealing Source region, drain region are formd in active layer, have not only maintained the device size as back channel etching structure, but also realize etching The high-performance of barrier layer structure device.The advantages of having combined high-performance and small size meets the hair of current display very much Exhibition trend, the especially development and application in terms of augmented reality, virtual reality.Secondly, annealing reduces the resistance of source and drain areas Rate thereby reduces the parasitic contact resistance between electrode and active layer, has been obviously improved the ON state performance of thin film transistor (TFT).Together When, the high resistivity of channel region is also maintained or even increased due to annealing, to reduce the OFF state of thin film transistor (TFT) significantly Electric current.Importantly, annealing can largely eliminate the defect density in channel region, greatly promotion device is reliable Property.The channel region of the first dielectric protection layer thin film transistor (TFT) above the channel region being naturally introduced by from external environment influence, The environmental reliability of device can be further strengthened.The present invention directly with electrode-covering portions active layer region, passes through annealing Come reduce electrode covering under source region, the resistivity in drain region, in the doping step being omitted in conventional semiconductor processing and photoetching Step while saving preparation cost, ensure that the stability of the low-resistivity of source and drain areas.Therefore, of the invention, have both height The advantages that performance, small size, high reliability, low cost.
Detailed description of the invention
Fig. 1 is the cross-sectional view of tradition back channel etching structure backgate thin film transistor (TFT).
Fig. 2 is the cross-sectional view of conventional etch barrier layer structure backgate thin film transistor (TFT).
Fig. 3 is the cross-sectional view of the first embodiment of thin-film transistor structure in the present invention.
Fig. 4 is the cross-sectional view of second of embodiment of thin-film transistor structure in the present invention.
Fig. 5 is the cross-sectional view of the third embodiment of thin-film transistor structure in the present invention.
Fig. 6 is the cross-sectional view of the 4th kind of embodiment of thin-film transistor structure in the present invention.
Fig. 7 is the schematic diagram of the first display module structure in display panel in the present invention.
Fig. 8 is the schematic diagram of second of display module structure in display panel in the present invention.
Specific embodiment
Referring to Fig.1, Fig. 1 is the cross-sectional view of tradition back channel etching structure backgate thin film transistor (TFT).Wherein, thin film transistor (TFT) It include: substrate 1a, the active layer 2a being arranged on substrate 1a.Gate stack 3a is additionally provided between active layer 2a and substrate 1a. Gate stack 3a includes the gate electrode 31a and gate insulating layer 32a being arranged between gate electrode 31a and active layer 2a.Have Electrode 4a is covered on active layer 2a.Active layer 2a is respectively formed source region 21a, drain region 23a with the region being in contact electrode 4a, has The region that active layer 2a is in contact with non-electrode 4a forms channel region 22a.Wherein, channel region 22a adjoins with gate stack 3a phase, and Source region 21a, drain region 23a are located at the both ends of channel region 22a, and are connected with channel region 22a.It is worked in thin film transistor (TFT) Cheng Zhong can change the resistivity of channel region, and then control through channel region by applying certain voltage to gate electrode Electric current, to realize the switch of thin film transistor (TFT).The off-state current of thin film transistor (TFT) is heavily dependent on the electricity of channel region Resistance rate and defect concentration, higher resistivity and fewer defects band of density come lower off-state current and better device Energy.The on-state current of thin film transistor (TFT) is limited to source region, the resistivity in drain region, and lower source region, the resistivity in drain region are conducive to Dead resistance is reduced, on-state current is improved.For carrying on the back channel etching structure backgate thin film transistor (TFT), channel region 22a is being etched It will receive damage during electrode 4a, generate a large amount of defect concentrations, substantially reduce the performance of device.The defect concentration packet of generation Conductive-type defect concentration is included, the resistivity of channel region 22a can be reduced, thus the OFF state electricity of very big transistor operating current Stream.On the other hand, the source region 21a of intrinsic high resistivity, drain region 23a can also reduce the on-state current of thin film transistor (TFT).
It is the cross-sectional view of conventional etch barrier layer structure backgate thin film transistor (TFT) referring to Fig. 2, Fig. 2.Wherein, thin film transistor (TFT) It include: substrate 1b, the active layer 2b being arranged on substrate 1b.Gate stack 3b is additionally provided between active layer 2b and substrate 1b. Gate stack 3b includes the gate electrode 31b and gate insulating layer 32b being arranged between gate electrode 31b and active layer 2b.? Etching barrier layer 5 is provided on active layer 2b.Electrode 4b is covered on etching barrier layer 5 and active layer 2b.Active layer 2b with The region that electrode 4b is in contact is respectively formed source region 21b, drain region 23b, and active layer 2b is formed with the region being in contact non-electrode 4b Channel region 22b.Wherein, channel region 22b adjoins with gate stack 3b phase, and source region 21b, drain region 23b are located at channel region 22b Both ends, and be connected with channel region 22b.Protect channel region 22b from electrode 4b etching process institute band by etching barrier layer 5 The damage come, to avoid introducing defect concentration in channel region 22b and reduce resistivity.But because etching barrier layer 5 draws Enter, channel region 22b and gate electrode 31b will correspondingly be extended, to guarantee that channel region 22b still passes through source region 21b, drain region 23b is connected with electrode 4b.This greatly increases the areas of thin film transistor (TFT), have deviated from the hair of thin film transistor (TFT) miniaturization Exhibition trend.Meanwhile because needing an additional step lithography step to carry out graphical etching barrier layer 5, preparation cost also be will increase.Equally Ground, the source region 21b of intrinsic high resistivity, drain region 23b can also reduce film crystal in etching barrier layer structure thin film transistor (TFT) The on-state current of pipe, influences device performance.
The present invention is described in detail with reference to the accompanying drawings and embodiments.It should be appreciated that specific embodiment described herein is Non-limiting example embodiment, and the feature shown in attached drawing be not required it is drawn to scale.Given example is only intended to favorably In explaining the present invention, it is understood not to limitation of the invention.
It is the cross-sectional view of the first embodiment of thin-film transistor structure in the present invention referring to Fig. 3, Fig. 3.It is thin in the present embodiment Film transistor uses back grid structure.Wherein, thin film transistor (TFT) includes: substrate 1；Active layer 2 on substrate 1 is set；Active layer 2 Gate stack 3 is additionally provided between substrate 1, gate stack 3 then includes gate electrode 31 and setting in gate electrode 31 and has Gate insulating layer 32 between active layer 2；The top of active layer 2 is covered with insulating layer 6, is formed on insulating layer 6 and is deep to active layer 2 Through-hole, be deposited with conductor in the through-hole, thus by extraction electrode 4 in the through-hole, the portion with active layer 2 respectively of electrode 4 Subregion is electrically connected.
Referring to Fig. 3, substrate 1 includes but is not limited to following material: glass, polymer substrate, flexible material etc..
Referring to Fig. 3, active layer 2 includes one of following material or a variety of combinations: zinc oxide, nitrogen oxidation zinc, oxidation Tin, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc-tin oxide, aluminium oxide tin, tin indium oxide, indium gallium Zinc, indium tin zinc oxide, aluminum oxide indium tin zinc, zinc sulphide, barium titanate, strontium titanates or lithium niobate.
In the present invention, when insulating layer or the thickness of conductor layer are less than the substance containing oxygen element in the insulating layer or conductor layer Diffusion length when, the substance containing oxygen element can enter metal oxide and have in annealing through the insulating layer or conductor layer Active layer, to keep, the resistivity of even raising metal oxide, the insulating layer or conductor layer are oxygen permeable layers at this time；When one When insulating layer or the thickness of conductor layer are greater than diffusion length of the substance containing oxygen element in the insulating layer, the insulating layer or conductor Layer can stop the substance containing oxygen element, to reduce the resistivity of metal oxide, the insulating layer or conductor layer are impermeable at this time Oxygen layer.
The substance containing oxygen element includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide and above-mentioned The plasma of substance.
Referring to Fig. 3, the thickness of insulating layer 6 is less than the diffusion length of the substance containing oxygen element in insulating layer 6, described Substance containing oxygen element can penetrate insulating layer 6 in annealing, thus insulating layer 6 is oxygen permeable layer.Insulating layer 6 includes following One of material or a variety of combinations: silica, silicon oxynitride, wherein the ratio of silicon nitride is less than in the silicon oxynitride 20%.Insulating layer 6 with a thickness of 10 to 3000 nanometers.Preferably, the thickness of insulating layer 6 is between 200 nanometers to 500 nanometers.
Referring to Fig. 3, the thickness of electrode 4 is greater than the diffusion length of the substance containing oxygen element in electrode 4,4 energy of electrode Stop the substance containing oxygen element, thus electrode 4 is impermeable oxygen layer.Preferably, electrode 4 with a thickness of described containing oxygen element Substance is between 2 to 100 times of diffusion length in electrode 4.Electrode 4 includes one of following material or a variety of combinations: titanium, Molybdenum, aluminium, copper, silver, gold, nickel, tungsten, chromium, hafnium, platinum, iron, titanium-tungsten, molybdenum aluminium alloy, molybdenum-copper or albronze.Electrode 4 With a thickness of 10 to 3000 nanometers.Preferably, the thickness of electrode 4 is between 200 nanometers to 500 nanometers.
Referring to Fig. 3, in annealing, electrode 4 blocks the described substance containing oxygen element, and active layer 2 is in the case where electrode 4 covers The resistivity in region be minimized, form source region 21, drain region 23.The resistivity of the source region 21, drain region 23 that reduce is conducive to The contact resistance between source region 21, drain region 23 and electrode 4 is reduced, to improve the ON state performance of thin film transistor (TFT).With electrode 4 For characteristic on the contrary, in annealing, the substance containing oxygen element can enter active layer 2, therefore active layer 2 through insulating layer 6 The resistivity in the region under non-electrode 4 covering, which is maintained, even to be improved, and channel region 22 is formed.It is exhausted above channel region 22 Edge layer 6 can also improve the resistivity of channel region 22, reduce the defect concentration of channel region 22, so as to improve the OFF state of thin film transistor (TFT) Characteristic, and insulating layer 6 can also protect channel region 22 from the influence of external environment, improve thin film transistor (TFT) stability and can By property.
Referring to Fig. 3, in the present invention, by covering electrode 4 above 2 partial region of active layer, then with make annealing treatment come Source region 21, the resistivity in drain region 23 are reduced, while being kept, the high resistivity of even raising channel region 22.Source region in active layer 2 21, drain region 23 and channel region 22 are connected with each other.Its joint face formed of annealing is and automatic without any lithography alignment technique In alignment with the boundary of the electrode 4 of covering active layer 2, it is similarly in existing silicon-based field-effect transistors technique, adulterates formation The joint face of source region, drain region and channel region is self aligned to gate electrode boundary.Usually all there is centainly inclined in this autoregistration Poor range.In the present invention, the joint face of source region, drain region and channel region is self-aligned to side of the electrode within active layer projected area The vertical guide on boundary, the deviation of alignment are less than 100 times of active layer thickness.
In the present invention, the projected area is the perspective plane of the vertical direction shown in the drawings in specific embodiment Product.
In the present invention, the annealing is heated including the use of heat, light, laser, microwave.The annealing is Under oxidizing atmosphere, for 10 seconds to 10 hours, temperature was between 100 DEG C and 600 DEG C.The oxidizing atmosphere includes: oxygen, smelly Oxygen, nitrous oxide, water, carbon dioxide and above-mentioned substance plasma.
Relative to traditional resistivity for reducing source region, drain region by way of being doped to source region and drain region, originally Resulting source region, the resulting resistivity of resistivity ratio doping in drain region of annealing in invention are lower, and the source region under electrode protection, leakage The low-resistivity in area is more stable.Relative to Traditional dopant mode, technique of the invention is simpler, cost is also lower.But the present invention Doping is not limited, and one or more of impurity: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminium or antimony can be mixed in active layer. This does not interfere the source region of device, channel region and the formation in drain region.Also therefore, the present invention and existing doping process are completely compatible, tool There is high scalability.
Relative to the method for conventional thin film transistor, annealing also assures, even improves channel region in the present invention High resistivity, so that the off-state current of thin film transistor (TFT) is significantly reduced, far below the 10 of current mainstream-13Pacify every micron, Even it is reduced to extremely low 10-18Pacify every micron.Importantly, annealing also largely eliminates lacking in channel region Density is fallen into, for example, Lacking oxygen defect concentration, metal interstitial defect density etc., these defect concentrations are universally present in metal oxygen In compound, it is considered to be an important factor for reducing the Performance And Reliability of thin film transistor (TFT), but in traditional device architecture again It is difficult thoroughly to eliminate.Because eliminating these defect concentrations, disclosed in this invention thin-film transistor structure greatly increase The strong performance and long-term reliability of thin film transistor (TFT).For example, the current on/off ratio of metal oxide thin-film transistor is greatly It improves, be even higher than 1011；Threshold voltage shift caused by common echo effect is suppressed within 0.15V；On gate electrode 0V or so is arrived in the shift degradation elimination of generated threshold voltage when applying certain voltage.Secondly, covered above channel region Insulating layer can not only protect completely channel region to damage from electrode etch bring as etching barrier layer, additionally it is possible to very well Ground protective film transistor is from the influence of external environment, the environmental stability of enhanced film transistor.For example, Celsius 80 The problem of performance degradations such as threshold voltage shift caused by 10 hours are saved under degree, 80% relative humidity, through the invention Middle thin-film transistor structure is available to be substantially improved.
In summary, the present invention possesses plurality of advantages compared to conventional thin film transistor structure, comprising: simpler manufacture Technique, lower preparation cost, higher process spread, more preferably device performance, reliability and environmental stability.
It is the cross-sectional view of second of embodiment of thin-film transistor structure in the present invention referring to Fig. 4, Fig. 4.It is thin in the present embodiment Film transistor uses top gate structure.Similarly, thin film transistor (TFT) includes: substrate 1；Active layer 2 on substrate 1 is set；It is active The oxygen flow grid for being provided with oxygen flow gate electrode 311 on layer 2 and being arranged between oxygen flow gate electrode 311 and active layer 2 is exhausted Edge layer 321；The top of active layer 2, oxygen flow gate insulating layer 321 and oxygen flow gate electrode 311 is covered with insulating layer 6, insulating layer 6 On be formed with the through-hole for being deep to active layer 2, be deposited with conductor in the through-hole, thus by extraction electrode 4 in the through-hole, electrode 4 partial region respectively with active layer 2 is electrically connected.
Referring to Fig. 4, the thickness of oxygen flow gate electrode 311 is less than the expansion of the substance containing oxygen element in gate electrode 31 Length is dissipated, the substance containing oxygen element can penetrate oxygen flow gate electrode 311, thus oxygen flow gate electrode in annealing 311 be oxygen permeable layer；Oxygen flow gate electrode 311 includes one of following material or a variety of combinations: zinc oxide, tin indium oxide, Aluminum zinc oxide, indium oxide aluminium or indium zinc oxide；Oxygen flow gate electrode 311 with a thickness of 10 to 3000 nanometers.Preferably, oxygen flow grid The thickness of pole electrode 311 is between 200 nanometers to 500 nanometers.
Referring to Fig. 4, the thickness of oxygen flow gate insulating layer 321 is less than the substance containing oxygen element in oxygen flow gate insulating layer Diffusion length in 321；The substance containing oxygen element can penetrate oxygen flow gate insulating layer 321 in annealing, thus Oxygen flow gate insulating layer 321 is oxygen permeable layer；Oxygen flow gate insulating layer 321 includes one of following material or a variety of combinations: Silica, silicon oxynitride, wherein the ratio of silicon nitride is less than 20% in the silicon oxynitride；The thickness of oxygen flow gate insulating layer 321 Degree is 10 to 3000 nanometers.Preferably, the thickness of oxygen flow gate insulating layer 321 is between 200 nanometers to 500 nanometers.
Referring to Fig. 4, in the present invention, in annealing, electrode 4 blocks the substance containing oxygen element, and active layer 2 is in electricity The resistivity in the region under the covering of pole 4 is minimized, and forms source region 21, drain region 23.The resistance of the source region 21, drain region 23 that reduce Rate advantageously reduces the contact resistance between source region 21, drain region 23 and electrode 4, to improve the ON state performance of thin film transistor (TFT). Characteristic with electrode 4 is on the contrary, insulating layer 6, oxygen flow gate electrode 311 and oxygen flow gate insulating layer 321 are oxygen permeable layers.Annealing In, the substance containing oxygen element can enter through insulating layer 6, oxygen flow gate electrode 311 and oxygen flow gate insulating layer 321 to be had Active layer 2, thus the resistivity in region of the active layer 2 under non-electrode 4 covering is maintained and even improves, and forms channel region 22. Insulating layer 6 above channel region 22 can also improve the resistivity of channel region 22, reduce the defect concentration of channel region 22, to change The OFF state characteristic of kind thin film transistor (TFT), and insulating layer 6 can also protect channel region 22 from the influence of external environment, improve film The stability and reliability of transistor.
It is the cross-sectional view of the third embodiment of thin-film transistor structure in the present invention referring to Fig. 5, Fig. 5.It is thin in the present embodiment Film transistor uses back grid structure.Wherein, thin film transistor (TFT) includes: substrate 1；Active layer 2 on substrate 1 is set；Active layer 2 Gate stack 3 is additionally provided between substrate 1, gate stack 3 then includes gate electrode 31 and setting in gate electrode 31 and has Gate insulating layer 32 between active layer 2；Second insulating layer 61 and the first insulation have been covered each by above the different zones of active layer 2 Layer 62 is formed with the through-hole for being deep to active layer 2 in second insulating layer 61, is deposited with conductor in the through-hole, thus by described logical Extraction electrode 4 in hole, partial region of the electrode 4 respectively with active layer 2 are electrically connected.The projected area and electricity of second insulating layer 61 The projected area of pole 4 is completely overlapped, and the first insulating layer 62 is except the projected area of electrode 4.
Referring to Fig. 5, the thickness of second insulating layer 61 is greater than the expansion of the substance containing oxygen element in second insulating layer 61 Length is dissipated, the substance containing oxygen element can be stopped, thus second insulating layer 61 is impermeable oxygen layer；Preferably, the second insulation Layer 61 with a thickness of the substance containing oxygen element between 2 to 100 times of diffusion length in second insulating layer 61.Second insulation Layer 61 is made of following material: silicon nitride, silicon oxynitride, aluminium oxide, hafnium oxide, wherein the silicon nitride ratio in silicon oxynitride is big In 20%.Second insulating layer 61 with a thickness of 10 to 3000 nanometers.Preferably, the thickness of second insulating layer 61 is arrived at 200 nanometers Between 500 nanometers.
Referring to Fig. 5, in the present invention, the thickness of the first insulating layer 62 is less than the substance containing oxygen element in the first insulating layer Diffusion length in 62, the substance containing oxygen element can penetrate the first insulating layer 62, thus the first insulation in annealing Layer 62 is oxygen permeable layer.First insulating layer 62 includes one of following material or a variety of combinations: silica, silicon oxynitride, In, the ratio of silicon nitride is less than 20% in the silicon oxynitride.First insulating layer 62 with a thickness of 10 to 3000 nanometers.It is preferred that Ground, the thickness of the first insulating layer 62 is between 200 nanometers to 500 nanometers.
Referring to Fig. 5, in annealing, electrode 4 and second insulating layer 61 stop the substance containing oxygen element jointly, have The resistivity in region of the active layer 2 in the case where electrode 4 and second insulating layer 61 cover is minimized, and forms source region 21, drain region 23.It reduces Source region 21, the resistivity in drain region 23 advantageously reduce the contact resistance between source region 21, drain region 23 and electrode 4, to mention The ON state performance of high thin film transistor (TFT).It is described oxygen-containing with the characteristic of electrode 4 and second insulating layer 61 on the contrary, in annealing The substance of element can enter active layer 2 through the first insulating layer 62, thus active layer 2 is in non-electrode 4 and second insulating layer 61 The resistivity in the region under covering is maintained and even improves, and forms channel region 22.The first insulating layer above channel region 22 62 can also improve the resistivity of channel region 22, reduce the defect concentration of channel region 22, special so as to improve the OFF state of thin film transistor (TFT) Property, and the first insulating layer 62 can also protect channel region 22 from the influence of external environment, improve the stability of thin film transistor (TFT) And reliability.
It is the cross-sectional view of the 4th kind of embodiment of thin-film transistor structure in the present invention referring to Fig. 6, Fig. 6.In the present embodiment Thin film transistor (TFT) uses back grid structure.Wherein, thin film transistor (TFT) includes: substrate 1；Active layer 2 on substrate 1 is set；It is active Gate stack 3 is additionally provided between layer 2 and substrate 1, gate stack 3 then includes gate electrode 31 and is arranged in 31 He of gate electrode Gate insulating layer 32 between active layer 2；Second insulating layer 61 and first has been covered each by above the different zones of active layer 2 absolutely Edge layer 62 is formed with the through-hole for being deep to active layer 2 in second insulating layer 61, conductor is deposited in the through-hole, thus by described Extraction electrode 4 in through-hole, partial region of the electrode 4 respectively with active layer 2 are electrically connected.The projected area of second insulating layer 61 with The projected area of electrode 4 is completely overlapped, and the first insulating layer 62 is except the projected area of electrode 4.In electrode 4, second insulating layer 61 and first are also covered with third insulating layer 7 on insulating layer 62.The perspective plane of the projected area of second insulating layer 61, electrode 4 Long-pending and third insulating layer 7 projected area is completely overlapped, and the first insulating layer 62 is except the projected area of electrode 4.
Referring to Fig. 6, in annealing, third insulating layer 7, electrode 4 and second insulating layer 61 stop described oxygen-containing jointly The resistivity of the substance of element, region of the active layer 2 under the covering of third insulating layer 7, electrode 4 and second insulating layer 61 is dropped It is low, form source region 21, drain region 23.The resistivity of the source region 21, drain region 23 that reduce advantageously reduces source region 21, drain region 23 and electricity Contact resistance between pole 4, to improve the ON state performance of thin film transistor (TFT).With the characteristic of electrode 4 on the contrary, in annealing, The substance containing oxygen element can through the first insulating layer 62 enter active layer 2, thus active layer 2 non-third insulating layer 7, The resistivity in electrode 4 and the region under the covering of second insulating layer 61 is maintained and even improves, and forms channel region 22.In channel region First insulating layer 62 of 22 tops can also improve the resistivity of channel region 22, reduce the defect concentration of channel region 22, so as to improve The OFF state characteristic of thin film transistor (TFT), and the first insulating layer 62 can also protect channel region 22 from the influence of external environment, improve The stability and reliability of thin film transistor (TFT).
It is the schematic diagram of the first display module structure in display panel in the present invention, display pannel referring to Fig. 7, Fig. 7 It is made of multiple display modules.It include thin film transistor (TFT), intermediate insulating layer 8, pixel electrode 9, photoelectric material 10 in display module With public electrode 11.Pixel electrode 9 and the electrode 4 of the thin film transistor (TFT) are electrically connected by the through-hole on intermediate insulating layer 8. Photoelectric material 10 includes but is not limited to: liquid crystal, light emitting diode, Organic Light Emitting Diode, light emitting diode with quantum dots.In this reality It applies in the display panel of example, the thin film transistor (TFT) is thin film transistor (TFT) described in Fig. 3.The thin film transistor (TFT) can be also used for structure At the driving circuit in circuit, such as display panel.
It is the schematic diagram of second of display module structure in display panel in the present invention, display pannel referring to Fig. 8, Fig. 8 It is made of multiple display modules.It include thin film transistor (TFT), intermediate insulating layer 8, pixel electrode 9, photoelectric material 10 in display module With public electrode 11.Pixel electrode 9 and the electrode 4 of the thin film transistor (TFT) are electrically connected by the through-hole on intermediate insulating layer 8. In the display panel of the present embodiment, the thin film transistor (TFT) is thin film transistor (TFT) described in Fig. 6.The thin film transistor (TFT) can be with For constituting the driving circuit in circuit, such as display panel.
Finally it should be noted that above embodiments are only presently preferred embodiments of the present invention, rather than the present invention is protected The limitation of range is protected, those skilled in the art should understand that, done within the spirit and principles of the present invention What modification, equivalent replacement or improvement etc., should all be included in the protection scope of the present invention.

Claims (23)

1. a kind of thin film transistor (TFT) characterized by comprising substrate and setting being made of metal oxide over the substrate Active layer；The active layer mutually adjoins with gate stack, and electrode is covered on the active layer partial region, the electrode Thickness is greater than diffusion length of the substance containing oxygen element in the electrode, further includes exhausted between the electrode and the active layer Edge layer is formed with the through-hole for being deep to the active layer on the insulating layer, is deposited with conductor in the through-hole, thus by described logical The electrode is drawn in hole, partial region of the electrode respectively with the active layer is electrically connected, and the insulating layer is in non-institute Stating the part under electrode covering is the first insulating layer, and the thickness of first insulating layer is less than the substance containing oxygen element in institute State the diffusion length in the first insulating layer；Annealed processing, region of the active layer under electrode covering are respectively formed Source region and drain region, the region under the non-electrode covering form channel region；The source region, the drain region and the channel region are mutual Connection, and is located at the both ends of the channel region, and the channel region mutually adjoins with the gate stack, the source region, described Joint face between drain region and the channel region is self-aligned to boundary of the electrode within the active layer projected area Vertical guide；The source region, the resistivity in the drain region are less than the resistivity of the channel region.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the source region, the drain region and the channel region Between the spacing of vertical guide on boundary within the active layer projected area of joint face and the electrode be less than and described have 100 times of active layer thickness.
3. thin film transistor (TFT) according to claim 1, which is characterized in that the channel region and the source region, the drain region Resistivity ratio be greater than 1000 times.
4. thin film transistor (TFT) according to claim 1, which is characterized in that the active layer includes one of following material Or a variety of combination: zinc oxide, nitrogen oxidation zinc, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, oxidation Zinc-tin, aluminium oxide tin, tin indium oxide, indium gallium zinc, indium tin zinc oxide, aluminum oxide indium tin zinc, zinc sulphide, barium titanate, metatitanic acid Strontium or lithium niobate.
5. thin film transistor (TFT) according to claim 1, which is characterized in that first insulating layer includes in following material One or more combinations: silica, silicon oxynitride, wherein the ratio of silicon nitride is less than 20% in the silicon oxynitride.
6. thin film transistor (TFT) according to claim 5, which is characterized in that first insulating layer with a thickness of 10 to 3000 Nanometer.
7. thin film transistor (TFT) according to claim 1, which is characterized in that the electrode with a thickness of described containing oxygen element Substance is between 2 to 100 times of diffusion length in the electrode.
8. thin film transistor (TFT) according to claim 1, which is characterized in that the electrode include one of following material or A variety of combination: titanium, molybdenum, aluminium, copper, silver, gold, nickel, tungsten, chromium, hafnium, platinum, iron, titanium-tungsten, molybdenum aluminium alloy, molybdenum-copper or copper Aluminium alloy.
9. thin film transistor (TFT) according to claim 8, which is characterized in that the electrode with a thickness of 10 to 3000 nanometers.
10. thin film transistor (TFT) according to claim 1, which is characterized in that the gate stack is arranged in the active layer Between the substrate.
11. thin film transistor (TFT) according to claim 1, which is characterized in that the active layer is arranged in the gate stack Between the substrate.
12. thin film transistor (TFT) according to claim 11, which is characterized in that the gate stack includes gate electrode and grid Pole insulating layer, the thickness of the gate electrode are less than the diffusion length of the substance containing oxygen element in the gate electrode, The thickness of the gate insulating layer is less than the diffusion length of the substance containing oxygen element in the gate insulating layer.
13. thin film transistor (TFT) according to claim 12, which is characterized in that the gate electrode includes in following material One or more combination: zinc oxide, tin indium oxide, aluminum zinc oxide, indium oxide aluminium or indium zinc oxide；The gate insulating layer packet Containing one of following material or a variety of combinations: silica, silicon oxynitride, wherein in the silicon oxynitride silicon nitride ratio Less than 20%.
14. thin film transistor (TFT) according to claim 13, which is characterized in that the gate electrode with a thickness of 10 to 3000 Nanometer；The gate insulating layer with a thickness of 10 to 3000 nanometers.
15. thin film transistor (TFT) according to claim 1, which is characterized in that the substance containing oxygen element include: oxygen, Ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide and above-mentioned substance plasma.
16. thin film transistor (TFT) according to claim 1, which is characterized in that the source region, the resistivity in the drain region are less than The resistivity of 10 ohmcms, the channel region is greater than 10 ohmcms.
17. a kind of display pannel, including multiple groups display module, which is characterized in that the display module include claim 1 to Any one of 16 thin film transistor (TFT)s.
18. a kind of manufacturing method of thin film transistor (TFT) characterized by comprising
Prepare a substrate；
In the gate stack that the substrate is arranged active layer and mutually adjoins with the active layer, the active layer is by metal oxygen Compound is constituted；
It is covered with electrode on the partial region of the active layer, the thickness of the electrode is made to be greater than the substance containing oxygen element in institute State the diffusion length in electrode；
It is provided with insulating layer between the electrode and the active layer, is formed on the insulating layer and is deep to the active layer Through-hole is deposited with conductor in the through-hole, thus by drawing the electrode in the through-hole, the electrode respectively with it is described active The partial region of layer is electrically connected, and makes part first insulating layer of the insulating layer under non-electrode covering, and described the The thickness of one insulating layer is less than the diffusion length of the substance containing oxygen element in first insulating layer；
It is made annealing treatment, region of the active layer under electrode covering is made to be respectively formed source region and drain region, it is non-described The lower region of electrode covering forms channel region, and the channel region mutually adjoins with the gate stack, the source region, the drain region and The channel region is connected with each other and is located at the both ends of the channel region, and makes the source region, the drain region and the channel Joint face is formed by annealing between area, which is self-aligned to the electrode within the active layer projected area The resistivity in the vertical guide on boundary, the source region and the drain region is less than the resistivity of the channel region.
19. the manufacturing method of thin film transistor (TFT) according to claim 18, which is characterized in that the source region, the drain region By the joint face formed and side of the electrode within the active layer projected area of annealing between the channel region The spacing of the vertical guide on boundary is less than 100 times of the active layer thickness.
20. the manufacturing method of thin film transistor (TFT) according to claim 18, which is characterized in that the annealing includes It is heated using heat, light, laser, microwave.
21. the manufacturing method of thin film transistor (TFT) according to claim 18, which is characterized in that it is described annealing be Under oxidizing atmosphere, for 10 seconds to 10 hours, temperature was between 100 DEG C and 600 DEG C.
22. the manufacturing method of thin film transistor (TFT) according to claim 21, which is characterized in that the oxidizing atmosphere includes: Oxygen, ozone, nitrous oxide, water, carbon dioxide and above-mentioned substance plasma.
23. a kind of display pannel, including multiple groups display module, which is characterized in that the display module includes claim 18 To the thin film transistor (TFT) of any one of 22 the method manufactures.
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