WO2017071662A1 - Thin film transistor, manufacturing method therefore, and display panel - Google Patents

Thin film transistor, manufacturing method therefore, and display panel Download PDF

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Publication number
WO2017071662A1
WO2017071662A1 PCT/CN2016/103836 CN2016103836W WO2017071662A1 WO 2017071662 A1 WO2017071662 A1 WO 2017071662A1 CN 2016103836 W CN2016103836 W CN 2016103836W WO 2017071662 A1 WO2017071662 A1 WO 2017071662A1
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Prior art keywords
electrode
thin film
film transistor
region
insulating layer
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PCT/CN2016/103836
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French (fr)
Chinese (zh)
Inventor
陆磊
王文
郭海成
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陆磊
王文
郭海成
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Publication of WO2017071662A1 publication Critical patent/WO2017071662A1/en

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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Definitions

  • the present invention relates to a metal oxide thin film transistor structure and a method of fabricating the same, and more particularly to a thin film transistor structure for use in a display panel.
  • a conventional metal oxide thin film transistor is used as an electrode by depositing a metal on an active layer.
  • a Schottky barrier is usually formed at the contact interface between the electrode and the active layer, so that the resistance value of the contact interface is high, thereby increasing the parasitic contact resistance of the thin film transistor, and the eigenstate metal oxide semiconductor is usually It is high resistivity, which causes problems with high resistivity source-drain resistance.
  • the existing solution is to reduce the resistivity of the source and drain regions by making the source and drain regions cumbersome, but this is usually at the expense of process stability and increased manufacturing costs. For example, the source and drain regions are catastrophically mixed with hydrogen ions into the source and drain regions by plasma treatment, but the entire process is not stable.
  • BCE Structure and etch-stop ES structures are the two main types of structures for back gate metal oxide thin film transistors.
  • a thin film transistor of a conventional back channel etch structure the exposed interface on the channel is damaged at the time of etching the electrode, thereby affecting the performance of the device.
  • etch stop layer on the channel region, this not only adds an additional lithography process, but also increases the fabrication cost.
  • the etch barrier device structure needs to extend the trench.
  • the length of the track and the length of the gate electrode, which expands the area of the thin film transistor, further greatly limits the resolution of the display, deviating from the high-resolution development trend of the display.
  • the advantages of the back-channel etched device structure are that it provides a simple process, lower fabrication cost, and smaller device size, while the device structure of the etch barrier provides better device performance and Improved device stability, but increases the area of the device and increases manufacturing costs. For this reason, the metal oxide thin film transistor manufacturing industry urgently needs a novel thin film transistor structure, which can simultaneously satisfy low cost, high performance, small size, and the like. Multiple requirements.
  • the technical problem to be solved by the present invention is to overcome the above-mentioned deficiencies of the prior art.
  • a high-performance metal oxide thin film transistor structure having a small source-drain region and low manufacturing cost is provided.
  • a thin film transistor provided by the present invention includes: a substrate and an active layer made of a metal oxide disposed on the substrate; the active layer is adjacent to the gate stack, The active layer portion is covered with an electrode, the thickness of the electrode is greater than the diffusion length of the oxygen-containing material in the electrode, and the insulating layer is further included between the electrode and the active layer; The portion not covered by the electrode is a first insulating layer, and the thickness of the first insulating layer is smaller than a diffusion length of the substance containing the oxygen element in the first insulating layer;
  • the regions covered by the electrodes respectively form a source region and a drain region, and the regions not covered by the electrodes form a channel region; the source region, the drain region and the channel region are connected to each other, and are respectively located in the At both ends of the channel region, the channel region is adjacent to the gate stack, and a connection surface between the source region, the drain region and the channel region is self-aligned with the electrode a vertical plane of a boundary within the projected area of the
  • a distance between a connection surface formed by annealing between the source region, the drain region and the channel region, and a vertical plane of a boundary of the electrode within a projected area of the active layer is smaller than 100 times the thickness of the active layer.
  • the resistivity ratio of the channel region to the source region and the drain region is greater than 1000 times.
  • the active layer includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, antimony oxide, indium zinc oxide, zinc tin oxide , aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium zinc tin zinc oxide, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
  • the first insulating layer comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the first insulating layer has a thickness of 10 to 3000 nm. [0011] the thickness of the electrode is between 2 and 100 times the diffusion length of the oxygen-containing substance in the electrode
  • the electrode comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, niobium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy , molybdenum-copper alloy or copper-aluminum alloy. Wherein the electrode has a thickness of 10 to 3000 nm.
  • the gate stack may be disposed between the active layer and the substrate;
  • the active layer is disposed between the gate stack and the substrate.
  • the gate stack includes a gate electrode and a gate insulating layer, the gate electrode has a thickness smaller than a diffusion length of the oxygen-containing material in the gate electrode, and the gate insulating layer The thickness of the layer is less than the diffusion length of the oxygen-containing material in the gate insulating layer.
  • the gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or indium zinc oxide; the gate insulating layer comprises one of the following materials Or a combination of a plurality of: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm.
  • the oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
  • the source region and the drain region have a resistivity of less than 10 ohm cm, and the channel region has a resistivity greater than 10 ohm cm.
  • the present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the thin film transistor described above.
  • the present invention also provides a method of manufacturing a thin film transistor, comprising:
  • an active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
  • a portion of the active layer is covered with an electrode such that the thickness of the electrode is greater than the diffusion length of the oxygen-containing material in the electrode;
  • An insulating layer is disposed between the electrode and the active layer, such that a portion of the insulating layer that is not covered by the electrode is a first insulating layer, and a thickness of the first insulating layer is smaller than Oxygen-containing substances in the house a diffusion length in the first insulating layer;
  • a distance between a connection surface formed by the annealing between the source region, the drain region, and the channel region, and a vertical plane of a boundary of the electrode within a projected area of the active layer Less than 100 times the thickness of the active layer.
  • the annealing treatment includes heating with heat, light, laser, or microwave.
  • the annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is between 100 ° C and 600 ° C
  • the oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above substances.
  • the present invention further provides a display panel comprising a plurality of sets of display modules, the display module comprising a thin film transistor prepared by the method described above.
  • the present invention Compared with the conventional thin film transistor structure, the present invention has the following advantages: First, the present scheme directly forms a source region and a drain region in the active layer by annealing, and maintains the same device as the back channel etch structure. The size, in turn, achieves high performance in etch barrier structure devices. The advantages of high performance and small size are taken into account, which is in line with the current development trend of displays, especially in the development of augmented reality and virtual reality. Secondly, the annealing reduces the resistivity of the source and drain regions, thereby reducing the parasitic contact resistance between the electrode and the active layer, and significantly improving the germanium performance of the thin film transistor.
  • the present invention has the advantages of high performance, small size, high reliability, low cost, and the like.
  • FIG. 1 is a cross-sectional view of a conventional back channel etched structure back gate thin film transistor.
  • FIG. 2 is a cross-sectional view of a conventional etch barrier structure back gate thin film transistor.
  • FIG 3 is a cross-sectional view showing a first embodiment of a thin film transistor structure of the present invention.
  • FIG. 4 is a cross-sectional view showing a second embodiment of a thin film transistor structure of the present invention.
  • FIG. 5 is a cross-sectional view showing a third embodiment of a thin film transistor structure of the present invention.
  • FIG. 6 is a cross-sectional view showing a fourth embodiment of a thin film transistor structure of the present invention.
  • FIG. 7 is a schematic diagram showing the structure of a first display module in the display panel of the present invention.
  • FIG. 8 is a schematic diagram showing the structure of a second display module in the display panel of the present invention.
  • FIG. 1 is a cross-sectional view of a conventional back channel etched structure back gate thin film transistor.
  • the thin film transistor includes: a substrate 1 a , an active layer 2 a disposed on the substrate 1 a .
  • a gate stack 3a is further provided between the active layer 2a and the substrate 1a.
  • the gate stack 3a includes a gate electrode 31a and a gate insulating layer 32a disposed between the gate electrode 31a and the active layer 2a.
  • the active layer 2a is covered with an electrode 4a.
  • a region where the active layer 2a is in contact with the electrode 4a forms a source region 21a and a drain region 23a, respectively, and a region where the active layer 2a contacts the non-electrode 4a forms a channel region 22a.
  • the channel region 22a is adjacent to the gate stack 3a, and the source region 21a and the drain region 23a are respectively located at both ends of the channel region 22a and are connected to the channel region 22a.
  • the off-state current of a thin film transistor is highly dependent on the resistivity and defect density of the channel region, and higher resistivity and less defect density result in lower off-state current and better device performance.
  • the zeta current of a thin film transistor is limited by the resistivity of the source and drain regions, and lower.
  • the resistivity of the source and drain regions is beneficial to reduce parasitic resistance and increase the zeta current.
  • the channel region 22a is damaged during the etching of the electrode 4a, which generates a large number of defect densities and greatly degrades the performance of the device.
  • the resulting defect density includes a conductive type defect density which lowers the resistivity of the channel region 22a, thereby greatly increasing the off-state current of the transistor operating current.
  • the intrinsic high resistivity source region 21a and the drain region 23a also lower the zeta current of the thin film transistor.
  • FIG. 2 is a cross-sectional view of a conventional etch barrier structure back gate thin film transistor.
  • the thin film transistor comprises: a substrate lb, an active layer 2b disposed on the substrate lb.
  • a gate stack 3b is also disposed between the active layer 2b and the substrate lb.
  • the gate stack 3b includes a gate electrode 31b and a gate insulating layer 32b disposed between the gate electrode 31b and the active layer 2b.
  • An etch stop layer 5 is provided on the active layer 2b. The etch stop layer 5 and the active layer 2b are covered with an electrode 4b.
  • a region where the active layer 2b is in contact with the electrode 4b forms a source region 21b and a drain region 23b, respectively, and a region where the active layer 2b contacts the non-electrode 4b forms a channel region 22b.
  • the channel region 22b is adjacent to the gate stack 3b, and the source region 21b and the drain region 23b are respectively located at both ends of the channel region 22b and are connected to the channel region 22b.
  • the channel region 22b is protected from damage by the etching process of the electrode 4b by etching the barrier layer 5, thereby avoiding introduction of defect density and reduction in resistivity in the channel region 22b.
  • the channel region 22b and the gate electrode 31b are correspondingly elongated to ensure that the channel region 22b is still connected through the source region 21b, the drain region 23b, and the electrode 4b.
  • the manufacturing cost is also increased because an additional one-step lithography step is required to pattern the etch barrier 5 .
  • the source region 21b and the drain region 23b of the intrinsic high resistivity in the etched barrier structure thin film transistor also lower the zeta current of the thin film transistor and affect the device performance.
  • FIG. 3 is a cross-sectional view showing a first embodiment of a thin film transistor structure of the present invention.
  • the thin film transistor in this embodiment adopts a back gate structure.
  • the thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; a gate stack 3 disposed between the active layer 2 and the substrate 1, and a gate stack 3 including a gate An electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; an upper surface of the active layer 2 is covered with an insulating layer 6, and a through hole deep to the active layer 2 is formed on the insulating layer 6.
  • a conductor is deposited in the through hole, thereby The electrode 4 is taken out from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively.
  • the substrate 1 includes, but is not limited to, the following materials: glass, polymer substrate, flexible material, and the like.
  • the active layer 2 includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, cerium oxide, indium zinc oxide, Zinc oxide tin, aluminum oxide tin
  • the substance containing the oxygen element when the thickness of the insulating layer or the conductor layer is smaller than the diffusion length of the substance containing the oxygen element in the insulating layer or the conductor layer, the substance containing the oxygen element can pass through the insulating layer during the annealing treatment or The conductor layer enters the active layer of the metal oxide to maintain, or even increase, the resistivity of the metal oxide.
  • the insulating layer or the conductor layer is an oxygen permeable layer; when an insulating layer or a conductor layer is thicker than the substance containing oxygen
  • the diffusion length ⁇ in the insulating layer, the insulating layer or the conductor layer can block the oxygen-containing material, thereby reducing the electrical resistivity of the metal oxide, and the insulating layer or the conductor layer is an oxygen-impermeable layer.
  • the oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
  • the thickness of the insulating layer 6 is smaller than the diffusion length of the substance containing the oxygen element in the insulating layer 6, and the substance containing the oxygen element can penetrate the insulating layer 6 in the annealing process, and thus the insulating layer 6 is an oxygen permeable layer.
  • the insulating layer 6 comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the insulating layer 6 has a thickness of 10 to 3,000 nm.
  • the insulating layer 6 has a thickness of between 200 nm and 500 nm.
  • the thickness of the electrode 4 is larger than the diffusion length of the substance containing the oxygen element in the electrode 4, and the electrode 4 can block the substance containing the oxygen element, and thus the electrode 4 is an oxygen-impermeable layer.
  • the thickness of the electrode 4 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the electrode 4.
  • the electrode 4 comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy Or copper alloy.
  • the electrode 4 has a thickness of 10 to 3000 nm.
  • the electrode 4 has a thickness between 200 nm and 500 nm.
  • the electrode 4 blocks the substance containing the oxygen element, and the resistivity of the active layer 2 in the region covered by the electrode 4 is lowered to form the source region 21 and the drain region 23.
  • the reduced resistivity of the source region 21 and the drain region 23 is advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the film.
  • the state of the transistor Contrary to the characteristics of the electrode 4, in the annealing treatment, the oxygen-containing substance can enter the active layer 2 through the insulating layer 6, so that the resistivity of the active layer 2 in the region covered by the non-electrode 4 is maintained or even improved. , a channel region 22 is formed.
  • the insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the insulating layer 6 can also protect the channel region 22 Protect the stability and reliability of thin film transistors from the external environment.
  • annealing treatment is used to reduce the resistivity of the source region 21 and the drain region 23, while maintaining or even increasing the channel region. 22 high resistivity.
  • the source region 21, the drain region 23, and the channel region 22 in the active layer 2 are connected to each other.
  • the junction surface formed by annealing is automatically aligned with the boundary of the electrode 4 covering the active layer 2 without any photolithography alignment process, which is similar to the source region formed by the existing silicon-based FET process.
  • the connection faces of the drain region and the channel region are automatically aligned to the gate electrode boundary. This self-alignment usually has a certain range of deviation.
  • the connection faces of the source region, the drain region and the channel region are self-aligned to the vertical plane of the boundary of the electrode within the projected area of the active layer, and the alignment deviation is less than 100 times the thickness of the active layer.
  • the projected area is the projection area in the vertical direction shown in the drawings in the specific embodiment.
  • the annealing treatment includes heating with heat, light, laser, or microwave.
  • the annealing treatment is carried out under an oxidizing atmosphere for 10 seconds to 10 hours and at a temperature between 100 ° C and 600 ° C.
  • the oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above.
  • the resistivity of the source region and the drain region obtained by annealing in the present invention is more complicated than that obtained by the impurity.
  • the rate is lower, and the low resistivity of the source and drain regions under electrode protection is more stable.
  • the process of the present invention is simpler and less expensive than conventionally cumbersome methods.
  • the present invention is not limited to the cumbersome one or more of the following impurities in the active layer: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminum or antimony. This does not prevent the formation of source, channel and drain regions of the device. Therefore, the present invention is fully compatible with the existing complicated processes and has high scalability.
  • the annealing treatment in the present invention also ensures or even improves the high resistivity of the channel region, thereby greatly reducing the off-state current of the thin film transistor, which is far lower than the current mainstream 1 0-13 amps per micron, even down to very low 10-18 amps per micron. More importantly, annealing also largely eliminates the defect density in the channel region, such as oxygen vacancy defect density, metal interstitial defect density, etc. These defect densities are widely present in metal oxides and are considered It is an important factor in reducing the performance and reliability of thin film transistors, but it is difficult to completely eliminate them in the conventional device structure.
  • the thin film transistor structure disclosed in the present invention greatly enhances the performance and long-term reliability of the thin film transistor.
  • the current-to-voltage ratio of metal oxide thin film transistors is greatly increased, even higher than 1011; the threshold voltage drift caused by the common hysteresis effect is suppressed to within 0.15 V; a certain voltage is applied to the gate electrode.
  • the drift of the threshold voltage is degraded to around 0 V.
  • the insulating layer covering the upper portion of the channel region can not only completely protect the channel region from the damage caused by electrode etching like the etch barrier layer, but also protect the thin film transistor from the external environment and enhance the film.
  • the environmental stability of the transistor For example, the problem of performance degradation such as threshold voltage drift caused by storing 10 small turns at 80 degrees Celsius and 80% relative humidity can be greatly improved by the structure of the thin film transistor of the present invention.
  • the present invention has many advantages over conventional thin film transistor structures, including: simpler manufacturing processes, lower fabrication costs, higher process scalability, better device performance, reliability, and Environmental stability.
  • FIG. 4 is a cross-sectional view showing a second embodiment of a thin film transistor structure of the present invention.
  • the thin film transistor has a top gate structure.
  • the thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; an oxygen permeable gate electrode 311 disposed over the active layer 2; and an oxygen permeable gate electrode 311 and an active layer disposed thereon
  • An oxygen permeable gate insulating layer 321 between the two; an active layer 2, an oxygen permeable gate insulating layer 321 and an oxygen permeable gate electrode 311 are covered with an insulating layer 6 and a deep to active layer is formed on the insulating layer 6.
  • a through hole is formed in the through hole, and a conductor is deposited in the through hole, thereby extracting the electrode 4 from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively.
  • the thickness of the oxygen permeable gate electrode 311 is smaller than the diffusion length of the oxygen-containing element in the gate electrode 31, and the oxygen-containing substance is transparent to the oxygen permeable gate during the annealing treatment.
  • the electrode 311, and thus the oxygen permeable gate electrode 311 is an oxygen permeable layer;
  • the oxygen permeable gate electrode 311 comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or Indium zinc oxide;
  • the oxygen permeable gate electrode 311 has a thickness of 10 to 3000 nm.
  • the oxygen permeable gate electrode 311 has a thickness of 200 nm to 500 nm. Between.
  • the thickness of the oxygen permeable gate insulating layer 321 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate insulating layer 321; the oxygen-containing substance is transparent in the annealing treatment.
  • the oxygen permeable gate insulating layer 321 is such that the oxygen permeable gate insulating layer 321 is an oxygen permeable layer; the oxygen permeable gate insulating layer 321 comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein The proportion of silicon nitride in the silicon oxynitride is less than 20%; and the thickness of the oxygen permeable gate insulating layer 321 is 10 to 3000 nm.
  • the oxygen permeable gate insulating layer 321 has a thickness of between 200 nm and 500 nm.
  • the electrode 4 blocks the substance containing the oxygen element, and the resistivity of the active layer 2 under the coverage of the electrode 4 is reduced to form the source region 21 and the drain. District 23.
  • the reduced resistivity of the source region 21 and the drain region 23 is advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the insulating layer 6, the oxygen permeable gate electrode 311 and the oxygen permeable gate insulating layer 321 are oxygen permeable layers.
  • the oxygen-containing substance can enter the active layer 2 through the insulating layer 6, the oxygen-permeable gate electrode 311, and the oxygen-permeable gate insulating layer 321, so that the active layer 2 is covered by the non-electrode 4
  • the resistivity of the region is maintained or even increased to form the channel region 22.
  • the insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the insulating layer 6 can also protect the channel region 22 Protect the stability and reliability of thin film transistors from the external environment.
  • FIG. 5 is a cross-sectional view showing a third embodiment of a thin film transistor structure of the present invention.
  • the thin film transistor has a back gate structure.
  • the thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; a gate stack 3 disposed between the active layer 2 and the substrate 1, and a gate stack 3 including a gate
  • the electrode 31 and the gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; the second insulating layer 61 and the first insulating layer 62 are respectively covered over different regions of the active layer 2, and the second insulating layer A through hole deep to the active layer 2 is formed on the 61, and a conductor is deposited in the through hole, so that the electrode 4 is taken out from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively.
  • the projected area of the second insulating layer 61 completely overlaps the projected area of the electrode 4, and the first insulating layer 62 is outside the projected area of
  • the thickness of the second insulating layer 61 is greater than the diffusion length of the substance containing the oxygen element in the second insulating layer 61, which can block the substance containing the oxygen element, and thus the second insulating layer 61 Is an oxygen-impermeable layer; preferably, the thickness of the second insulating layer 61 is the diffusion length of the oxygen-containing substance in the second insulating layer 61 Between 2 and 100 times.
  • the second insulating layer 61 is made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, wherein the proportion of silicon nitride in the silicon oxynitride is more than 20%.
  • the second insulating layer 61 has a thickness of 10 to 3000 nm. Preferably, the thickness of the second insulating layer 61 is between 200 nm and 500 nm.
  • the thickness of the first insulating layer 62 is smaller than the diffusion length of the oxygen-containing material in the first insulating layer 62, and the oxygen-containing substance is transparent in the annealing process.
  • the first insulating layer 62 is passed, and thus the first insulating layer 62 is an oxygen permeable layer.
  • the first insulating layer 62 includes a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the first insulating layer 62 has a thickness of 10 to 3000 nm.
  • the thickness of the first insulating layer 62 is between 200 nm and 50 nm.
  • the electrode 4 and the second insulating layer 61 collectively block the resistivity of the oxygen-containing substance, the region of the active layer 2 covered by the electrode 4 and the second insulating layer 61. It is reduced to form the source region 2 1 and the drain region 23 .
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can penetrate the first insulating layer 62 into the active layer 2, and thus the active layer 2 is on the non-electrode 4 and The resistivity of the region covered by the second insulating layer 61 is maintained or even increased to form the channel region 22.
  • the first insulating layer 62 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 62 can also The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • FIG. 6 is a cross-sectional view showing a fourth embodiment of the thin film transistor structure of the present invention.
  • the thin film transistor in this embodiment adopts a back gate structure.
  • the thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; a gate stack 3 disposed between the active layer 2 and the substrate 1, and a gate stack 3 including a gate
  • the electrode 31 and the gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; the second insulating layer 61 and the first insulating layer 62 are respectively covered over different regions of the active layer 2, and the second insulating layer A through hole deep to the active layer 2 is formed on the 61, and a conductor is deposited in the through hole, so that the electrode 4 is taken out from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively.
  • the projected area of the second insulating layer 61 completely overlaps the projected area of the electrode 4, and the first insulating layer 62 is outside the projected area of the electrode 4.
  • a third insulating layer 7 is also covered over the electrode 4, the second insulating layer 61 and the first insulating layer 62. Projection area of the second insulating layer 61, the electrode 4 The projected area and the projected area of the third insulating layer 7 completely overlap, and the first insulating layer 62 is outside the projected area of the electrode 4.
  • the third insulating layer 7, the electrode 4, and the second insulating layer 61 collectively block the substance containing the oxygen element, the active layer 2 is on the third insulating layer 7, the electrode 4, and The resistivity of the region covered by the second insulating layer 61 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer 2 through the first insulating layer 62, and thus the active layer 2 is on the non-third insulating layer 7, the electrode 4, and the second
  • the resistivity of the region covered by the insulating layer 61 is maintained or even increased to form the channel region 22.
  • the first insulating layer 62 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 62 can also protect The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • FIG. 7 is a schematic diagram showing the structure of a first display module in a display panel according to the present invention, wherein the display panel is composed of a plurality of display modules.
  • the display module includes a thin film transistor, an intermediate insulating layer 8, a pixel electrode 9, a photovoltaic material 10, and a common electrode 11.
  • the pixel electrode 9 and the electrode 4 of the thin film transistor are electrically connected through a via hole in the intermediate insulating layer 8.
  • Photoelectric material 10 includes, but is not limited to, liquid crystals, light emitting diodes, organic light emitting diodes, and quantum dot light emitting diodes.
  • the thin film transistor is the thin film transistor described in Fig. 3.
  • the thin film transistor can also be used to form a circuit such as a driver circuit in a display panel.
  • FIG. 8 is a schematic diagram showing the structure of a second display module in a display panel according to the present invention.
  • the display panel is composed of a plurality of display modules.
  • the display module includes a thin film transistor, an intermediate insulating layer 8, a pixel electrode 9, a photovoltaic material 10, and a common electrode 11.
  • the pixel electrode 9 and the electrode 4 of the thin film transistor are electrically connected through a via hole in the intermediate insulating layer 8.
  • the thin film transistor is the thin film transistor described in FIG.
  • the thin film transistor can also be used to form a circuit, such as a driver circuit in a display panel.

Abstract

A thin film transistor comprises a substrate (1), an active layer (2) composed of a metal oxides arranged on the substrate (1); the active layer (2) is adjacent to a grid stack (3); a partial region of the active layer (2) is covered with an electrode (4); an insulating layer (6) is further arranged between the electrode (4) and the active layer (2); a source region (21) and a drain region (23) are respectively formed in the region of the active layer (2) covered by the electrode (4); and a channel region (22) is formed in a region not covered by the electrode (4). The present invention also relates to a manufacturing method of the thin film transistor and a display panel having the thin film transistor. The thin film transistor has the small size of a traditional transistor having a back channel etched structure, and has better performance than such a traditional transistor having an etched barrier structure, in aspects such as low source/drain parasitic resistance, better on-state and off-state performance and enhanced reliability. The display panel having the thin film transistor has high performance, high reliability, low cost and complies with the development trend of display panels.

Description

一种薄膜晶体管及制造方法和显示器面板 技术领域  Thin film transistor and manufacturing method thereof and display panel
[0001] 本发明涉及一种金属氧化物薄膜晶体管结构及其制造方法， 尤其是用于显示器 面板中的薄膜晶体管结构。  [0001] The present invention relates to a metal oxide thin film transistor structure and a method of fabricating the same, and more particularly to a thin film transistor structure for use in a display panel.
背景技术  Background technique
[0002] 传统的金属氧化物薄膜晶体管通过在有源层上淀积金属来作为电极。 在电极和 有源层的接触界面处通常会形成肖特基势垒， 使得接触界面的电阻值很高， 进 而增大了薄膜晶体管的寄生接触电阻， 同吋本征态的金属氧化物半导体通常是 高电阻率的， 这会带来高电阻率的源漏电阻的问题。 现有的解决办法是通过对 源区、 漏区进行惨杂来降低源区、 漏区的电阻率， 但这通常以牺牲工艺稳定性 和增加制备成本为代价。 例如， 源漏区域通过等离子处理将氢离子惨杂到源区 、 漏区中， 但整个过程并不稳定。 其他惨杂物， 例如硼和磷， 则需要极为昂贵 的离子注入设备以及额外的激活过程。 为此， 在薄膜晶体管制造行业急需要一 种成本低廉、 制造工艺简单的方法来降低金属氧化物源漏区域的电阻率。  [0002] A conventional metal oxide thin film transistor is used as an electrode by depositing a metal on an active layer. A Schottky barrier is usually formed at the contact interface between the electrode and the active layer, so that the resistance value of the contact interface is high, thereby increasing the parasitic contact resistance of the thin film transistor, and the eigenstate metal oxide semiconductor is usually It is high resistivity, which causes problems with high resistivity source-drain resistance. The existing solution is to reduce the resistivity of the source and drain regions by making the source and drain regions cumbersome, but this is usually at the expense of process stability and increased manufacturing costs. For example, the source and drain regions are catastrophically mixed with hydrogen ions into the source and drain regions by plasma treatment, but the entire process is not stable. Other filths, such as boron and phosphorus, require extremely expensive ion implantation equipment and additional activation processes. For this reason, there is an urgent need in the thin film transistor manufacturing industry for a method of low cost and simple manufacturing process to reduce the resistivity of the metal oxide source and drain regions.
[0003] 另一方面， 背沟道刻蚀 （back-channel etched  [0003] On the other hand, back-channel etched
BCE) 结构和刻蚀阻挡层 （etch-stop ES) 结构是背栅金属氧化物薄膜晶体管的 两种主流结构。 在传统背沟道刻蚀结构的薄膜晶体管中， 暴露的沟道上界面会 在刻蚀电极的吋候受到损害， 进而影响到器件的性能。 虽然通过在沟道区上添 加一层刻蚀阻挡层能避免这样的损害， 但是这样不仅会增加一步额外的光刻过 程、 从而增加制备成本， 更重要的是刻蚀阻挡层器件结构需要延长沟道长度和 栅极电极的长度， 这样会扩大薄膜晶体管的面积、 进而极大地限制显示器的分 辨率的进一步提升， 背离了显示器的高分辨率发展趋势。 归纳而言， 背沟道刻 蚀的器件结构的优势在于提供了简单的工艺过程、 较低的制备成本和较小的器 件尺寸， 而刻蚀阻挡层的器件结构提供了更优的器件性能和改善的器件稳定性 ， 但扩大了器件的面积， 增加了制造成本。 为此， 金属氧化物薄膜晶体管制造 业急需一种新型的薄膜晶体管结构， 能够同吋满足低成本、 高性能、 小尺寸等 多重要求。 BCE) Structure and etch-stop ES structures are the two main types of structures for back gate metal oxide thin film transistors. In a thin film transistor of a conventional back channel etch structure, the exposed interface on the channel is damaged at the time of etching the electrode, thereby affecting the performance of the device. Although such damage can be avoided by adding an etch stop layer on the channel region, this not only adds an additional lithography process, but also increases the fabrication cost. More importantly, the etch barrier device structure needs to extend the trench. The length of the track and the length of the gate electrode, which expands the area of the thin film transistor, further greatly limits the resolution of the display, deviating from the high-resolution development trend of the display. In summary, the advantages of the back-channel etched device structure are that it provides a simple process, lower fabrication cost, and smaller device size, while the device structure of the etch barrier provides better device performance and Improved device stability, but increases the area of the device and increases manufacturing costs. For this reason, the metal oxide thin film transistor manufacturing industry urgently needs a novel thin film transistor structure, which can simultaneously satisfy low cost, high performance, small size, and the like. Multiple requirements.
技术问题  technical problem
[0004] 本发明所要解决的技术问题在于克服上述现有技术之不足， 首先提供一种源漏 区域电阻率小， 但制造成本低廉的高性能金属氧化物薄膜晶体管结构。  The technical problem to be solved by the present invention is to overcome the above-mentioned deficiencies of the prior art. First, a high-performance metal oxide thin film transistor structure having a small source-drain region and low manufacturing cost is provided.
问题的解决方案  Problem solution
技术解决方案  Technical solution
[0005] 本发明提供的一种薄膜晶体管， 包括： 衬底和设置在所述衬底上的由金属氧化 物构成的有源层； 所述有源层与栅极叠层相毗邻， 所述有源层部分区域上覆盖 有电极， 所述电极的厚度大于含氧元素的物质在所述电极中的扩散长度， 所述 电极与所述有源层之间还包括绝缘层； 所述绝缘层在非所述电极覆盖下的部分 为第一绝缘层， 所述第一绝缘层的厚度小于所述含氧元素的物质在所述第一绝 缘层中的扩散长度； 所述有源层在所述电极覆盖下的区域分别形成源区和漏区 ， 非所述电极覆盖下的区域形成沟道区； 所述源区、 所述漏区与所述沟道区相 互连接， 且分别位于所述沟道区的两端， 所述沟道区与所述栅极叠层相毗邻， 所述源区、 所述漏区与所述沟道区之间的连接面自对准于所述电极在所述有源 层投影面积之内的边界的铅垂面； 所述源区、 所述漏区的电阻率小于所述沟道 区的电阻率。  A thin film transistor provided by the present invention includes: a substrate and an active layer made of a metal oxide disposed on the substrate; the active layer is adjacent to the gate stack, The active layer portion is covered with an electrode, the thickness of the electrode is greater than the diffusion length of the oxygen-containing material in the electrode, and the insulating layer is further included between the electrode and the active layer; The portion not covered by the electrode is a first insulating layer, and the thickness of the first insulating layer is smaller than a diffusion length of the substance containing the oxygen element in the first insulating layer; The regions covered by the electrodes respectively form a source region and a drain region, and the regions not covered by the electrodes form a channel region; the source region, the drain region and the channel region are connected to each other, and are respectively located in the At both ends of the channel region, the channel region is adjacent to the gate stack, and a connection surface between the source region, the drain region and the channel region is self-aligned with the electrode a vertical plane of a boundary within the projected area of the active layer; The source region, the drain region resistivity smaller than the resistivity of the channel region.
[0006] 作为上述晶体管结构优选的方式：  [0006] As a preferred way of the above transistor structure:
[0007] 所述源区、 所述漏区与所述沟道区之间由退火形成的连接面和所述电极在所述 有源层投影面积之内的边界的铅垂面的间距小于所述有源层厚度的 100倍。  [0007] a distance between a connection surface formed by annealing between the source region, the drain region and the channel region, and a vertical plane of a boundary of the electrode within a projected area of the active layer is smaller than 100 times the thickness of the active layer.
[0008] 所述沟道区与所述源区、 所述漏区的电阻率比值大于 1000倍。 [0008] The resistivity ratio of the channel region to the source region and the drain region is greater than 1000 times.
[0009] 所述有源层包括以下材料中的一种或多种的组合： 氧化锌、 氮氧化锌、 氧化锡 、 氧化铟、 氧化镓、 氧化铜、 氧化铋、 氧化铟锌、 氧化锌锡、 氧化铝锡、 氧化 铟锡、 氧化铟镓锌、 氧化铟锡锌、 氧化铝铟锡锌、 硫化锌、 钛酸钡、 钛酸锶或 铌酸锂。 [0009] The active layer includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, antimony oxide, indium zinc oxide, zinc tin oxide , aluminum tin oxide, indium tin oxide, indium gallium zinc oxide, indium zinc tin zinc oxide, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
[0010] 所述第一绝缘层包括以下材料中的一种或多种的组合： 氧化硅、 氮氧化硅， 其 中所述氮氧化硅中氮化硅的比例小于 20%。 其中， 所述第一绝缘层的厚度为 10至 3000纳米。 [0011] 所述电极的厚度为所述含氧元素的物质在所述电极中扩散长度的 2至 100倍之间 [0010] The first insulating layer comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The first insulating layer has a thickness of 10 to 3000 nm. [0011] the thickness of the electrode is between 2 and 100 times the diffusion length of the oxygen-containing substance in the electrode
[0012] 所述电极包括以下材料中的一种或多种的组合： 钛、 钼、 铝、 铜、 银、 金、 镍 、 钨、 铬、 铪、 铂、 铁、 钛钨合金、 钼铝合金、 钼铜合金或铜铝合金。 其中， 所述电极的厚度为 10至 3000纳米。 [0012] The electrode comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, niobium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy , molybdenum-copper alloy or copper-aluminum alloy. Wherein the electrode has a thickness of 10 to 3000 nm.
[0013] 所述栅极叠层可设置在所述有源层与所述衬底之间； 或者， [0013] the gate stack may be disposed between the active layer and the substrate; or
[0014] 将所述有源层设置在所述栅极叠层和所述衬底之间。 进一步地， 所述栅极叠层 包括栅极电极和栅极绝缘层， 所述栅极电极的厚度小于所述含氧元素的物质在 所述栅极电极中的扩散长度， 所述栅极绝缘层的厚度小于所述含氧元素的物质 在所述栅极绝缘层中的扩散长度。 所述栅极电极包含以下材料中的一种或多种 的组合： 氧化锌、 氧化铟锡、 氧化铝锌、 氧化铟铝或氧化铟锌； 所述栅极绝缘 层包含以下材料中的一种或多种的组合： 氧化硅、 氮氧化硅， 其中所述氮氧化 硅中氮化硅的比例小于 20%。 所述栅极电极的厚度为 10至 3000纳米； 所述栅极绝 缘层的厚度为 10至 3000纳米。 [0014] The active layer is disposed between the gate stack and the substrate. Further, the gate stack includes a gate electrode and a gate insulating layer, the gate electrode has a thickness smaller than a diffusion length of the oxygen-containing material in the gate electrode, and the gate insulating layer The thickness of the layer is less than the diffusion length of the oxygen-containing material in the gate insulating layer. The gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or indium zinc oxide; the gate insulating layer comprises one of the following materials Or a combination of a plurality of: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm.
[0015] 所述含氧元素的物质包括： 氧气、 臭氧、 一氧化二氮、 水、 双氧水、 二氧化碳 和上述物质的等离子体。 [0015] The oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
[0016] 所述源区、 漏区的电阻率小于 10欧姆厘米， 所述沟道区的电阻率大于 10欧姆厘 米。 [0016] The source region and the drain region have a resistivity of less than 10 ohm cm, and the channel region has a resistivity greater than 10 ohm cm.
[0017] 本发明还提供了一种显示器面板， 包括多组显示模块， 所述显示模块包含上述 所述的薄膜晶体管。  [0017] The present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the thin film transistor described above.
[0018] 本发明还提供了一种薄膜晶体管的制造方法， 包括： [0018] The present invention also provides a method of manufacturing a thin film transistor, comprising:
[0019] 准备一个衬底； [0019] preparing a substrate;
[0020] 在所述衬底之上设置有源层和与所述有源层相毗邻的栅极叠层， 所述有源层由 金属氧化物构成；  [0020] an active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
[0021] 在所述有源层的部分区域上覆盖有电极， 使所述电极的厚度大于含氧元素的物 质在所述电极中的扩散长度；  [0021] a portion of the active layer is covered with an electrode such that the thickness of the electrode is greater than the diffusion length of the oxygen-containing material in the electrode;
[0022] 在所述电极与所述有源层之间设置有绝缘层， 使所述绝缘层在非所述电极覆盖 下的部分为第一绝缘层， 所述第一绝缘层的厚度小于所述含氧元素的物质在所 述第一绝缘层中的扩散长度； [0022] An insulating layer is disposed between the electrode and the active layer, such that a portion of the insulating layer that is not covered by the electrode is a first insulating layer, and a thickness of the first insulating layer is smaller than Oxygen-containing substances in the house a diffusion length in the first insulating layer;
[0023] 进行退火处理， 使所述有源层在所述电极覆盖下的区域分别形成源区和漏区， 非所述电极覆盖下的区域形成沟道区， 所述沟道区与所述栅极叠层相毗邻， 所 述源区、 所述漏区与所述沟道区相互连接、 且分别位于所述沟道区的两端， 且 使所述源区、 所述漏区与所述沟道区之间由退火形成连接面， 该连接面自对准 于所述电极在所述有源层投影面积之内的边界的铅垂面， 所述源区和所述漏区 的电阻率小于所述沟道区的电阻率。  [0023] performing an annealing process to form a source region and a drain region respectively in a region under the electrode covering of the active layer, and a channel region in a region not covered by the electrode, the channel region and the channel region The gate stacks are adjacent to each other, and the source region, the drain region and the channel region are connected to each other and respectively located at two ends of the channel region, and the source region, the drain region and the drain region are Forming a connection surface between the channel regions by annealing, the connection surface being self-aligned to a vertical surface of a boundary of the electrode within a projected area of the active layer, resistance of the source region and the drain region The rate is less than the resistivity of the channel region.
[0024] 作为本发明上述所述的晶体管制作方法的优选方式：  [0024] A preferred mode of the transistor fabrication method described above in the present invention:
[0025] 所述源区、 所述漏区与所述沟道区之间由所述退火形成的连接面和所述电极在 所述有源层投影面积之内的边界的铅垂面的间距小于所述有源层厚度的 100倍。  [0025] a distance between a connection surface formed by the annealing between the source region, the drain region, and the channel region, and a vertical plane of a boundary of the electrode within a projected area of the active layer Less than 100 times the thickness of the active layer.
[0026] 所述退火处理包括利用热、 光、 激光、 微波进行加热。 [ annealing] The annealing treatment includes heating with heat, light, laser, or microwave.
[0027] 所述退火处理是在氧化气氛下， 持续 10秒至 10小吋， 温度在 100°C和 600°C之间  [0027] The annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is between 100 ° C and 600 ° C
[0028] 所述氧化气氛包括： 氧气、 臭氧、 一氧化二氮、 水、 二氧化碳和上述物质的等 离子体。 [0028] The oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above substances.
[0029] 根据上述方法， 本发明还提供了一种显示器面板， 包括多组显示模块， 所述显 示模块包含采用上述所述方法制备的薄膜晶体管。  [0029] According to the above method, the present invention further provides a display panel comprising a plurality of sets of display modules, the display module comprising a thin film transistor prepared by the method described above.
发明的有益效果  Advantageous effects of the invention
有益效果  Beneficial effect
[0030] 相对于传统的薄膜晶体管结构， 本发明具有以下优点： 首先， 本方案直接通过 退火在有源层中形成了源区、 漏区， 既保持了和背沟道刻蚀结构一样的器件尺 寸， 又实现了刻蚀阻挡层结构器件的高性能。 同吋兼顾了高性能和小尺寸的优 点， 非常符合目前显示器的发展趋势， 特别是在增强现实、 虚拟现实方面的发 展应用。 其次， 退火减小了源漏区域的电阻率， 进而降低了电极与有源层之间 的寄生接触电阻， 显著提升了薄膜晶体管的幵态性能。 同吋， 由于退火还保持 甚至提高了沟道区的高电阻率， 从而显著地降低了薄膜晶体管的关态电流。 更 重要的是， 退火会在很大程度上消除沟道区中的缺陷密度， 极大地提升器件的 可靠性。 自然引入的沟道区上方的第一绝缘层保护薄膜晶体管的沟道区免受外 界环境的影响， 器件的环境可靠性能得到进一步加强。 本发明直接以电极覆盖 部分有源层区域， 通过退火来降低电极覆盖下的源区、 漏区的电阻率， 在省略 了传统半导体工艺中的惨杂步骤和光刻步骤， 节省了制备成本的同吋， 保证了 源漏区域的低电阻率的稳定性。 因此， 本发明， 兼具高性能、 小尺寸、 高可靠 性、 低成本等优点。 [0030] Compared with the conventional thin film transistor structure, the present invention has the following advantages: First, the present scheme directly forms a source region and a drain region in the active layer by annealing, and maintains the same device as the back channel etch structure. The size, in turn, achieves high performance in etch barrier structure devices. The advantages of high performance and small size are taken into account, which is in line with the current development trend of displays, especially in the development of augmented reality and virtual reality. Secondly, the annealing reduces the resistivity of the source and drain regions, thereby reducing the parasitic contact resistance between the electrode and the active layer, and significantly improving the germanium performance of the thin film transistor. At the same time, since the annealing maintains or even increases the high resistivity of the channel region, the off-state current of the thin film transistor is remarkably lowered. More importantly, annealing greatly eliminates the defect density in the channel region and greatly improves the reliability of the device. The first insulating layer above the naturally introduced channel region protects the channel region of the thin film transistor from the outside The environmental reliability of the device can be further enhanced by the influence of the environmental environment. The invention directly covers a portion of the active layer region with an electrode, and reduces the resistivity of the source region and the drain region under the electrode coverage by annealing, omitting the complicated steps and the photolithography step in the conventional semiconductor process, thereby saving the preparation cost. At the same time, the stability of the low resistivity of the source and drain regions is ensured. Therefore, the present invention has the advantages of high performance, small size, high reliability, low cost, and the like.
对附图的简要说明  Brief description of the drawing
附图说明  DRAWINGS
[0031] 图 1为传统背沟道刻蚀结构背栅薄膜晶体管的剖视图。  1 is a cross-sectional view of a conventional back channel etched structure back gate thin film transistor.
[0032] 图 2为传统刻蚀阻挡层结构背栅薄膜晶体管的剖视图。 2 is a cross-sectional view of a conventional etch barrier structure back gate thin film transistor.
[0033] 图 3为本发明中薄膜晶体管结构第一种实施例的剖视图。 3 is a cross-sectional view showing a first embodiment of a thin film transistor structure of the present invention.
[0034] 图 4为本发明中薄膜晶体管结构第二种实施例的剖视图。 4 is a cross-sectional view showing a second embodiment of a thin film transistor structure of the present invention.
[0035] 图 5为本发明中薄膜晶体管结构第三种实施例的剖视图。 5 is a cross-sectional view showing a third embodiment of a thin film transistor structure of the present invention.
[0036] 图 6为本发明中薄膜晶体管结构第四种实施例的剖视图。 6 is a cross-sectional view showing a fourth embodiment of a thin film transistor structure of the present invention.
[0037] 图 7为本发明中显示面板中第一种显示模块结构的示意图。 7 is a schematic diagram showing the structure of a first display module in the display panel of the present invention.
[0038] 图 8为本发明中显示面板中第二种显示模块结构的示意图。 8 is a schematic diagram showing the structure of a second display module in the display panel of the present invention.
本发明的实施方式 Embodiments of the invention
[0039] 参照图 1， 图 1为传统背沟道刻蚀结构背栅薄膜晶体管的剖视图。 其中， 薄膜晶 体管包括： 衬底 la、 设置在衬底 la上的有源层 2a。 有源层 2a与衬底 la之间还设置 有栅极叠层 3a。 栅极叠层 3a包括栅极电极 31a和设置在栅极电极 31a和有源层 2a之 间的栅极绝缘层 32a。 有源层 2a之上覆盖有电极 4a。 有源层 2a与电极 4a相接触的 区域分别形成源区 21a、 漏区 23a， 有源层 2a与非电极 4a相接触的区域形成沟道区 22a。 其中， 沟道区 22a与栅极叠层 3a相毗邻， 而源区 21a、 漏区 23a分别位于沟道 区 22a的两端， 并与沟道区 22a相连接。 在薄膜晶体管工作过程中， 通过对栅极电 极施加一定的电压， 能够改变沟道区的电阻率， 进而控制通过沟道区的电流， 从而实现薄膜晶体管的幵关。 薄膜晶体管的关态电流很大程度上取决于沟道区 的电阻率和缺陷密度， 更高的电阻率和更少的缺陷密度带来更低的关态电流和 更好的器件性能。 薄膜晶体管的幵态电流受限于源区、 漏区的电阻率， 更低的 源区、 漏区的电阻率有利于降低寄生电阻， 提高幵态电流。 对于背沟道刻蚀结 构背栅薄膜晶体管， 其沟道区 22a在刻蚀电极 4a的过程中会受到损害， 产生大量 缺陷密度， 大大降低器件的性能。 产生的缺陷密度包括导电类缺陷密度， 其会 降低沟道区 22a的电阻率， 从而极大了晶体管工作电流的关态电流。 另一方面， 本征高电阻率的源区 21a、 漏区 23a也会降低薄膜晶体管的幵态电流。 Referring to FIG. 1, FIG. 1 is a cross-sectional view of a conventional back channel etched structure back gate thin film transistor. The thin film transistor includes: a substrate 1 a , an active layer 2 a disposed on the substrate 1 a . A gate stack 3a is further provided between the active layer 2a and the substrate 1a. The gate stack 3a includes a gate electrode 31a and a gate insulating layer 32a disposed between the gate electrode 31a and the active layer 2a. The active layer 2a is covered with an electrode 4a. A region where the active layer 2a is in contact with the electrode 4a forms a source region 21a and a drain region 23a, respectively, and a region where the active layer 2a contacts the non-electrode 4a forms a channel region 22a. The channel region 22a is adjacent to the gate stack 3a, and the source region 21a and the drain region 23a are respectively located at both ends of the channel region 22a and are connected to the channel region 22a. During the operation of the thin film transistor, by applying a certain voltage to the gate electrode, the resistivity of the channel region can be changed, and the current passing through the channel region can be controlled, thereby achieving the switching of the thin film transistor. The off-state current of a thin film transistor is highly dependent on the resistivity and defect density of the channel region, and higher resistivity and less defect density result in lower off-state current and better device performance. The zeta current of a thin film transistor is limited by the resistivity of the source and drain regions, and lower. The resistivity of the source and drain regions is beneficial to reduce parasitic resistance and increase the zeta current. For the back channel etched structure back gate thin film transistor, the channel region 22a is damaged during the etching of the electrode 4a, which generates a large number of defect densities and greatly degrades the performance of the device. The resulting defect density includes a conductive type defect density which lowers the resistivity of the channel region 22a, thereby greatly increasing the off-state current of the transistor operating current. On the other hand, the intrinsic high resistivity source region 21a and the drain region 23a also lower the zeta current of the thin film transistor.
[0040] 参照图 2， 图 2为传统刻蚀阻挡层结构背栅薄膜晶体管的剖视图。 其中， 薄膜晶 体管包括： 衬底 lb、 设置在衬底 lb上的有源层 2b。 有源层 2b与衬底 lb之间还设 置有栅极叠层 3b。 栅极叠层 3b包括栅极电极 31b和设置在栅极电极 31b和有源层 2 b之间的栅极绝缘层 32b。 在有源层 2b上设置有刻蚀阻挡层 5。 刻蚀阻挡层 5和有 源层 2b之上覆盖有电极 4b。 有源层 2b与电极 4b相接触的区域分别形成源区 21b、 漏区 23b， 有源层 2b与非电极 4b相接触的区域形成沟道区 22b。 其中， 沟道区 22b 与栅极叠层 3b相毗邻， 而源区 21b、 漏区 23b分别位于沟道区 22b的两端， 并与沟 道区 22b相连接。 通过刻蚀阻挡层 5保护沟道区 22b免受电极 4b刻蚀过程所带来的 损害， 从而避免在沟道区 22b引入缺陷密度和降低电阻率。 但是因为刻蚀阻挡层 5的引入， 沟道区 22b和栅极电极 31b相应地要有所延长， 以保证沟道区 22b依然 通过源区 21b、 漏区 23b和电极 4b相连接。 这样极大地增加了薄膜晶体管的面积 ， 背离了薄膜晶体管小型化的发展趋势。 同吋， 因需要额外的一步光刻步骤来 图形化刻蚀阻挡层 5， 制备成本也会增加。 同样地， 在刻蚀阻挡层结构薄膜晶体 管中本征高电阻率的源区 21b、 漏区 23b也会降低薄膜晶体管的幵态电流， 影响 器件性能。 Referring to FIG. 2, FIG. 2 is a cross-sectional view of a conventional etch barrier structure back gate thin film transistor. Wherein the thin film transistor comprises: a substrate lb, an active layer 2b disposed on the substrate lb. A gate stack 3b is also disposed between the active layer 2b and the substrate lb. The gate stack 3b includes a gate electrode 31b and a gate insulating layer 32b disposed between the gate electrode 31b and the active layer 2b. An etch stop layer 5 is provided on the active layer 2b. The etch stop layer 5 and the active layer 2b are covered with an electrode 4b. A region where the active layer 2b is in contact with the electrode 4b forms a source region 21b and a drain region 23b, respectively, and a region where the active layer 2b contacts the non-electrode 4b forms a channel region 22b. The channel region 22b is adjacent to the gate stack 3b, and the source region 21b and the drain region 23b are respectively located at both ends of the channel region 22b and are connected to the channel region 22b. The channel region 22b is protected from damage by the etching process of the electrode 4b by etching the barrier layer 5, thereby avoiding introduction of defect density and reduction in resistivity in the channel region 22b. However, due to the introduction of the etch barrier layer 5, the channel region 22b and the gate electrode 31b are correspondingly elongated to ensure that the channel region 22b is still connected through the source region 21b, the drain region 23b, and the electrode 4b. This greatly increases the area of the thin film transistor and deviates from the trend of miniaturization of the thin film transistor. At the same time, the manufacturing cost is also increased because an additional one-step lithography step is required to pattern the etch barrier 5 . Similarly, the source region 21b and the drain region 23b of the intrinsic high resistivity in the etched barrier structure thin film transistor also lower the zeta current of the thin film transistor and affect the device performance.
[0041] 下面结合附图及实施例详细描述本发明。 应当理解， 此处所描述的具体实施例 为非限制性示例实施例， 且附图示出的特征不是必须按比例绘制。 所给出的示 例仅旨在有利于解释本发明， 不应被理解为对本发明的限定。  The present invention will be described in detail below with reference to the accompanying drawings and embodiments. It is understood that the specific embodiments described herein are non-limiting exemplary embodiments, and the features of the drawings are not necessarily to scale. The examples are given only to facilitate the explanation of the invention and are not to be construed as limiting the invention.
[0042] 参照图 3， 图 3为本发明中薄膜晶体管结构第一种实施例的剖视图。 本实施例中 薄膜晶体管采用背栅结构。 其中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的 有源层 2; 有源层 2与衬底 1之间还设置有栅极叠层 3， 栅极叠层 3则包括栅极电极 31和设置在栅极电极 31和有源层 2之间的栅极绝缘层 32; 有源层 2的上方覆盖有 绝缘层 6， 绝缘层 6上形成有深至有源层 2的通孔， 所述通孔内淀积有导体， 从而 由所述通孔中引出电极 4， 电极 4分别与有源层 2的部分区域相电连接。 Referring to FIG. 3, FIG. 3 is a cross-sectional view showing a first embodiment of a thin film transistor structure of the present invention. The thin film transistor in this embodiment adopts a back gate structure. The thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; a gate stack 3 disposed between the active layer 2 and the substrate 1, and a gate stack 3 including a gate An electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; an upper surface of the active layer 2 is covered with an insulating layer 6, and a through hole deep to the active layer 2 is formed on the insulating layer 6. a conductor is deposited in the through hole, thereby The electrode 4 is taken out from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively.
[0043] 参照图 3， 衬底 1包括但不限于以下材料： 玻璃、 聚合物衬底、 柔性材料等。 Referring to FIG. 3, the substrate 1 includes, but is not limited to, the following materials: glass, polymer substrate, flexible material, and the like.
[0044] 参照图 3， 有源层 2包括以下材料中的一种或多种的组合： 氧化锌、 氮氧化锌、 氧化锡、 氧化铟、 氧化镓、 氧化铜、 氧化铋、 氧化铟锌、 氧化锌锡、 氧化铝锡[0044] Referring to FIG. 3, the active layer 2 includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, cerium oxide, indium zinc oxide, Zinc oxide tin, aluminum oxide tin
、 氧化铟锡、 氧化铟镓锌、 氧化铟锡锌、 氧化铝铟锡锌、 硫化锌、 钛酸钡、 钛 酸锶或铌酸锂。 Indium tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
[0045] 本发明中， 当绝缘层或导体层的厚度小于含氧元素的物质在该绝缘层或导体层 中的扩散长度吋， 含氧元素的物质能在退火处理中透过该绝缘层或导体层进入 金属氧化物有源层， 从而保持、 甚至提高金属氧化物的电阻率， 此吋该绝缘层 或导体层是透氧层； 当一个绝缘层或导体层的厚度大于含氧元素的物质在该绝 缘层中的扩散长度吋， 该绝缘层或导体层能阻挡含氧元素的物质， 从而降低金 属氧化物的电阻率， 此吋该绝缘层或导体层是不透氧层。  [0045] In the present invention, when the thickness of the insulating layer or the conductor layer is smaller than the diffusion length of the substance containing the oxygen element in the insulating layer or the conductor layer, the substance containing the oxygen element can pass through the insulating layer during the annealing treatment or The conductor layer enters the active layer of the metal oxide to maintain, or even increase, the resistivity of the metal oxide. The insulating layer or the conductor layer is an oxygen permeable layer; when an insulating layer or a conductor layer is thicker than the substance containing oxygen The diffusion length 吋 in the insulating layer, the insulating layer or the conductor layer can block the oxygen-containing material, thereby reducing the electrical resistivity of the metal oxide, and the insulating layer or the conductor layer is an oxygen-impermeable layer.
[0046] 所述含氧元素的物质包括： 氧气、 臭氧、 一氧化二氮、 水、 双氧水、 二氧化碳 和上述物质的等离子体。  [0046] The oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
[0047] 参照图 3， 绝缘层 6的厚度小于所述含氧元素的物质在绝缘层 6中的扩散长度， 所述含氧元素的物质在退火处理中能够透过绝缘层 6， 因而绝缘层 6是透氧层。 绝缘层 6包括以下材料中的一种或多种的组合： 氧化硅、 氮氧化硅， 其中， 所述 氮氧化硅中氮化硅的比例小于 20%。 绝缘层 6的厚度为 10至 3000纳米。 优选地， 绝缘层 6的厚度在 200纳米到 500纳米之间。  Referring to FIG. 3, the thickness of the insulating layer 6 is smaller than the diffusion length of the substance containing the oxygen element in the insulating layer 6, and the substance containing the oxygen element can penetrate the insulating layer 6 in the annealing process, and thus the insulating layer 6 is an oxygen permeable layer. The insulating layer 6 comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The insulating layer 6 has a thickness of 10 to 3,000 nm. Preferably, the insulating layer 6 has a thickness of between 200 nm and 500 nm.
[0048] 参照图 3， 电极 4的厚度大于所述含氧元素的物质在电极 4中的扩散长度， 电极 4 能阻挡所述含氧元素的物质， 因而电极 4是不透氧层。 优选地， 电极 4的厚度为 所述含氧元素的物质在电极 4中扩散长度的 2至 100倍之间。 电极 4包括以下材料 中的一种或多种的组合： 钛、 钼、 铝、 铜、 银、 金、 镍、 钨、 铬、 铪、 铂、 铁 、 钛钨合金、 钼铝合金、 钼铜合金或铜铝合金。 电极 4的厚度为 10至 3000纳米。 优选地， 电极 4的厚度在 200纳米到 500纳米之间。  Referring to FIG. 3, the thickness of the electrode 4 is larger than the diffusion length of the substance containing the oxygen element in the electrode 4, and the electrode 4 can block the substance containing the oxygen element, and thus the electrode 4 is an oxygen-impermeable layer. Preferably, the thickness of the electrode 4 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the electrode 4. The electrode 4 comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy Or copper alloy. The electrode 4 has a thickness of 10 to 3000 nm. Preferably, the electrode 4 has a thickness between 200 nm and 500 nm.
[0049] 参照图 3， 退火处理中， 电极 4阻挡了所述含氧元素的物质， 有源层 2在电极 4覆 盖下的区域的电阻率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 2 3的电阻率有利于降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜 晶体管的幵态性能。 与电极 4的特性相反， 退火处理中， 所述含氧元素的物质能 够透过绝缘层 6进入有源层 2， 因此有源层 2在非电极 4覆盖下的区域的电阻率得 到保持甚至提高， 形成沟道区 22。 在沟道区 22上方的绝缘层 6还能提高沟道区 22 的电阻率、 降低沟道区 22的缺陷密度， 从而改善薄膜晶体管的关态特性， 并且 绝缘层 6还能保护沟道区 22免受外界环境的影响， 提高薄膜晶体管的稳定性和可 靠性。 Referring to FIG. 3, in the annealing treatment, the electrode 4 blocks the substance containing the oxygen element, and the resistivity of the active layer 2 in the region covered by the electrode 4 is lowered to form the source region 21 and the drain region 23. The reduced resistivity of the source region 21 and the drain region 23 is advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the film. The state of the transistor. Contrary to the characteristics of the electrode 4, in the annealing treatment, the oxygen-containing substance can enter the active layer 2 through the insulating layer 6, so that the resistivity of the active layer 2 in the region covered by the non-electrode 4 is maintained or even improved. , a channel region 22 is formed. The insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the insulating layer 6 can also protect the channel region 22 Protect the stability and reliability of thin film transistors from the external environment.
[0050] 参照图 3， 本发明中， 通过在有源层 2部分区域上方覆盖电极 4， 继而用退火处 理来降低源区 21、 漏区 23的电阻率， 同吋保持、 甚至提高沟道区 22的高电阻率 。 有源层 2中的源区 21、 漏区 23和沟道区 22相互连接。 其退火形成的连接面无需 借助任何光刻对准工艺， 而自动对准于覆盖有源层 2的电极 4的边界， 这类似于 现有硅基场效应晶体管工艺中， 惨杂形成的源区、 漏区和沟道区的连接面自动 对准于栅极电极边界。 这种自对准通常都存在一定的偏差范围。 本发明中， 源 区、 漏区和沟道区的连接面自对准于电极在有源层投影面积之内的边界的铅垂 面， 其对准的偏差小于有源层厚度的 100倍。  Referring to FIG. 3, in the present invention, by covering the electrode 4 over a partial region of the active layer 2, annealing treatment is used to reduce the resistivity of the source region 21 and the drain region 23, while maintaining or even increasing the channel region. 22 high resistivity. The source region 21, the drain region 23, and the channel region 22 in the active layer 2 are connected to each other. The junction surface formed by annealing is automatically aligned with the boundary of the electrode 4 covering the active layer 2 without any photolithography alignment process, which is similar to the source region formed by the existing silicon-based FET process. The connection faces of the drain region and the channel region are automatically aligned to the gate electrode boundary. This self-alignment usually has a certain range of deviation. In the present invention, the connection faces of the source region, the drain region and the channel region are self-aligned to the vertical plane of the boundary of the electrode within the projected area of the active layer, and the alignment deviation is less than 100 times the thickness of the active layer.
[0051] 在本发明中， 所述的投影面积为具体实施例中的附图所示的垂直方向的投影面 积。  In the present invention, the projected area is the projection area in the vertical direction shown in the drawings in the specific embodiment.
[0052] 在本发明中， 所述退火处理包括利用热、 光、 激光、 微波进行加热。 所述退火 处理是在氧化气氛下， 持续 10秒至 10小吋， 温度在 100°C和 600°C之间。 所述氧化 气氛包括： 氧气、 臭氧、 一氧化二氮、 水、 二氧化碳和上述物质的等离子体。  [0052] In the present invention, the annealing treatment includes heating with heat, light, laser, or microwave. The annealing treatment is carried out under an oxidizing atmosphere for 10 seconds to 10 hours and at a temperature between 100 ° C and 600 ° C. The oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above.
[0053] 相对于传统的通过对源区和漏区进行惨杂的方式来降低源区、 漏区的电阻率， 本发明中退火所得的源区、 漏区的电阻率比惨杂所得的电阻率更低， 且电极保 护下的源区、 漏区的低电阻率更稳定。 相对于传统惨杂方式， 本发明的工艺更 简单、 成本也更低。 但本发明不限制惨杂， 有源层中可以惨入以下一种或多种 杂质： 氢、 氮、 氟、 硼、 磷、 砷、 硅、 铟、 铝或锑。 这不妨碍器件的源区、 沟 道区和漏区的形成。 也因此， 本发明和现有惨杂工艺完全兼容， 具有高扩展性  [0053] Compared with the conventional method of reducing the source region and the drain region in a complicated manner to reduce the resistivity of the source region and the drain region, the resistivity of the source region and the drain region obtained by annealing in the present invention is more complicated than that obtained by the impurity. The rate is lower, and the low resistivity of the source and drain regions under electrode protection is more stable. The process of the present invention is simpler and less expensive than conventionally cumbersome methods. However, the present invention is not limited to the cumbersome one or more of the following impurities in the active layer: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminum or antimony. This does not prevent the formation of source, channel and drain regions of the device. Therefore, the present invention is fully compatible with the existing complicated processes and has high scalability.
[0054] 相对于传统薄膜晶体管的方法， 本发明中退火处理还保证了、 甚至提高了沟道 区的高电阻率， 从而极大地降低了薄膜晶体管的关态电流， 远低于目前主流的 1 0-13安每微米， 甚至降低到极低的 10-18安每微米。 更重要的是， 退火还在很大 程度上消除了沟道区中的缺陷密度， 比如， 氧空位缺陷密度、 金属填隙缺陷密 度等， 这些缺陷密度广泛地存在于金属氧化物中， 被认为是降低薄膜晶体管的 性能和可靠性的重要因素， 但在传统的器件结构中又很难彻底地消除。 因为消 除了这些缺陷密度， 本发明中所公幵的薄膜晶体管结构极大地增强了薄膜晶体 管的性能和长期可靠性。 比如， 金属氧化物薄膜晶体管的电流幵关比极大地提 高、 甚至高于 1011 ; 常见的回滞效应引起的阈值电压漂移被抑制到 0.15 V之内； 栅极电极上施加一定的电压吋所产生的阈值电压的漂移退化消除到 0 V左右。 其 次， 沟道区上方覆盖的绝缘层不仅能够像刻蚀阻挡层一样完全保护沟道区免受 电极刻蚀带来的损害， 还能够很好地保护薄膜晶体管免受外界环境的影响、 增 强薄膜晶体管的环境稳定性。 比如， 在 80摄氏度、 80%相对湿度下保存 10个小吋 所引起的阈值电压漂移等性能退化的问题， 通过本发明中薄膜晶体管结构可以 得到大大改善。 Compared with the conventional thin film transistor method, the annealing treatment in the present invention also ensures or even improves the high resistivity of the channel region, thereby greatly reducing the off-state current of the thin film transistor, which is far lower than the current mainstream 1 0-13 amps per micron, even down to very low 10-18 amps per micron. More importantly, annealing also largely eliminates the defect density in the channel region, such as oxygen vacancy defect density, metal interstitial defect density, etc. These defect densities are widely present in metal oxides and are considered It is an important factor in reducing the performance and reliability of thin film transistors, but it is difficult to completely eliminate them in the conventional device structure. Since these defect densities are eliminated, the thin film transistor structure disclosed in the present invention greatly enhances the performance and long-term reliability of the thin film transistor. For example, the current-to-voltage ratio of metal oxide thin film transistors is greatly increased, even higher than 1011; the threshold voltage drift caused by the common hysteresis effect is suppressed to within 0.15 V; a certain voltage is applied to the gate electrode. The drift of the threshold voltage is degraded to around 0 V. Secondly, the insulating layer covering the upper portion of the channel region can not only completely protect the channel region from the damage caused by electrode etching like the etch barrier layer, but also protect the thin film transistor from the external environment and enhance the film. The environmental stability of the transistor. For example, the problem of performance degradation such as threshold voltage drift caused by storing 10 small turns at 80 degrees Celsius and 80% relative humidity can be greatly improved by the structure of the thin film transistor of the present invention.
[0055] 总结来说， 本发明相较于传统薄膜晶体管结构拥有诸多优点， 包括： 更简单的 制造工艺， 更低的制备成本， 更高的工艺扩展性， 更优的器件性能， 可靠性和 环境稳定性。  [0055] In summary, the present invention has many advantages over conventional thin film transistor structures, including: simpler manufacturing processes, lower fabrication costs, higher process scalability, better device performance, reliability, and Environmental stability.
[0056] 参照图 4， 图 4为本发明中薄膜晶体管结构第二种实施例的剖视图。 本实施例中 薄膜晶体管采用顶栅结构。 同样地， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上 的有源层 2; 有源层 2之上设置有透氧栅极电极 311和设置在透氧栅极电极 311和 有源层 2之间的透氧栅极绝缘层 321 ; 有源层 2、 透氧栅极绝缘层 321和透氧栅极 电极 311的上方覆盖有绝缘层 6， 绝缘层 6上形成有深至有源层 2的通孔， 所述通 孔内淀积有导体， 从而由所述通孔中引出电极 4， 电极 4分别与有源层 2的部分区 域相电连接。  Referring to FIG. 4, FIG. 4 is a cross-sectional view showing a second embodiment of a thin film transistor structure of the present invention. In the embodiment, the thin film transistor has a top gate structure. Similarly, the thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; an oxygen permeable gate electrode 311 disposed over the active layer 2; and an oxygen permeable gate electrode 311 and an active layer disposed thereon An oxygen permeable gate insulating layer 321 between the two; an active layer 2, an oxygen permeable gate insulating layer 321 and an oxygen permeable gate electrode 311 are covered with an insulating layer 6 and a deep to active layer is formed on the insulating layer 6. A through hole is formed in the through hole, and a conductor is deposited in the through hole, thereby extracting the electrode 4 from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively.
[0057] 参照图 4， 透氧栅极电极 311的厚度小于所述含氧元素的物质在栅极电极 31中的 扩散长度， 所述含氧元素的物质在退火处理中能够透过透氧栅极电极 311， 因而 透氧栅极电极 311是透氧层； 透氧栅极电极 311包含以下材料中的一种或多种的 组合： 氧化锌、 氧化铟锡、 氧化铝锌、 氧化铟铝或氧化铟锌； 透氧栅极电极 311 的厚度为 10至 3000纳米。 优选地， 透氧栅极电极 311的厚度在 200纳米到 500纳米 之间。 Referring to FIG. 4, the thickness of the oxygen permeable gate electrode 311 is smaller than the diffusion length of the oxygen-containing element in the gate electrode 31, and the oxygen-containing substance is transparent to the oxygen permeable gate during the annealing treatment. The electrode 311, and thus the oxygen permeable gate electrode 311 is an oxygen permeable layer; the oxygen permeable gate electrode 311 comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or Indium zinc oxide; the oxygen permeable gate electrode 311 has a thickness of 10 to 3000 nm. Preferably, the oxygen permeable gate electrode 311 has a thickness of 200 nm to 500 nm. Between.
[0058] 参照图 4， 透氧栅极绝缘层 321的厚度小于所述含氧元素的物质在透氧栅极绝缘 层 321中的扩散长度； 所述含氧元素的物质在退火处理中能够透过透氧栅极绝缘 层 321， 因而透氧栅极绝缘层 321是透氧层； 透氧栅极绝缘层 321包含以下材料中 的一种或多种的组合： 氧化硅、 氮氧化硅， 其中所述氮氧化硅中氮化硅的比例 小于 20%; 透氧栅极绝缘层 321的厚度为 10至 3000纳米。 优选地， 透氧栅极绝缘 层 321的厚度在 200纳米到 500纳米之间。  Referring to FIG. 4, the thickness of the oxygen permeable gate insulating layer 321 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate insulating layer 321; the oxygen-containing substance is transparent in the annealing treatment. The oxygen permeable gate insulating layer 321 is such that the oxygen permeable gate insulating layer 321 is an oxygen permeable layer; the oxygen permeable gate insulating layer 321 comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein The proportion of silicon nitride in the silicon oxynitride is less than 20%; and the thickness of the oxygen permeable gate insulating layer 321 is 10 to 3000 nm. Preferably, the oxygen permeable gate insulating layer 321 has a thickness of between 200 nm and 500 nm.
[0059] 参照图 4， 本发明中， 退火处理中， 电极 4阻挡了所述含氧元素的物质， 有源层 2在电极 4覆盖下的区域的电阻率得以降低， 形成源区 21、 漏区 23。 降低了的源 区 21、 漏区 23的电阻率有利于降低源区 21、 漏区 23与电极 4之间的接触电阻， 从 而提高薄膜晶体管的幵态性能。 与电极 4的特性相反， 绝缘层 6、 透氧栅极电极 3 11和透氧栅极绝缘层 321是透氧层。 退火处理中， 所述含氧元素的物质能够透过 绝缘层 6、 透氧栅极电极 311和透氧栅极绝缘层 321进入有源层 2， 因而有源层 2在 非电极 4覆盖下的区域的电阻率得到保持甚至提高， 形成沟道区 22。 在沟道区 22 上方的绝缘层 6还能提高沟道区 22的电阻率、 降低沟道区 22的缺陷密度， 从而改 善薄膜晶体管的关态特性， 并且绝缘层 6还能保护沟道区 22免受外界环境的影响 ， 提高薄膜晶体管的稳定性和可靠性。  Referring to FIG. 4, in the annealing process, the electrode 4 blocks the substance containing the oxygen element, and the resistivity of the active layer 2 under the coverage of the electrode 4 is reduced to form the source region 21 and the drain. District 23. The reduced resistivity of the source region 21 and the drain region 23 is advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. In contrast to the characteristics of the electrode 4, the insulating layer 6, the oxygen permeable gate electrode 311 and the oxygen permeable gate insulating layer 321 are oxygen permeable layers. In the annealing treatment, the oxygen-containing substance can enter the active layer 2 through the insulating layer 6, the oxygen-permeable gate electrode 311, and the oxygen-permeable gate insulating layer 321, so that the active layer 2 is covered by the non-electrode 4 The resistivity of the region is maintained or even increased to form the channel region 22. The insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the insulating layer 6 can also protect the channel region 22 Protect the stability and reliability of thin film transistors from the external environment.
[0060] 参照图 5， 图 5为本发明中薄膜晶体管结构第三种实施例的剖视图。 本实施例中 薄膜晶体管采用背栅结构。 其中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上的 有源层 2; 有源层 2与衬底 1之间还设置有栅极叠层 3， 栅极叠层 3则包括栅极电极 31和设置在栅极电极 31和有源层 2之间的栅极绝缘层 32; 有源层 2的不同区域上 方分别覆盖有第二绝缘层 61和第一绝缘层 62， 第二绝缘层 61上形成有深至有源 层 2的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出电极 4， 电极 4分别 与有源层 2的部分区域相电连接。 第二绝缘层 61的投影面积与电极 4的投影面积 完全重叠， 第一绝缘层 62在电极 4的投影面积之外。  Referring to FIG. 5, FIG. 5 is a cross-sectional view showing a third embodiment of a thin film transistor structure of the present invention. In the embodiment, the thin film transistor has a back gate structure. The thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; a gate stack 3 disposed between the active layer 2 and the substrate 1, and a gate stack 3 including a gate The electrode 31 and the gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; the second insulating layer 61 and the first insulating layer 62 are respectively covered over different regions of the active layer 2, and the second insulating layer A through hole deep to the active layer 2 is formed on the 61, and a conductor is deposited in the through hole, so that the electrode 4 is taken out from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively. The projected area of the second insulating layer 61 completely overlaps the projected area of the electrode 4, and the first insulating layer 62 is outside the projected area of the electrode 4.
[0061] 参照图 5， 第二绝缘层 61的厚度大于所述含氧元素的物质在第二绝缘层 61中的 扩散长度， 其能阻挡所述含氧元素的物质， 因而第二绝缘层 61是不透氧层； 优 选地， 第二绝缘层 61的厚度为所述含氧元素的物质在第二绝缘层 61中扩散长度 的 2至 100倍之间。 第二绝缘层 61由以下材料制成： 氮化硅、 氮氧化硅、 氧化铝 、 氧化铪， 其中氮氧化硅中的氮化硅比例大于 20%。 第二绝缘层 61的厚度为 10至 3000纳米。 优选地， 第二绝缘层 61的厚度在 200纳米到 500纳米之间。 Referring to FIG. 5, the thickness of the second insulating layer 61 is greater than the diffusion length of the substance containing the oxygen element in the second insulating layer 61, which can block the substance containing the oxygen element, and thus the second insulating layer 61 Is an oxygen-impermeable layer; preferably, the thickness of the second insulating layer 61 is the diffusion length of the oxygen-containing substance in the second insulating layer 61 Between 2 and 100 times. The second insulating layer 61 is made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, wherein the proportion of silicon nitride in the silicon oxynitride is more than 20%. The second insulating layer 61 has a thickness of 10 to 3000 nm. Preferably, the thickness of the second insulating layer 61 is between 200 nm and 500 nm.
[0062] 参照图 5， 本发明中， 第一绝缘层 62的厚度小于所述含氧元素的物质在第一绝 缘层 62中的扩散长度， 所述含氧元素的物质在退火处理中能透过第一绝缘层 62 ， 因而第一绝缘层 62是透氧层。 第一绝缘层 62包括以下材料中的一种或多种的 组合： 氧化硅、 氮氧化硅， 其中， 所述氮氧化硅中氮化硅的比例小于 20%。 第一 绝缘层 62的厚度为 10至 3000纳米。 优选地， 第一绝缘层 62的厚度在 200纳米到 50 0纳米之间。 Referring to FIG. 5, in the present invention, the thickness of the first insulating layer 62 is smaller than the diffusion length of the oxygen-containing material in the first insulating layer 62, and the oxygen-containing substance is transparent in the annealing process. The first insulating layer 62 is passed, and thus the first insulating layer 62 is an oxygen permeable layer. The first insulating layer 62 includes a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The first insulating layer 62 has a thickness of 10 to 3000 nm. Preferably, the thickness of the first insulating layer 62 is between 200 nm and 50 nm.
[0063] 参照图 5， 在退火处理中， 电极 4和第二绝缘层 61共同阻挡所述含氧元素的物质 ， 有源层 2在电极 4和第二绝缘层 61覆盖下的区域的电阻率得以降低， 形成源区 2 1、 漏区 23。 降低了的源区 21、 漏区 23的电阻率有利于降低源区 21、 漏区 23与电 极 4之间的接触电阻， 从而提高薄膜晶体管的幵态性能。 与电极 4和第二绝缘层 6 1的特性相反， 在退火处理中， 所述含氧元素的物质能够透过第一绝缘层 62进入 有源层 2， 因而有源层 2在非电极 4和第二绝缘层 61覆盖下的区域的电阻率得到保 持甚至提高， 形成沟道区 22。 在沟道区 22上方的第一绝缘层 62还能提高沟道区 2 2的电阻率、 降低沟道区 22的缺陷密度， 从而改善薄膜晶体管的关态特性， 并且 第一绝缘层 62还能保护沟道区 22免受外界环境的影响， 提高薄膜晶体管的稳定 性和可靠性。  Referring to FIG. 5, in the annealing process, the electrode 4 and the second insulating layer 61 collectively block the resistivity of the oxygen-containing substance, the region of the active layer 2 covered by the electrode 4 and the second insulating layer 61. It is reduced to form the source region 2 1 and the drain region 23 . The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. Contrary to the characteristics of the electrode 4 and the second insulating layer 61, in the annealing process, the oxygen-containing substance can penetrate the first insulating layer 62 into the active layer 2, and thus the active layer 2 is on the non-electrode 4 and The resistivity of the region covered by the second insulating layer 61 is maintained or even increased to form the channel region 22. The first insulating layer 62 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 62 can also The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0064] 参照图 6， 图 6为本发明中的薄膜晶体管结构第四种实施例的剖视图。 本实施例 中薄膜晶体管采用背栅结构。 其中， 薄膜晶体管包括： 衬底 1 ; 设置在衬底 1上 的有源层 2; 有源层 2与衬底 1之间还设置有栅极叠层 3， 栅极叠层 3则包括栅极电 极 31和设置在栅极电极 31和有源层 2之间的栅极绝缘层 32; 有源层 2的不同区域 上方分别覆盖有第二绝缘层 61和第一绝缘层 62， 第二绝缘层 61上形成有深至有 源层 2的通孔， 所述通孔内淀积有导体， 从而由所述通孔中引出电极 4， 电极 4分 别与有源层 2的部分区域相电连接。 第二绝缘层 61的投影面积与电极 4的投影面 积完全重叠， 第一绝缘层 62在电极 4的投影面积之外。 在电极 4、 第二绝缘层 61 和第一绝缘层 62之上还覆盖有第三绝缘层 7。 第二绝缘层 61的投影面积、 电极 4 的投影面积和第三绝缘层 7的投影面积完全重叠， 第一绝缘层 62在电极 4的投影 面积之外。 6, FIG. 6 is a cross-sectional view showing a fourth embodiment of the thin film transistor structure of the present invention. The thin film transistor in this embodiment adopts a back gate structure. The thin film transistor includes: a substrate 1; an active layer 2 disposed on the substrate 1; a gate stack 3 disposed between the active layer 2 and the substrate 1, and a gate stack 3 including a gate The electrode 31 and the gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; the second insulating layer 61 and the first insulating layer 62 are respectively covered over different regions of the active layer 2, and the second insulating layer A through hole deep to the active layer 2 is formed on the 61, and a conductor is deposited in the through hole, so that the electrode 4 is taken out from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer 2, respectively. The projected area of the second insulating layer 61 completely overlaps the projected area of the electrode 4, and the first insulating layer 62 is outside the projected area of the electrode 4. A third insulating layer 7 is also covered over the electrode 4, the second insulating layer 61 and the first insulating layer 62. Projection area of the second insulating layer 61, the electrode 4 The projected area and the projected area of the third insulating layer 7 completely overlap, and the first insulating layer 62 is outside the projected area of the electrode 4.
[0065] 参照图 6， 在退火处理中， 第三绝缘层 7、 电极 4和第二绝缘层 61共同阻挡所述 含氧元素的物质， 有源层 2在第三绝缘层 7、 电极 4和第二绝缘层 61覆盖下的区域 的电阻率得以降低， 形成源区 21、 漏区 23。 降低了的源区 21、 漏区 23的电阻率 有利于降低源区 21、 漏区 23与电极 4之间的接触电阻， 从而提高薄膜晶体管的幵 态性能。 与电极 4的特性相反， 退火处理中， 所述含氧元素的物质能够透过第一 绝缘层 62进入有源层 2， 因而有源层 2在非第三绝缘层 7、 电极 4和第二绝缘层 61 覆盖下的区域的电阻率得到保持甚至提高， 形成沟道区 22。 在沟道区 22上方的 第一绝缘层 62还能提高沟道区 22的电阻率、 降低沟道区 22的缺陷密度， 从而改 善薄膜晶体管的关态特性， 并且第一绝缘层 62还能保护沟道区 22免受外界环境 的影响， 提高薄膜晶体管的稳定性和可靠性。  Referring to FIG. 6, in the annealing process, the third insulating layer 7, the electrode 4, and the second insulating layer 61 collectively block the substance containing the oxygen element, the active layer 2 is on the third insulating layer 7, the electrode 4, and The resistivity of the region covered by the second insulating layer 61 is lowered to form the source region 21 and the drain region 23. The reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor. Contrary to the characteristics of the electrode 4, in the annealing treatment, the oxygen-containing substance can enter the active layer 2 through the first insulating layer 62, and thus the active layer 2 is on the non-third insulating layer 7, the electrode 4, and the second The resistivity of the region covered by the insulating layer 61 is maintained or even increased to form the channel region 22. The first insulating layer 62 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 62 can also protect The channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
[0066] 参照图 7， 图 7为本发明中显示面板中第一种显示模块结构的示意图， 显示器面 板由多个显示模块组成。 显示模块中包括薄膜晶体管、 中间绝缘层 8、 像素电极 9、 光电材料 10和公共电极 11。 像素电极 9与所述薄膜晶体管的电极 4通过中间绝 缘层 8上的通孔相电连接。 光电材料 10包括但不限于： 液晶、 发光二极管、 有机 发光二极管、 量子点发光二极管。 在本实施例的显示面板中， 所述薄膜晶体管 为图 3所述薄膜晶体管。 所述薄膜晶体管还可以用于构成电路， 比如显示面板中 的驱动电路。  7, FIG. 7 is a schematic diagram showing the structure of a first display module in a display panel according to the present invention, wherein the display panel is composed of a plurality of display modules. The display module includes a thin film transistor, an intermediate insulating layer 8, a pixel electrode 9, a photovoltaic material 10, and a common electrode 11. The pixel electrode 9 and the electrode 4 of the thin film transistor are electrically connected through a via hole in the intermediate insulating layer 8. Photoelectric material 10 includes, but is not limited to, liquid crystals, light emitting diodes, organic light emitting diodes, and quantum dot light emitting diodes. In the display panel of this embodiment, the thin film transistor is the thin film transistor described in Fig. 3. The thin film transistor can also be used to form a circuit such as a driver circuit in a display panel.
[0067] 参照图 8， 图 8为本发明中显示面板中第二种显示模块结构的示意图， 显示器面 板由多个显示模块组成。 显示模块中包括薄膜晶体管、 中间绝缘层 8、 像素电极 9、 光电材料 10和公共电极 11。 像素电极 9与所述薄膜晶体管的电极 4通过中间绝 缘层 8上的通孔相电连接。 在本实施例的显示面板中， 所述薄膜晶体管为图 6所 述薄膜晶体管。 所述薄膜晶体管还可以用于构成电路， 比如显示面板中的驱动 电路。  Referring to FIG. 8, FIG. 8 is a schematic diagram showing the structure of a second display module in a display panel according to the present invention. The display panel is composed of a plurality of display modules. The display module includes a thin film transistor, an intermediate insulating layer 8, a pixel electrode 9, a photovoltaic material 10, and a common electrode 11. The pixel electrode 9 and the electrode 4 of the thin film transistor are electrically connected through a via hole in the intermediate insulating layer 8. In the display panel of this embodiment, the thin film transistor is the thin film transistor described in FIG. The thin film transistor can also be used to form a circuit, such as a driver circuit in a display panel.
[0068] 最后应当说明的是， 以上实施例仅为本发明的较佳实施例而已， 而非对本发明 保护范围的限制， 本领域的普通技术人员应当理解， 凡在本发明的精神和原则 之内所作的任何修改、 等同替换或改进等， 均应包含在本发明的保护范围之内 [0068] It should be noted that the above embodiments are merely preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Those skilled in the art should understand that the spirit and principles of the present invention Any modifications, equivalent substitutions or improvements made therein shall be included in the scope of protection of the present invention.
C8C0l/9T0ZN3/X3d Ζ99Ϊ.0/.Ϊ0Ζ OAV C8C0l/9T0ZN3/X3d Ζ99Ϊ.0/.Ϊ0Ζ OAV

Claims

权利要求书  Claim
一种薄膜晶体管， 包括： 衬底和设置在所述衬底上的由金属氧化物构 成的有源层； 所述有源层与栅极叠层相毗邻， 所述有源层部分区域上 覆盖有电极， 所述电极的厚度大于含氧元素的物质在所述电极中的扩 散长度， 所述电极与所述有源层之间还包括绝缘层， 所述绝缘层在非 所述电极覆盖下的部分为第一绝缘层， 所述第一绝缘层的厚度小于所 述含氧元素的物质在所述第一绝缘层中的扩散长度； 所述有源层在所 述电极覆盖下的区域分别形成源区和漏区， 非所述电极覆盖下的区域 形成沟道区； 所述源区、 所述漏区与所述沟道区相互连接， 且分别位 于所述沟道区的两端， 所述沟道区与所述栅极叠层相毗邻， 所述源区 、 所述漏区与所述沟道区之间的连接面自对准于所述电极在所述有源 层投影面积之内的边界的铅垂面； 所述源区、 所述漏区的电阻率小于 所述沟道区的电阻率。 A thin film transistor comprising: a substrate and an active layer made of a metal oxide disposed on the substrate; the active layer is adjacent to the gate stack, and the active layer is partially covered An electrode having a thickness greater than a diffusion length of a substance containing an oxygen element in the electrode, and an insulating layer between the electrode and the active layer, the insulating layer being covered by the electrode a portion of the first insulating layer having a thickness smaller than a diffusion length of the oxygen-containing material in the first insulating layer; Forming a source region and a drain region, wherein the region not covered by the electrode forms a channel region; the source region, the drain region and the channel region are connected to each other, and are respectively located at two ends of the channel region, The channel region is adjacent to the gate stack, and a connection surface between the source region, the drain region and the channel region is self-aligned with a projected area of the electrode in the active layer a vertical plane of a boundary within the boundary; the source region, the drain region The resistivity is less than the resistivity of the channel region.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述源区、 所述漏 区与所述沟道区之间的连接面和所述电极在所述有源层投影面积之内 的边界的铅垂面的间距小于所述有源层厚度的 100倍。 The thin film transistor according to claim 1, wherein a boundary between the source region, the drain region and the channel region, and a boundary of the electrode within a projected area of the active layer The pitch of the vertical plane is less than 100 times the thickness of the active layer.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述沟道区与所述 源区、 所述漏区的电阻率比值大于 1000倍。 The thin film transistor according to claim 1, wherein a ratio of resistivity of said channel region to said source region and said drain region is greater than 1000 times.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述有源层包括以 下材料中的一种或多种的组合： 氧化锌、 氮氧化锌、 氧化锡、 氧化铟 、 氧化镓、 氧化铜、 氧化铋、 氧化铟锌、 氧化锌锡、 氧化铝锡、 氧化 铟锡、 氧化铟镓锌、 氧化铟锡锌、 氧化铝铟锡锌、 硫化锌、 钛酸钡、 钛酸锶或铌酸锂。 The thin film transistor according to claim 1, wherein the active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide , yttria, indium zinc oxide, zinc tin oxide, aluminum oxide tin, indium tin oxide, indium gallium zinc oxide, indium tin zinc, aluminum indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate .
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述第一绝缘层包 括以下材料中的一种或多种的组合： 氧化硅、 氮氧化硅， 其中所述氮 氧化硅中氮化硅的比例小于 20%。 The thin film transistor according to claim 1, wherein the first insulating layer comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein silicon nitride in the silicon oxynitride The proportion is less than 20%.
根据权利要求 5所述的薄膜晶体管， 其特征在于， 所述第一绝缘层的 厚度为 10至 3000纳米。 根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述电极的厚度为 所述含氧元素的物质在所述电极中扩散长度的 2至 100倍之间。 The thin film transistor according to claim 5, wherein the first insulating layer has a thickness of 10 to 3000 nm. The thin film transistor according to claim 1, wherein the electrode has a thickness of between 2 and 100 times the diffusion length of the oxygen-containing substance in the electrode.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述电极包括以下 材料中的一种或多种的组合： 钛、 钼、 铝、 铜、 银、 金、 镍、 钨、 铬 、 铪、 铂、 铁， 钛钨合金、 钼铝合金、 钼铜合金或铜铝合金。 The thin film transistor according to claim 1, wherein the electrode comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, ruthenium, Platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy.
根据权利要求 8所述的薄膜晶体管， 其特征在于， 所述电极的厚度为 1 0至 3000纳米。 The thin film transistor according to claim 8, wherein the electrode has a thickness of from 10 to 3,000 nm.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述栅极叠层设置 在所述有源层与所述衬底之间。 The thin film transistor according to claim 1, wherein the gate stack is disposed between the active layer and the substrate.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述有源层设置在 所述栅极叠层和所述衬底之间。 The thin film transistor according to claim 1, wherein the active layer is provided between the gate stack and the substrate.
根据权利要求 11所述的薄膜晶体管， 其特征在于， 所述栅极叠层包括 栅极电极和栅极绝缘层， 所述栅极电极的厚度小于所述含氧元素的物 质在所述栅极电极中的扩散长度， 所述栅极绝缘层的厚度小于所述含 氧元素的物质在所述栅极绝缘层中的扩散长度。 The thin film transistor according to claim 11, wherein the gate stack includes a gate electrode and a gate insulating layer, and a thickness of the gate electrode is smaller than a substance of the oxygen-containing element at the gate a diffusion length in the electrode, the thickness of the gate insulating layer being smaller than a diffusion length of the oxygen-containing material in the gate insulating layer.
根据权利要求 12所述的薄膜晶体管， 其特征在于， 所述栅极电极包含 以下材料中的一种或多种的组合： 氧化锌、 氧化铟锡、 氧化铝锌、 氧 化铟铝或氧化铟锌； 所述栅极绝缘层包含以下材料中的一种或多种的 组合： 氧化硅、 氮氧化硅， 其中所述氮氧化硅中氮化硅的比例小于 20 。 The thin film transistor according to claim 12, wherein the gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or indium zinc oxide The gate insulating layer comprises a combination of one or more of the following materials: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20.
根据权利要求 13所述的薄膜晶体管， 其特征在于， 所述栅极电极的厚 度为 10至 3000纳米； 所述栅极绝缘层的厚度为 10至 3000纳米。 The thin film transistor according to claim 13, wherein the gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述含氧元素的物 质包括： 氧气、 臭氧、 一氧化二氮、 水、 双氧水、 二氧化碳和上述物 质的等离子体。 The thin film transistor according to claim 1, wherein the oxygen-containing substance comprises: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above substance.
根据权利要求 1所述的薄膜晶体管， 其特征在于， 所述源区、 所述漏 区的电阻率小于 10欧姆厘米， 所述沟道区的电阻率大于 10欧姆厘米。 一种显示器面板， 包括多组显示模块， 其特征在于， 所述显示模块包 含权利要求 1至 16任一项所述薄膜晶体管。 The thin film transistor according to claim 1, wherein the source region and the drain region have a resistivity of less than 10 ohm cm, and the channel region has a resistivity greater than 10 ohm cm. A display panel includes a plurality of sets of display modules, wherein the display module package A thin film transistor according to any one of claims 1 to 16.
一种薄膜晶体管的制造方法， 其特征在于， 包括： A method of manufacturing a thin film transistor, comprising:
准备一个衬底； Preparing a substrate;
在所述衬底之上设置有源层和与所述有源层相毗邻的栅极叠层， 所述 有源层由金属氧化物构成； An active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
在所述有源层的部分区域上覆盖有电极， 使所述电极的厚度大于含氧 元素的物质在所述电极中的扩散长度； a portion of the active layer is covered with an electrode such that the thickness of the electrode is greater than a diffusion length of the oxygen-containing material in the electrode;
在所述电极与所述有源层之间设置有绝缘层， 使所述绝缘层在非所述 电极覆盖下的部分为第一绝缘层， 所述第一绝缘层的厚度小于所述含 氧元素的物质在所述第一绝缘层中的扩散长度； An insulating layer is disposed between the electrode and the active layer, wherein a portion of the insulating layer that is not covered by the electrode is a first insulating layer, and a thickness of the first insulating layer is smaller than the oxygen content a diffusion length of the substance of the element in the first insulating layer;
进行退火处理， 使所述有源层在所述电极覆盖下的区域分别形成源区 和漏区， 非所述电极覆盖下的区域形成沟道区， 所述沟道区与所述栅 极叠层相毗邻， 所述源区、 所述漏区与所述沟道区相互连接、 且分别 位于所述沟道区的两端， 且使所述源区、 所述漏区与所述沟道区之间 由退火处理形成连接面， 该连接面自对准于所述电极在所述有源层投 影面积之内的边界的铅垂面， 所述源区和所述漏区的电阻率小于所述 沟道区的电阻率。 Performing an annealing process to form a source region and a drain region respectively in a region under the cover of the electrode, and a region not covered by the electrode to form a channel region, the channel region and the gate stack The layers are adjacent to each other, the source region, the drain region and the channel region are connected to each other, and are respectively located at two ends of the channel region, and the source region, the drain region and the channel are Forming a connection surface between the regions by annealing, the connection surface being self-aligned to a vertical plane of a boundary of the electrode within a projected area of the active layer, and the resistivity of the source region and the drain region is less than The resistivity of the channel region.
根据权利要求 18所述的薄膜晶体管制造方法， 其特征在于， 所述源区 、 所述漏区与所述沟道区之间由退火形成的所述连接面与所述电极在 所述有源层投影面积之内的边界的铅垂面的间距小于所述有源层厚度 的 100倍。 The thin film transistor manufacturing method according to claim 18, wherein said connection region formed by annealing between said source region, said drain region and said channel region, and said electrode are active at said electrode The pitch of the vertical plane of the boundary within the projected area of the layer is less than 100 times the thickness of the active layer.
根据权利要求 18所述的薄膜晶体管制造方法， 其特征在于， 所述退火 处理包括利用热、 光、 激光、 微波进行加热。 The method of manufacturing a thin film transistor according to claim 18, wherein the annealing treatment comprises heating with heat, light, laser, or microwave.
根据权利要求 18所述的薄膜晶体管制造方法， 其特征在于， 所述退火 处理是在氧化气氛下， 持续 10秒至 10小吋， 温度在 100°C和 600°C之间 根据权利要求 21所述的薄膜晶体管制造方法中， 其特征在于， 所述氧 化气氛包括： 氧气、 臭氧、 一氧化二氮、 水、 二氧化碳和上述物质的 等离子体。 The method of manufacturing a thin film transistor according to claim 18, wherein the annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is between 100 ° C and 600 ° C according to claim 21. In the method of manufacturing a thin film transistor, the oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and the like Plasma.
[权利要求 23] —种显示器面板， 包括多组显示模块， 其特征在于， 所述显示模块包 含权利要求 18至 22任一项所述方法制造的薄膜晶体管。  [Claim 23] A display panel comprising a plurality of sets of display modules, wherein the display module comprises a thin film transistor fabricated by the method of any one of claims 18 to 22.
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