CN104851809A - Thin-film transistor, producing method thereof, array substrate, and display device - Google Patents
Thin-film transistor, producing method thereof, array substrate, and display device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 118
- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 238000000151 deposition Methods 0.000 claims abstract description 47
- 230000008569 process Effects 0.000 claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 claims abstract description 34
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- 238000006243 chemical reaction Methods 0.000 claims abstract description 24
- 239000010410 layer Substances 0.000 claims description 94
- 238000002425 crystallisation Methods 0.000 claims description 45
- 230000008025 crystallization Effects 0.000 claims description 45
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- 229910052751 metal Inorganic materials 0.000 claims description 23
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- 238000005468 ion implantation Methods 0.000 claims description 21
- 239000012212 insulator Substances 0.000 claims description 19
- 238000000059 patterning Methods 0.000 claims description 18
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 18
- 239000011241 protective layer Substances 0.000 claims description 17
- 238000005224 laser annealing Methods 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 13
- 238000002161 passivation Methods 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 8
- 238000000576 coating method Methods 0.000 claims description 8
- 238000005234 chemical deposition Methods 0.000 claims description 2
- 125000000896 monocarboxylic acid group Chemical group 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052799 carbon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 230000008859 change Effects 0.000 abstract description 4
- 230000031700 light absorption Effects 0.000 abstract 1
- 239000002243 precursor Substances 0.000 abstract 1
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- 238000002513 implantation Methods 0.000 description 15
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- 210000002381 plasma Anatomy 0.000 description 13
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- 229910052796 boron Inorganic materials 0.000 description 10
- 239000000463 material Substances 0.000 description 10
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- 238000005516 engineering process Methods 0.000 description 7
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- 239000012159 carrier gas Substances 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
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- 239000011574 phosphorus Substances 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
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- 229910001182 Mo alloy Inorganic materials 0.000 description 2
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- 229910018540 Si C Inorganic materials 0.000 description 2
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- 229910052786 argon Inorganic materials 0.000 description 2
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- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Provided is a method for producing a thin-film transistor. The method comprises: a step of depositing a crystallized precursor, wherein a chemical vapor deposition (CVD) process is used and a carbon-containing gas and a silicon-containing gas are used as a reaction source in the CVD process; a crystallizing step; a step of forming an active layer; a step of forming a gate insulated layer and a gate electrode; and a step of forming a source electrode and a drain electrode. The method for producing the thin-film transistor may increase the forbidden bandwidth of the active layer so as to further reduce the leakage current of the low temperature poly-silicon thin-film transistor, the visible light absorption coefficient of the low temperature poly silicon, and the photoinduced leakage current generated by a backlight. In addition, the method for producing the thin-film transistor is suitable for a conventional poly-silicon thin-film transistor production line, prevents an increase in the number of photomask times and a change in production equipment, and is easy and convenient to operate. The invention also provides a thin-film transistor, an array substrate, and a display device.
Description
Technical field
The present invention relates to field of semiconductor devices, particularly relate to a kind of thin-film transistor and preparation method thereof and array base palte and display unit.
Background technology
Thin Film Transistor-LCD (TFT-LCD) is most important one in flat display field, because it has many merits, as thin in volume, lightweight, picture quality is excellent, low in energy consumption, life-span length, digitlization etc., and be the Display Technique uniquely can crossing over all sizes, its application widely, almost cover the primary electron product of current information-intensive society, as TV, monitor, portable computer, mobile phone, PDA, GPS, car-mounted display, instrument and meter, public display and medical display etc.
In a liquid crystal display, thin-film transistor is generally used as switch element and controls pixel, or being used as driving element drives pixel.Thin-film transistor can be divided into amorphous silicon (a-Si) and polysilicon (Poly-Si) two kinds usually according to silicon thin film character, compared with amorphous silicon film transistor, carrier mobility height 2-3 order of magnitude of polycrystalline SiTFT, this makes polycrystalline SiTFT in high resolution flat, have great advantage.But, off-state current (i.e. leakage current) nearly 1 order of magnitude higher than amorphous silicon film transistor of polycrystalline SiTFT.Off-state current is excessive, then can affect the switching characteristic of thin-film transistor, thus display is uneven, turn white, the display class defect such as to harass to cause TFT-LCD to occur.
At present, most Display panel manufacturer mostly controls the off-state current of polycrystalline SiTFT by changing TFT structure, as TFT is made double-grid structure, or the raceway groove of TFT is made S shape etc., increased the length-width ratio of TFT by the length increasing TFT raceway groove, thus reduce its off-state current.But these methods bring negative effect to be that TFT area obviously increases, display aperture ratio declines.In high-resolution display, along with the raising of resolution, the area of each pixel becomes more and more less, and in limited elemental area, the shortcoming reducing the method for the off-state current of polycrystalline SiTFT by increasing TFT channel length also becomes more and more obviously and is difficult to maintain.How to solve this contradiction, avoid the reduction of display aperture ratio at the off-state current controlling polycrystalline SiTFT simultaneously, be the direction of industry pursuit and the emphasis of research always.
Summary of the invention
Based on this, the invention provides a kind of thin-film transistor and preparation method thereof and array base palte and display unit, the reduction of display aperture ratio can be avoided at the off-state current reducing polycrystalline SiTFT simultaneously, and the method is applicable to existing polycrystalline SiTFT production line, without the need to increasing photomask number of times or change production equipment, method of operation is simple and convenient.
A manufacture method for thin-film transistor, comprising:
The deposition step of crystallization predecessor, described deposition step adopts chemical vapor deposition method, and in described chemical vapor deposition method with carbonaceous gas and silicon-containing gas for reaction source;
Crystallization steps;
Be formed with the step of active layer;
Form the step of gate insulator and grid;
Form the step of source electrode and drain electrode.
Wherein in an embodiment, in described chemical vapor deposition method, the gas flow ratio of described carbonaceous gas and described silicon-containing gas is 1/10 ~ 1.
Wherein in an embodiment, described silicon-containing gas is SiH
4, SiH
2cl
2or SiH
3at least one in Cl, described carbonaceous gas is CH
4, C
2h
6, CH
3oH, C
2h
5oH or CH
3at least one in COOH.
Wherein in an embodiment, described chemical deposition process is plasma enhanced chemical vapor deposition, and wherein, the temperature adopted is 250 ~ 400 DEG C, and the pressure adopted is 100 ~ 400Pa, and the radio-frequency power adopted is 10 ~ 80mW/cm
2.
Wherein in an embodiment, specifically comprise:
Deposition of gate metal level on substrate, by patterning processes, forms grid;
Deposition of gate insulating barrier on described grid;
On described gate insulator, using plasma strengthens chemical vapor deposition method deposition crystallization predecessor, and in described plasma enhanced chemical vapor deposition technique with carbonaceous gas and silicon-containing gas for reaction source;
Quasi-molecule laser annealing technique is carried out to described crystallization predecessor, forms crystallization layer;
Patterning processes is carried out to described crystallization layer, is formed with active layer;
Ion implantation is carried out to described active layer, realizes channel doping;
Depositing trench insulating barrier on described active layer, by patterning processes, forms channel protective layer;
Take channel protective layer as mask, ion implantation is carried out to described active layer, form source region and drain region;
Intermediate protective layer in described active layer deposition, and via hole is formed on described intermediate protective layer;
Depositing metal layers on described intermediate insulating layer, by patterning processes, forms source electrode and drain electrode.
Wherein in an embodiment, specifically comprise:
Substrate forms resilient coating;
On described resilient coating, using plasma strengthens chemical vapor deposition method deposition crystallization predecessor, and in described plasma enhanced chemical vapor deposition technique with carbonaceous gas and silicon-containing gas for reaction source;
Quasi-molecule laser annealing technique is carried out to described crystallization predecessor, forms crystallization layer;
Patterning processes is carried out to described crystallization layer, is formed with active layer;
Ion implantation is carried out to described active layer, realizes channel doping;
Deposition of gate insulating barrier on described active layer;
Deposition of gate metal level on described gate insulator, by patterning processes, forms grid;
Take grid as mask, ion implantation is carried out to described active layer, form source region and drain region;
Deposit passivation layer on described grid, forms via hole at described gate insulator and described passivation layer;
Make source electrode and drain electrode.
Wherein in an embodiment, the thickness of described crystallization predecessor is 40nm ~ 60nm.
A kind of thin-film transistor, described thin-film transistor adopts above-mentioned arbitrary described manufacture method manufacture to obtain.
A kind of array base palte, comprises substrate, and is arranged at above-mentioned thin-film transistor, grid line, data wire and the pixel electrode on described substrate.
A kind of display unit, comprises above-mentioned array base palte.
The manufacture method of above-mentioned thin-film transistor by the deposition process of crystallization predecessor simultaneously with carbonaceous gas and silicon-containing gas for reaction source, the active layer of doping carbon element is obtained after laser crystallization, compared with undoped low temperature polycrystalline silicon, carbon doping can make to form the stronger Si-C key of bond energy in low temperature polycrystalline silicon, improve the energy gap of active layer, and then effectively reduce the leakage current of low-temperature polysilicon film transistor.And, also can reduce the visible absorption coefficient of low temperature polycrystalline silicon, reduce the induced leakage current that backlight produces.In addition, the manufacture method of above-mentioned thin-film transistor, is applicable to existing polycrystalline SiTFT production line, and without the need to increasing photomask number of times or change production equipment, method of operation is simple and convenient.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of one embodiment of the invention;
Fig. 2 is the schematic flow sheet of the manufacture method of another embodiment of the present invention;
Fig. 3 A-3G is respectively the structural representation of each step of the thin-film transistor shown in Fig. 2 in manufacturing process.
Embodiment
For feature of the present invention, technological means and the specific purposes reached, function can be understood further, below in conjunction with embodiment, the present invention is described in further detail.
The invention provides a kind of manufacture method of thin-film transistor, comprising:
The deposition step of crystallization predecessor, described deposition step adopts chemical vapor deposition method, and in described chemical vapor deposition method with carbonaceous gas and silicon-containing gas for reaction source;
Crystallization steps;
Be formed with the step of active layer;
Form the step of gate insulator and grid;
Form the step of source electrode and drain electrode.
The position relationship of grid and source drain pressed by thin-film transistor, can be divided into bottom grating structure and top gate structure.The present embodiment can be used for the thin-film transistor making bottom grating structure, and it specifically comprises the steps:
S110: deposition of gate metal level on substrate, by patterning processes, forms grid.
On clean transparency carrier, as glass, polyimides (PI) and PETG (PET) etc., adopt the method deposition of gate metal levels such as sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapour deposition (CVD) (LPCVD), Films Prepared by APCVD (APCVD), electron cyclotron resonance microwave plasmas chemical vapour deposition (CVD) (ECR-CVD), then, mask plate (mask) is utilized to carry out exposing, develop and etching, gate metal layer is graphical, form grid.
Such as, the material of gate metal layer is the metal or alloy such as molybdenum, aluminium, chromium, copper, alumel and molybdenum and tungsten alloy, and for example, uses the combination of above-mentioned different materials.In the present embodiment, the thickness of gate metal layer is 100-800nm, and certainly, the thickness of gate metal layer also can need to select suitable thickness according to concrete technology.
S120: deposition of gate insulating barrier on grid.
Such as, adopt chemical gaseous phase depositing process, the substrate defining grid forms gate insulator.And for example, depositing temperature general control is below 500 DEG C.And for example, the thickness of gate insulator can be 30 ~ 300nm, also can need to select suitable thickness according to concrete technology.And for example, gate insulator adopts silica, the silicon nitride of individual layer, or the lamination of the two.
S130: using plasma strengthens chemical vapor deposition method deposition crystallization predecessor on gate insulator, and in plasma enhanced chemical vapor deposition technique with carbonaceous gas and silicon-containing gas for reaction source.
The know-why of plasma enhanced chemical vapor deposition (PECVD) utilizes low temperature plasma to make energy source, sample is placed on the electrode of PECVD device, heater is utilized to make sample be warmed up to predetermined temperature, then appropriate reacting gas is passed into reaction chamber, two battery lead plates apply high-frequency ac voltage, gas is ionized under high-frequency electric field, then through series of chemical, forms solid film at sample surfaces.
Usually, when utilizing PECVD deposition techniques thin-film material, mainly contain following three basic processes: (1) electronics in the plasma of glow discharge through external electric field accelerate after, with reacting gas generation primary reaction, reacting gas is decomposed, forms the mixture of ion and active group; (2) cation is subject to the acceleration of sheath accelerating field and top electrode collides, also less sheath electric field can be there is near bottom electrode, so substrate is also by Ions Bombardment to a certain extent, to film growth surface and tube wall diffusion transport, there is the secondary reaction between each reactant in various active group simultaneously; (3) the various primary reaction and the secondary reactants that arrive substrate surface are adsorbed and are mutually reacted with surface, thus form film, releasing again with gas molecule in space thing simultaneously.
In the present embodiment, with carbonaceous gas and silicon-containing gas for reaction source, take hydrogen as carrier gas, the gas flow ratio controlling carbonaceous gas and silicon-containing gas is 1/10 ~ 1, namely 10% to 100%, the pressure controlling reaction chamber is 100 ~ 400Pa, and temperature is 250 ~ 400 DEG C, and radio-frequency power is 10 ~ 80mW/cm
2shi Jinhang plasma reinforced chemical vapour deposition.Wherein, silicon-containing gas can be SiH
4, SiH
2cl
2or SiH
3cl, carbonaceous gas can be CH
4, C
2h
6, CH
3oH, C
2h
5oH or CH
3cOOH.Such as, the volume ratio of reaction source and carrier gas is 1 ~ 10:1 ~ 1000; Such as, 1 ~ 10:1 ~ 100; And for example, with carbonaceous gas and silicon-containing gas for reaction source, take argon gas as carrier gas.
In the present embodiment, the thickness of crystallization predecessor is 40nm ~ 60nm.Certainly, also can need according to concrete technique to select suitable thickness.Such as, the thickness of crystallization predecessor is 42nm ~ 55nm, and and for example, the thickness of crystallization predecessor is 45nm, 48nm, 50nm, 51nm, 52nm or 54nm.
S140: carry out laser annealing technique to crystallization predecessor, forms crystallization layer.
Such as, laser annealing can adopt the excimer lasers such as chlorination xenon (XeCl), KrF (KrF), argon fluoride (ArF), and such as wavelength is 308nm, carries out quasi-molecule laser annealing.Laser beam is linear light sorurce after optical system.
Such as, the pulse recurrence rate (pulse repetition ratio) of quasi-molecule laser annealing is 300Hz ~ 800Hz, and and for example, the pulse recurrence rate of quasi-molecule laser annealing is 400Hz ~ 600Hz; And for example, sweep span (scan pitch) is 15 μm ~ 30 μm; And for example, laser energy density is 250 ~ 600mJ/cm
2, and for example, laser energy density is 350 ~ 500mJ/cm
2; And for example, sweep speed is preferably 0.5mm/s ~ 50mm/s, and and for example, sweep speed is 0.5mm/s ~ 50mm/s 1mm/s ~ 30mm/s, and and for example, sweep speed is 2mm/s ~ 10mm/s.
Preferably, before carrying out laser annealing technique, need to carry out dehydrogenation to this crystallization predecessor, make hydrogen content be down to less than 2%, prevent the generation of the quick-fried phenomenon of hydrogen.Such as, heat treatment is adopted to be got rid of from this crystallization predecessor by hydrogen.
S150: patterning processes is carried out to crystallization layer, is formed with active layer;
Such as, particularly, it comprises the following steps:
S151: utilize photoetching process to form mask, adopts dry etching method to form figure, forms the active layer comprising source region, drain region, channel region.
S152: ion implantation is carried out to active layer, realizes channel doping.
In the present embodiment, the object of doping is the threshold voltage in order to regulate thin-film transistor.Such as, when needing the threshold voltage of thin-film transistor to move to positive direction, boron element doping is carried out to active layer; When needing the threshold voltage of thin-film transistor to move to negative direction, P elements doping or arsenic element doping are carried out to active layer; And if do not need adjusting threshold voltage according to technique, then do not need that ion implantation is carried out to active layer and realize channel doping.
Ion implantation mode comprises the ion implantation mode with mass-synchrometer, the ion cloud formula injection mode without mass-synchrometer, Plasma inpouring mode or solid-state diffusion formula injection mode.Such as, the ion implantation mode with mass-synchrometer is adopted in the present embodiment.
According to the needs of thin-film transistor threshold voltage, injected media is the gas containing boron element or phosphorus element-containing.Such as, when needing to inject containing boron element, as with B
2h
6with H
2mist be injected media, and for example, B
2h
6with H
2ratio be 1% ~ 30%, Implantation Energy scope is 2 ~ 50KeV, and preferred energy range is 4 ~ 10KeV, and implantation dosage scope is 0 ~ 5 × 10
13atoms/cm
3, preferably, implantation dosage scope is 0 ~ 9 × 10
12atoms/cm
3.And for example, phosphorus element-containing is adopted, as with PH
3with H
2mist as injected media, such as, PH
3with H
2ratio be 1% ~ 30%; Implantation Energy scope is 5 ~ 50KeV, and preferred energy range is 7 ~ 20KeV; Implantation dosage scope is 0 ~ 5 × 10
13atoms/cm
3, preferably, implantation dosage scope is 0 ~ 9 × 10
12atoms/cm
3.
S160: depositing trench insulating barrier on active layer, by patterning processes, forms channel protective layer.
Such as, chemical gaseous phase depositing process is adopted, depositing trench insulating barrier on active layer.And for example, depositing temperature general control is below 500 DEG C.And for example, the thickness of raceway groove insulating barrier can be 20 ~ 300nm, also can need to select suitable thickness according to concrete technology.And for example, raceway groove insulating barrier adopts silica, the silicon nitride of individual layer, or the lamination of the two.
Such as, raceway groove insulating barrier applies photoresist, is exposed by mask plate.And for example, use positive photoresist, exposure light source exposes photoresist from orientation substrate through substrate, and have the local exposure light source of grid to be blocked, photoresist is not below exposed, and forms pattern after development.
Do template with the photoresist retained, channel protective layer is etched.The protective layer covered not having photoresist etches away.Then by releasing process, photoresist is removed.
S170: take channel protective layer as mask, carry out ion implantation to active layer, forms source region and drain region.
Ion implantation mode comprises the ion implantation mode with mass-synchrometer, the ion cloud formula injection mode without mass-synchrometer, Plasma inpouring mode or solid-state diffusion formula injection mode.Such as, the ion implantation mode with mass-synchrometer is adopted in the present embodiment.
According to design needs, injected media is the gas containing boron element and/or phosphorus element-containing, to form P type or N-type TFT.Such as, adopt containing boron element, as with B
2h
6/ H
2mist be injected media, such as, B
2h
6with H
2ratio be 1% ~ 30%; Implantation Energy scope is 5 ~ 50KeV, and preferred energy range is 7 ~ 25KeV; Implantation dosage scope is 1 × 10
13~ 1 × 10
17atoms/cm
3, preferably, implantation dosage scope is 5 × 10
14~ 5 × 10
15atoms/cm
3; And for example, phosphorus element-containing is adopted, as with PH
3/ H
2mist as injected media.
S180: deposit intermediate insulating layer in channel protective layer, and via hole is carried out to intermediate insulating layer.
Such as, adopt chemical gaseous phase depositing process, channel protective layer deposits intermediate insulating layer.And for example, depositing temperature general control is below 500 DEG C.And for example, the thickness of intermediate insulating layer can be 100 ~ 1000nm, also can need to select suitable thickness according to concrete technology.And for example, intermediate insulating layer adopts silica, the silicon nitride of individual layer, or the lamination of the two.
Such as, adopt the method for dry etching, form mask with photoetching process, intermediate insulating layer forms via hole to expose source region and drain region.Wherein, in dry etch process, the gas containing fluorine element or chloride element can be adopted, as SF
6, CF
4, CHF
3, CCl
2f
2deng gas or These gases and O
2mist as etch media, adopt reactive ion etching method, plasma etching method or inductively coupled plasma etching method to etch.
S190: depositing metal layers on intermediate protective layer, by patterning processes, forms source electrode and drain electrode.
Such as, S190 specifically comprises the steps:
S191: at intermediate protective layer deposition source and drain metallic film;
S192: the method adopting wet etching or dry etching, forms mask with photoetching process, carries out composition to source and drain metallic film, forms source electrode and drain electrode.
So far, completed the preparation of thin-film transistor that array base palte comprises grid, source electrode and drain electrode, and grid line, data wire and the pixel electrode on array base palte can obtain according to common process.According to the topology requirement of array base palte, finally form display floater by common process, form display unit further.
Another embodiment of the present invention also provides one for the manufacture method of the thin-film transistor of top gate structure, and its concrete steps are as follows:
S210: form resilient coating on substrate.
Refer to Fig. 3 A, clean substrate 100 forms resilient coating 200, and substrate 100 can be glass substrate or flexible base, board.The resilient coating 200 formed can improve the degree of adhesion between crystallization predecessor to be formed and substrate.Meanwhile, can also prevent the metal ion in substrate from diffusing to active layer, reduce impurity defect, and the generation of leakage current can be reduced.
Particularly, plasma chemical vapor deposition (PECVD) is utilized to deposit the certain thickness resilient coating of one deck on the glass substrate.Deposition materials can be the silica (SiO of individual layer
x) rete or silicon nitride (SiN
x) rete, or be silica (SiO
x) and silicon nitride (SiN
x) lamination.
Wherein, SiN is formed
xthe reacting gas of rete can be SiH
4, NH
3, N
2mist, or be SiH
2cl
2, NH
3, N
2mist; Form SiO
xthe reacting gas of rete can be SiH
4, N2O mist, or be SiH
4, silester (TEOS) mist.
S220: using plasma strengthens chemical vapor deposition method deposition crystallization predecessor on the buffer layer, and in plasma enhanced chemical vapor deposition technique with carbonaceous gas and silicon-containing gas for reaction source.
In the present embodiment, with carbonaceous gas and silicon-containing gas for reaction source, take hydrogen as carrier gas, the gas flow ratio controlling carbonaceous gas and silicon-containing gas is 1/10 ~ 1, the pressure controlling reaction chamber is 100 ~ 400Pa, and temperature is 250 ~ 400 DEG C, and radio-frequency power is 10 ~ 80mW/cm
2shi Jinhang plasma reinforced chemical vapour deposition.Wherein, silicon-containing gas can be SiH
4, SiH
2cl
2or SiH
3cl, carbonaceous gas can be CH
4, C
2h
6, CH
3oH, C
2h
5oH or CH
3cOOH.Such as, the volume ratio of reaction source and carrier gas is 1 ~ 10:1 ~ 1000; Such as, 1 ~ 10:1 ~ 100; And for example, with carbonaceous gas and silicon-containing gas for reaction source, take argon gas as carrier gas.
In the present embodiment, the thickness of crystallization predecessor is 40nm ~ 60nm.Certainly, also can need according to concrete technique to select suitable thickness.Such as, the thickness of crystallization predecessor is 42nm ~ 55nm, and and for example, the thickness of crystallization predecessor is 45nm, 48nm, 50nm, 51nm, 52nm or 54nm.
S230: carry out laser annealing technique to crystallization predecessor, forms crystallization layer.
Such as, laser annealing can adopt the excimer lasers such as chlorination xenon (XeCl), KrF (KrF), argon fluoride (ArF), and such as wavelength is 308nm, carries out quasi-molecule laser annealing.Laser beam is linear light sorurce after optical system.
Such as, the pulse recurrence rate (pulse repetition ratio) of quasi-molecule laser annealing is 300Hz ~ 800Hz, and and for example, the pulse recurrence rate of quasi-molecule laser annealing is 400Hz ~ 600Hz; And for example, sweep span (scan pitch) is 15 μm ~ 30 μm; And for example, laser energy density is 250 ~ 600mJ/cm
2, and for example, laser energy density is 350 ~ 500mJ/cm
2; And for example, sweep speed is preferably 0.5mm/s ~ 50mm/s, and and for example, sweep speed is 0.5mm/s ~ 50mm/s 1mm/s ~ 30mm/s, and and for example, sweep speed is 2mm/s ~ 10mm/s.
Preferably, before carrying out laser annealing technique, need to carry out dehydrogenation to this crystallization predecessor, make hydrogen content be down to less than 2%, prevent the generation of the quick-fried phenomenon of hydrogen.Such as, thermal anneal process is adopted to be got rid of from this crystallization predecessor by hydrogen.
S240: patterning processes is carried out to crystallization layer, is formed with active layer.
Such as, particularly, it comprises the following steps:
S241: utilize photoetching process to form mask, adopts dry etching method to form figure, forms the active layer 300 comprising source region, drain region and channel region, its complete after cross section refer to Fig. 3 B.
S242: ion implantation is carried out to active layer, realizes channel doping.
The object of adulterating to raceway groove is the threshold voltage in order to adjusting means.Such as, when needing the threshold voltage of thin-film transistor to move to positive direction, boron element doping is carried out to active layer; When needing the threshold voltage of thin-film transistor to move to negative direction, P elements doping or arsenic element doping are carried out to active layer; And if do not need adjusting threshold voltage according to technique, then do not need that ion implantation is carried out to active layer and realize channel doping.
S250: deposition of gate insulating barrier 400 on active layer 300, its complete after cross section refer to Fig. 3 C.
Such as, adopt chemical gaseous phase depositing process, the substrate defining active layer forms gate insulator.And for example, depositing temperature general control is below 500 DEG C.And for example, the thickness of gate insulator can be 80 ~ 200nm, also can need to select suitable thickness according to concrete technology.And for example, gate insulator adopts silica, the silicon nitride of individual layer, or the lamination of the two.
S260: deposition of gate metal level on gate insulator 400, by patterning processes, formed grid 500, its complete after cross section refer to Fig. 3 D.
Such as, adopt the method deposition of gate metal levels such as sputtering, thermal evaporation or plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapour deposition (CVD) (LPCVD), Films Prepared by APCVD (APCVD), electron cyclotron resonance microwave plasmas chemical vapour deposition (CVD) (ECR-CVD), then, mask plate (mask) is utilized to carry out exposing, develop and etching, gate metal layer is graphical, form grid.
Such as, the material of gate metal layer is the metal or alloy such as molybdenum, aluminium, chromium, copper, alumel and molybdenum and tungsten alloy, and for example, uses the combination of above-mentioned different materials.In the present embodiment, the thickness of gate metal layer is 100-800nm, and certainly, the thickness of gate metal layer also can need to select suitable thickness according to concrete technology.
S270: using grid 500 as mask, carries out ion implantation to active layer 300, forms source region 310 and drain region 320, its complete after cross section refer to Fig. 3 E.
Such as, the ion implantation mode with mass-synchrometer is adopted in the present embodiment.And for example, according to design needs, injected media is the gas containing boron element and/or phosphorus element-containing, to form P type or N-type TFT.Such as, adopt containing boron element, as with B
2h
6/ H
2mist be injected media, such as, B
2h
6with H
2ratio be 1% ~ 30%; Implantation Energy scope is 5 ~ 50KeV, and preferred energy range is 20 ~ 30KeV; Implantation dosage scope is 1 × 10
13~ 1 × 10
17atoms/cm
3, preferably, implantation dosage scope is 5 × 10
14~ 5 × 10
15atoms/cm
3; And for example, phosphorus element-containing is adopted, as with PH
3/ H
2mist as injected media.As with PH
3/ H
2mist be injected media, such as, PH
3with H
2ratio be 1% ~ 30%; Implantation Energy scope is 20 ~ 110KeV, and preferred energy range is 50 ~ 70KeV; Implantation dosage scope is 1 × 10
13~ 1 × 10
17atoms/cm
3, preferably, implantation dosage scope is 5 × 10
14~ 5 × 10
15atoms/cm
3.
S280: deposit passivation layer 600 on grid 500, and form via hole 610 at gate insulator 400 and passivation layer 600, its complete after cross section refer to Fig. 3 F.
Particularly, can be the passivation layer of 200nm ~ 800nm by chemical vapor deposition method deposit thickness, such as, passivation layer is oxide, nitride or oxynitrides, and and for example, passivation layer is single layer structure or sandwich construction, and for example, the gas forming passivation layer is SiH
4, NH
3, N
2or SiH
4, N
2o.
Such as, adopt the method for dry etching, form mask with photoetching process, passivation layer and gate insulator form via hole to expose source region and drain region.Wherein, in dry etch process, the gas containing fluorine element or chloride element can be adopted, as SF
6, CF
4, CHF
3, CCl
2f
2deng gas or These gases and O
2mist as etch media, adopt reactive ion etching method, plasma etching method or inductively coupled plasma etching method to etch.
S290: make source electrode 710 and drain electrode 720, its complete after cross section refer to Fig. 3 G.
Particularly, above passivation layer, adopt sputtering mode, thermal evaporation methods or plasma enhanced chemical vapor deposition mode, low-pressure chemical vapor deposition mode, sub-atmospheric CVD mode or electron cyclotron resonance chemical vapour deposition (CVD) mode to form metal level.Above metal level, adopt photoetching process to form photolithographic mask with photoresist, and adopt wet etching or dry etching to form the figure comprising source electrode and drain electrode.Refer to Fig. 3 G, source electrode 710 runs through via hole 610 and is electrically connected with source region 310, and drain electrode 720 runs through via hole 610 and is electrically connected with drain region 320.
So far, namely completed by the method the preparation of thin-film transistor that array base palte comprises grid, source electrode and drain electrode, and grid line, data wire and the pixel electrode on array base palte can obtain according to common process.According to the topology requirement of array base palte, finally form display floater by common process, form display unit further.
And for example, a kind of thin-film transistor, it adopts manufacture method described in above-mentioned any embodiment to prepare.
And for example, a kind of array base palte, it comprises substrate, and is arranged at thin-film transistor, grid line, data wire and the pixel electrode on described substrate, and wherein, described thin-film transistor adopts manufacture method described in above-mentioned any embodiment to prepare.
There is provided a display unit in the present embodiment, this display unit comprises the array base palte in above-mentioned any embodiment.Such as, this display unit is product or the parts with Presentation Function; Such as, this display unit is liquid crystal panel, Electronic Paper, oled panel, mobile phone, panel computer, television set, display, notebook computer, DPF or navigator.
The manufacture method of above-mentioned thin-film transistor by the deposition process of crystallization predecessor simultaneously with carbonaceous gas and silicon-containing gas for reaction source, the active layer of doping carbon element is obtained after Excimer-Laser Crystallization, compared with undoped low temperature polycrystalline silicon, carbon doping can make to form the stronger Si-C key of bond energy in low temperature polycrystalline silicon, improves the energy gap of active layer.
And leakage current mainly comprises in low temperature polycrystalline silicon: reverse saturation current, the band-to-band-tunneling electric current that band-to-band-tunneling electric current and defect are assisted.
For reverse saturation current, according to reverse saturation current formula:
Wherein: j is reverse saturation current, A and κ is coefficient, T is temperature, E
gfor material energy gap, L
nand L
pbe respectively diffusion length, the τ as few son of electron hole
nand τ
pbe respectively electronics and hole minority carrier life time, N as few period of the day from 11 p.m. to 1 a.m
aand N
dbe respectively the doping content in P district and N district, q is electric charge, V is reversed bias voltage.
It can thus be appreciated that reaction saturation current j is with material energy gap E
grising and exponentially reduce.
For the band-to-band-tunneling electric current that band-to-band-tunneling electric current and defect are assisted, according to Kane band-to-band-tunneling probability formula:
Wherein: G
bTBTfor band-to-band-tunneling probability, m
*for electron effective mass, E be transverse electric field intensity,
for reduced Planck constant.
It can thus be appreciated that, band-to-band-tunneling G
bTBTprobability is with material energy gap E
gincrease and reduce, therefore, the auxiliary band-to-band-tunneling electric current of band-to-band-tunneling electric current and defect also can with material energy gap E
gincrease and reduce.
Therefore, carbon doping improves to make the energy gap of active layer, thus effectively can reduce the leakage current of this low-temperature polysilicon film transistor.And, increase active layer energy gap, also can reduce its visible absorption coefficient, reduce the induced leakage current that backlight produces.
In addition, the manufacture method of above-mentioned thin-film transistor, is applicable to existing polycrystalline SiTFT production line, and without the need to increasing photomask number of times or change production equipment, method of operation is simple and convenient.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a manufacture method for thin-film transistor, is characterized in that, comprising:
The deposition step of crystallization predecessor, described deposition step adopts chemical vapor deposition method, and in described chemical vapor deposition method with carbonaceous gas and silicon-containing gas for reaction source;
Crystallization steps;
Be formed with the step of active layer;
Form the step of gate insulator and grid;
Form the step of source electrode and drain electrode.
2. manufacture method according to claim 1, is characterized in that, in described chemical vapor deposition method, the gas flow ratio of described carbonaceous gas and described silicon-containing gas is 1/10 ~ 1.
3. manufacture method according to claim 2, is characterized in that, described silicon-containing gas is SiH
4, SiH
2cl
2or SiH
3at least one in Cl, described carbonaceous gas is CH
4, C
2h
6, CH
3oH, C
2h
5oH or CH
3at least one in COOH.
4. manufacture method according to claim 2, is characterized in that, described chemical deposition process is plasma enhanced chemical vapor deposition, wherein, the temperature adopted is 250 ~ 400 DEG C, and the pressure adopted is 100 ~ 400Pa, and the radio-frequency power adopted is 10 ~ 80mW/cm
2.
5. manufacture method according to claim 1, is characterized in that, specifically comprises:
Deposition of gate metal level on substrate, by patterning processes, forms grid;
Deposition of gate insulating barrier on described grid;
On described gate insulator, using plasma strengthens chemical vapor deposition method deposition crystallization predecessor, and in described plasma enhanced chemical vapor deposition technique with carbonaceous gas and silicon-containing gas for reaction source;
Laser annealing technique is carried out to described crystallization predecessor, forms crystallization layer;
Patterning processes is carried out to described crystallization layer, is formed with active layer;
There is layer to carry out ion implantation to described, realize channel doping;
Depositing trench insulating barrier on described active layer, by patterning processes, forms channel protective layer;
Take channel protective layer as mask, ion implantation is carried out to described active layer, form source region and drain region;
Intermediate protective layer in described active layer deposition, and via hole is formed on described intermediate protective layer;
Depositing metal layers on described intermediate protective layer, by patterning processes, forms source electrode and drain electrode.
6. manufacture method according to claim 1, is characterized in that, specifically comprises:
Substrate forms resilient coating;
On described resilient coating, using plasma strengthens chemical vapor deposition method deposition crystallization predecessor, and in described plasma enhanced chemical vapor deposition technique with carbonaceous gas and silicon-containing gas for reaction source;
Quasi-molecule laser annealing technique is carried out to described crystallization predecessor, forms crystallization layer;
Patterning processes is carried out to described crystallization layer, is formed with active layer;
There is layer to carry out ion implantation to described, realize channel doping;
Deposition of gate insulating barrier on described active layer;
Deposition of gate metal level on described gate insulator, by patterning processes, forms grid;
Take grid as mask, ion implantation is carried out to described active layer, form source region and drain region;
Deposit passivation layer on described grid, and form via hole at described gate insulator and described passivation layer;
Make source electrode and drain electrode.
7. manufacture method according to claim 1, is characterized in that, the thickness of described crystallization predecessor is 40nm ~ 60nm.
8. a thin-film transistor, is characterized in that, the manufacture method manufacture as described in described thin-film transistor employing is as arbitrary in claim 1 to 7 obtains.
9. an array base palte, is characterized in that, comprises substrate, and is arranged at thin-film transistor as claimed in claim 8, grid line, data wire and the pixel electrode on described substrate.
10. a display unit, is characterized in that, comprises array base palte as claimed in claim 9.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017071662A1 (en) * | 2015-10-29 | 2017-05-04 | 陆磊 | Thin film transistor, manufacturing method therefore, and display panel |
| CN107039284A (en) * | 2017-04-17 | 2017-08-11 | 武汉华星光电技术有限公司 | A kind of method for making low-temperature polysilicon film transistor |
| CN111192908A (en) * | 2020-01-09 | 2020-05-22 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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| US4849797A (en) * | 1987-01-23 | 1989-07-18 | Hosiden Electronics Co., Ltd. | Thin film transistor |
| US5581092A (en) * | 1993-09-07 | 1996-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Gate insulated semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4849797A (en) * | 1987-01-23 | 1989-07-18 | Hosiden Electronics Co., Ltd. | Thin film transistor |
| US5581092A (en) * | 1993-09-07 | 1996-12-03 | Semiconductor Energy Laboratory Co., Ltd. | Gate insulated semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2017071662A1 (en) * | 2015-10-29 | 2017-05-04 | 陆磊 | Thin film transistor, manufacturing method therefore, and display panel |
| WO2017071661A1 (en) * | 2015-10-29 | 2017-05-04 | 陆磊 | Thin film transistor, manufacturing method therefor, and display panel |
| CN107039284A (en) * | 2017-04-17 | 2017-08-11 | 武汉华星光电技术有限公司 | A kind of method for making low-temperature polysilicon film transistor |
| CN111192908A (en) * | 2020-01-09 | 2020-05-22 | 武汉华星光电半导体显示技术有限公司 | Display panel and preparation method thereof |
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Application publication date: 20150819 |