CN104966663B - Low-temperature polycrystalline silicon thin film, preparation method thereof and thin film transistor - Google Patents

Low-temperature polycrystalline silicon thin film, preparation method thereof and thin film transistor Download PDF

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CN104966663B
CN104966663B CN201510268994.XA CN201510268994A CN104966663B CN 104966663 B CN104966663 B CN 104966663B CN 201510268994 A CN201510268994 A CN 201510268994A CN 104966663 B CN104966663 B CN 104966663B
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graphene
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polycrystalline silicon
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陈卓
陈建荣
任思雨
苏君海
李建华
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Truly Huizhou Smart Display Ltd
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Abstract

A preparation method of a low-temperature polycrystalline silicon film comprises the following steps: forming a buffer layer on a substrate; carrying out a composition process on the buffer layer, and forming a groove on the buffer layer corresponding to the non-channel region; forming a graphene layer in the groove; depositing an amorphous silicon layer on the buffer layer; and carrying out laser annealing treatment on the amorphous silicon layer to enable the amorphous silicon layer to form a polycrystalline silicon layer. According to the low-temperature polycrystalline silicon film, the graphene layer is arranged in the region corresponding to the non-channel region, and the thermal conductivity of graphene is utilized to form a temperature gradient in the silicon film, so that the polycrystalline silicon of the prepared low-temperature polycrystalline silicon film is large in crystal grain size and uniform in distribution.

Description

Low-temperature polycrystalline silicon thin film, preparation method thereof and thin film transistor
Technical Field
The invention relates to the technical field, in particular to a low-temperature polycrystalline silicon thin film, a preparation method of a thin film transistor and the thin film transistor.
Background
Polycrystalline silicon (p-Si) thin films, which have high carrier mobility much greater than that of amorphous silicon (a-Si) and comparable to that of monocrystalline silicon, are often applied to the active layer of Thin Film Transistors (TFTs) instead of amorphous silicon, and thus have very important applications in integrated peripheral-driven active liquid crystal displays (AMLCDs) and active organic light emitting diodes (AMOLEDs). The substrate of the polysilicon thin film of the flat panel display is glass that is difficult to withstand high temperature processes, and under this condition, Low Temperature Polysilicon (LTPS) technology is a necessary choice in the industry.
As for the current technology, there are the following main technologies: rapid annealing solid phase crystallization (RTA), excimer laser annealing crystallization (ELA), Metal Induced Lateral Crystallization (MILC), hot filament catalyzed chemical vapor deposition (Cat-CVD), and the like. Among them, ELA and MILC are currently most widely used in the industry.
ELA belongs to a liquid phase recrystallization method, and the polycrystalline silicon prepared by the method has large crystal grains and few inter-grain defects, so that the TFT device has excellent performance, such as high field effect mobility, low subthreshold swing value and low threshold voltage. The method for preparing the low-temperature polysilicon by the ELA comprises the steps of growing a buffer layer on glass, then growing amorphous silicon, scanning the amorphous silicon by utilizing excimer laser, and recrystallizing the amorphous silicon by high-temperature melting to form the polysilicon. In the ELA process, amorphous silicon is subjected to a high temperature to become a critical fully molten (polycrystalline) state, and then recrystallized to form polycrystalline silicon. The recrystallization proceeds to a high energy direction at a low energy and to a high temperature at a low temperature. In the prior art, an amorphous silicon layer is directly formed on a buffer layer, and in the process of excimer laser annealing, the heating conditions of all regions of the amorphous silicon layer tend to be consistent, and the starting point of recrystallization and the growth direction of crystal grains are messy, so that the grain size of low-temperature polycrystalline silicon after recrystallization is small, the grain boundaries among the crystal grains are large, the electron mobility of polycrystalline silicon is influenced, and the reaction speed of panel display is further influenced.
Disclosure of Invention
In view of the above, it is necessary to provide a low temperature polysilicon thin film, a method for preparing the same, and a thin film transistor, in which the polysilicon grains of the low temperature polysilicon thin film prepared by the preparation method are large and uniformly distributed.
A preparation method of a low-temperature polycrystalline silicon film comprises the following steps:
forming a buffer layer on a substrate;
carrying out a composition process on the buffer layer, and forming a groove on the buffer layer corresponding to the non-channel region;
forming a graphene layer in the groove;
depositing an amorphous silicon layer on the buffer layer;
and carrying out laser annealing treatment on the amorphous silicon layer to enable the amorphous silicon layer to form a polycrystalline silicon layer.
In one embodiment, the step of forming a graphene layer within the recess includes: and depositing graphene on the buffer layer, and etching the graphene to retain the graphene corresponding to the non-channel region to form a graphene layer.
In one embodiment, the graphene layer is deposited using a plasma enhanced chemical vapor deposition process.
In one embodiment, the buffer layer includes a silicon nitride layer and a silicon oxide layer sequentially stacked on the substrate.
In one embodiment, the depth of the recess is less than the thickness of the silicon oxide layer.
In one embodiment, before the step of performing laser annealing on the amorphous silicon layer, a high temperature dehydrogenation treatment is performed on the amorphous silicon layer.
In one embodiment, the laser annealing step uses an XeCl laser.
In one embodiment, the thickness of the amorphous silicon layer is 40-60 nm.
A low-temperature polycrystalline silicon thin film, which is prepared by the preparation method of any one of the preceding claims.
A thin film transistor comprises the low-temperature polycrystalline silicon thin film.
According to the low-temperature polycrystalline silicon film, the graphene layer is arranged in the region corresponding to the non-channel region, and the thermal conductivity of graphene is utilized to form a temperature gradient in the silicon film, so that the polycrystalline silicon of the prepared low-temperature polycrystalline silicon film is large in crystal grain size and uniform in distribution.
Drawings
FIG. 1 is a schematic flow chart of a method for preparing a low temperature polysilicon thin film according to an embodiment of the present invention;
fig. 2A-2E are schematic structural diagrams of steps of the low temperature polysilicon thin film shown in fig. 1 during the preparation process, respectively.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.
A preparation method of a low-temperature polycrystalline silicon film comprises the following steps: forming a buffer layer on a substrate; carrying out a composition process on the buffer layer, and forming a groove on the buffer layer corresponding to the non-channel region; forming a graphene layer in the groove; depositing an amorphous silicon layer on the buffer layer; and carrying out laser annealing treatment on the amorphous silicon layer to enable the amorphous silicon layer to form a polycrystalline silicon layer.
Fig. 1 is a flow chart of a method for preparing a low temperature polysilicon thin film according to an embodiment of the present invention.
S110: a buffer layer is formed on a substrate.
Referring to fig. 2A, a buffer layer 200 is formed on a clean substrate 100, and the substrate 100 may be a glass substrate or a flexible substrate. The formed buffer layer 200 can improve the adhesion degree between the amorphous silicon to be formed and the substrate, is beneficial to reducing the heat conduction effect, slows down the cooling rate of the silicon heated by laser, and is beneficial to crystallization of polycrystalline silicon. Meanwhile, metal ions in the substrate can be prevented from diffusing to the active layer, impurity defects are reduced, and generation of leakage current can be reduced.
Specifically, a buffer layer with a certain thickness is deposited on the glass substrate by using a Plasma Enhanced Chemical Vapor Deposition (PECVD), for example, the certain thickness is 50-100 nm. The deposition material may be a single layer of silicon oxide (SiO)x) Film or silicon nitride (SiN)x) Film layer, or silicon oxide (SiO)x) And silicon nitride (SiN)x) The laminate of (1). In the present embodiment, referring to fig. 2A, the buffer layer 200 includes a silicon nitride layer 210 and a silicon oxide layer 220 sequentially stacked on the substrate 100, for example, the silicon nitride layer 210 is disposed between the substrate 100 and the silicon oxide layer 220, which is beneficial for the subsequent hydrogenation process and obtains good electrical performance. Specifically, the silicon nitrideAnd the thickness of the silicon oxide lamination layer is 50 to 100 nm. For another example, the thickness ratio of the silicon nitride layer 210 to the silicon oxide layer 220 is 1 to 1.5: 0.8 to 1.6; for example, the thickness ratio of the silicon nitride layer 210 to the silicon oxide layer 220 is 1: 1. for example, the thickness of the silicon oxide layer is 20 to 60 nm.
Wherein SiN is formedxThe reaction gas of the film layer is SiH4、NH3、N2Or a mixed gas of SiH2Cl2、NH3、N2The mixed gas of (3); formation of SiOxThe reaction gas of the film layer is SiH4、N2Mixed gas of O, or SiH4And ethyl silicate (TEOS).
And S120, carrying out a composition process on the buffer layer, and forming a groove on the buffer layer corresponding to the non-channel region.
Referring to fig. 2B, a patterning process is performed to partially etch the buffer layer 200 corresponding to the non-channel region, so as to form a patterned groove 221 on the buffer layer 200, specifically, a region corresponding to the groove is an active layer non-channel region in the thin film transistor to be formed. For example, the buffer layer of the non-channel region is subjected to dry etching, and the buffer layer of the region corresponding to the non-channel region is removed, so that a patterned groove structure is formed on the buffer layer. And presetting the pattern of the groove structure. For another example, the etching gas used in the dry etching includes Ar and O2、CO、CO2、H2、SF6、CxFyOr CxFyHzOne or more of them. For another example, the etching gas used in the dry etching includes Ar and O2、CO、CO2、H2、SF6、CF4Or CHF3One or more of them.
For another example, the depth of the recess is less than the thickness of the silicon oxide layer. For another example, the depth of the groove is 1-10 nm, and for another example, the depth of the groove is 2-8 nm. In another example, the depth of the groove is 4-5 nm. For another example, the cross section of the groove is a trapezoid structure, and the width of the opening end of the groove is larger than that of the bottom of the groove. For another example, the cross-section of the groove is a rectangular structure.
S130, forming a graphene layer in the groove.
Referring to fig. 2C, graphene is filled in the groove 221 to form a graphene layer 230. For example, graphene is deposited on the buffer layer, and the graphene is etched to retain the graphene corresponding to the non-channel region, so as to form a graphene layer. In another example, the graphene layer is deposited using a plasma enhanced chemical vapor deposition process. In another example, the graphene layer is formed by a lift-off process. For another example, a chemical vapor deposition method is used to continuously grow multilayer graphene on the metal substrate, and then the metal substrate is used as a sacrificial layer to be corroded away, so that the multilayer graphene is attached to the groove. As another example, the graphene layer is p-type doped graphene.
For example, the graphene layer is 3-15 layers of graphene. In another example, the graphene is 5-10 layers of graphene. As another example, the thickness of the graphene layer is the same as the depth of the groove, that is, the graphene is flush with the top end of the groove; if the thickness of the graphene layer is 60% -90% of the depth of the groove, efficient filling of graphene is facilitated, and production efficiency is improved. Of course, the thickness of the graphene layer can be adjusted according to actual conditions.
And S140, depositing an amorphous silicon layer on the buffer layer.
Referring to fig. 2D, an amorphous silicon layer 300 is deposited on the buffer layer 200. For example, an amorphous silicon layer is deposited on the insulating layer using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. As another example, the deposition temperature is typically controlled below 500 ℃.
In this embodiment, the thickness of the amorphous silicon layer is 40nm to 60 nm. Of course, the thickness can be selected as appropriate for the particular process requirements. For example, the thickness of the amorphous silicon layer is 42nm to 55nm, and for example, the thickness of the amorphous silicon layer is 45nm, 48nm, 50nm, 51nm, 52nm or 54 nm.
S150, carrying out laser annealing treatment on the amorphous silicon layer to enable the amorphous silicon layer to form a polycrystalline silicon layer.
Referring to fig. 2E, the amorphous silicon layer 300 is subjected to a laser annealing process to form a polysilicon layer 400 on the amorphous silicon layer 300.
For example, excimer lasers such as xenon chloride (XeCl), krypton fluoride (KrF), and argon fluoride (ArF) can be used for laser annealing. In this example, an XeCl laser with a wavelength of 308nm was used for excimer laser annealing. The laser beam is a linear light source after passing through the optical system.
For example, the pulse repetition rate (pulse repetition rate) of excimer laser annealing is 300Hz to 800Hz, and for example, the pulse repetition rate of excimer laser annealing is 400Hz to 600 Hz; for another example, the scan pitch (scanpitch) is 15 μm to 30 μm; for another example, the laser energy density is 250-600 mJ/cm2For another example, the laser energy density is 350-500 mJ/cm2(ii) a The scan rate is preferably from 0.5mm/s to 50mm/s, from 1mm/s to 30mm/s, and from 2mm/s to 10mm/s, for example.
Preferably, before the laser annealing process is performed, the amorphous silicon layer needs to be subjected to dehydrogenation treatment, so that the hydrogen content is reduced to below 2%, and the hydrogen explosion phenomenon is prevented. For example, a thermal annealing process is used to remove hydrogen from the crystallization precursor.
Irradiating the solid amorphous silicon film by laser, wherein the silicon absorbs light energy and converts the light energy into heat energy, and the heat energy is converted from a solid state to a completely molten state; when the silicon thin film is cooled and crystallized after light irradiation, because the graphene layer has better heat conduction performance, the non-channel region of the silicon thin film is in a non-complete melting state, and the channel region of the silicon thin film is in a complete melting state; under the action of temperature gradient force, the solid-liquid surface of the silicon film crystallization is continuously pushed to the channel region from the non-channel regions on the two sides, thereby realizing super transverse crystallization of silicon crystal grains and obtaining a polycrystalline silicon layer with large grain size and uniform distribution.
According to the low-temperature polycrystalline silicon film, the graphene layer is arranged in the region corresponding to the non-channel region, and the thermal conductivity of graphene is utilized to form a temperature gradient in the silicon film, so that the polycrystalline silicon of the prepared low-temperature polycrystalline silicon film is large in crystal grain size and uniform in distribution.
The invention also provides a low-temperature polycrystalline silicon film prepared by the preparation method, and the low-temperature polycrystalline silicon film can be used for manufacturing a thin film transistor, a solar cell material or other semiconductor devices.
Another embodiment of the present invention further provides a method for manufacturing a thin film transistor, which includes the steps of:
and S210, forming a buffer layer on the substrate.
For example, a buffer layer is deposited on a glass substrate to a certain thickness by Plasma Enhanced Chemical Vapor Deposition (PECVD). The deposition material may be a single layer of silicon oxide (SiO)x) Film or silicon nitride (SiN)x) Film layer, or silicon oxide (SiO)x) And silicon nitride (SiN)x) The laminate of (1). In this embodiment, the buffer layer includes a silicon nitride layer and a silicon oxide layer sequentially stacked on the substrate, which is advantageous for the subsequent hydrogenation process and good electrical properties. Specifically, the thickness of the silicon nitride is 50-100 nm, and the thickness of the silicon oxide is 150-300 nm. Wherein SiN is formedxThe reaction gas of the film layer is SiH4、NH3、N2Or a mixed gas of SiH2Cl2、NH3、N2The mixed gas of (3); formation of SiOxThe reaction gas of the film layer is SiH4、N2Mixed gas of O, or SiH4And ethyl silicate (TEOS).
S220, carrying out a composition process on the buffer layer, and forming a groove on the buffer layer corresponding to the non-channel region.
For example, by a patterning process, the buffer layer corresponding to the non-channel region is partially etched, so that a patterned groove is formed on the buffer layer, and specifically, the region corresponding to the groove is the non-channel region of the active layer in the thin film transistor to be formed. For example, the buffer layer of the non-channel region is subjected to dry etching, and the buffer layer of the region corresponding to the non-channel region is removed, so that a patterned groove structure is formed on the buffer layer. For another example, the etching gas used in the dry etching includes Ar and O2、CO、CO2、H2、SF6、CxFyOr CxFyHzOne or more of them. As another example, the dry etching employs etchingThe gas comprises Ar, O2、CO、CO2、H2、SF6、CF4Or CHF3One or more of them.
For another example, the depth of the recess is less than the thickness of the silicon oxide layer. For another example, the depth of the groove is 1-10 nm, and for another example, the depth of the groove is 2-8 nm. In another example, the depth of the groove is 4-5 nm. For another example, the cross section of the groove is a trapezoid structure, and the width of the opening end of the groove is larger than that of the bottom of the groove. For another example, the cross-section of the groove is a rectangular structure.
And S230, forming a graphene layer in the groove.
For example, graphene is deposited on the buffer, and the graphene is etched to retain graphene corresponding to a non-channel region, so as to form a graphene layer. In another example, the graphene layer is deposited using a plasma enhanced chemical vapor deposition process. In another example, the graphene layer is formed by a lift-off process. For another example, a chemical vapor deposition method is used to continuously grow multilayer graphene on the metal substrate, and then the metal substrate is used as a sacrificial layer to be corroded away, so that the multilayer graphene is attached to the groove. As another example, the graphene layer is p-type doped graphene.
For example, the graphene layer is 3-15 layers of graphene. In another example, the graphene is 5-10 layers of graphene. As another example, the thickness of the graphene layer is the same as the depth of the groove, i.e., the graphene is flush with the top of the groove. Of course, the thickness of the graphene layer can be adjusted according to actual conditions.
S240, depositing an amorphous silicon layer on the buffer layer, and performing laser annealing treatment on the amorphous silicon layer to enable the amorphous silicon layer to form a polycrystalline silicon layer.
For example, an amorphous silicon layer is deposited on the insulating layer using a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. As another example, the deposition temperature is typically controlled below 500 ℃.
In this embodiment, the thickness of the amorphous silicon layer is 40nm to 60 nm. Of course, the thickness can be selected as appropriate for the particular process requirements. For example, the thickness of the amorphous silicon layer is 42nm to 55nm, and for example, the thickness of the amorphous silicon layer is 45nm, 48nm, 50nm, 51nm, 52nm or 54 nm.
For example, excimer lasers such as xenon chloride (XeCl), krypton fluoride (KrF), and argon fluoride (ArF) can be used for laser annealing. In this example, an XeCl laser with a wavelength of 308nm was used for excimer laser annealing. The laser beam is a linear light source after passing through the optical system.
For example, the pulse repetition rate (pulse repetition rate) of excimer laser annealing is 300Hz to 800Hz, and for example, the pulse repetition rate of excimer laser annealing is 400Hz to 600 Hz; for another example, the scan pitch (scan pitch) is 15 μm to 30 μm; for another example, the laser energy density is 250-600 mJ/cm2For another example, the laser energy density is 350-500 mJ/cm2(ii) a The scan rate is preferably from 0.5mm/s to 50mm/s, from 1mm/s to 30mm/s, and from 2mm/s to 10mm/s, for example.
Preferably, before the laser annealing process is performed, the amorphous silicon layer needs to be subjected to dehydrogenation treatment, so that the hydrogen content is reduced to below 2%, and the hydrogen explosion phenomenon is prevented. For example, a thermal annealing process is used to remove hydrogen from the crystallization precursor.
And S250, carrying out a composition process on the polycrystalline silicon layer to form an active layer.
For example, it specifically comprises the following steps:
and S251, forming a mask by utilizing a photoetching process, forming a pattern by adopting a dry etching method, and forming an active layer comprising a source region, a drain region and a channel region, wherein the active layer of the region corresponding to the graphene layer is the active layer of the source region or the drain region to be formed.
And S252, performing ion implantation on the active layer to realize channel doping.
The purpose of doping the channel is to adjust the threshold voltage of the device. For example, when the threshold voltage of the thin film transistor is required to be shifted in the positive direction, boron element doping is performed on the active layer; when the threshold voltage of the thin film transistor needs to move towards the negative direction, phosphorus element doping or arsenic element doping is carried out on the active layer; and if the threshold voltage does not need to be adjusted according to the process, the active layer does not need to be subjected to ion implantation to realize channel doping.
And S260, depositing a gate insulation layer on the active layer.
For example, a gate insulating layer is formed on the substrate on which the active layer is formed using a chemical vapor deposition method. As another example, the deposition temperature is typically controlled below 500 ℃. For another example, the thickness of the gate insulating layer may be 80 to 200nm, and an appropriate thickness may be selected according to specific process requirements. As another example, the gate insulating layer may be a single layer of silicon oxide, silicon nitride, or a stack of the two.
S270, depositing a grid metal layer on the grid insulating layer, and forming a grid through a composition process.
For example, a gate metal layer is deposited by sputtering, thermal evaporation, or Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), Atmospheric Pressure Chemical Vapor Deposition (APCVD), electron cyclotron resonance microwave plasma chemical vapor deposition (ECR-CVD), or the like, and then, the gate metal layer is patterned by exposure, development, and etching using a mask (mask) to form a gate electrode.
For example, the material of the gate metal layer is a metal or an alloy such as molybdenum, aluminum, chromium, copper, aluminum-nickel alloy, molybdenum-tungsten alloy, and the like, and for example, a combination of the above materials is used. In the embodiment, the thickness of the gate metal layer is 100 to 800nm, and of course, the thickness of the gate metal layer may also be selected according to the specific process requirements.
And S280, performing ion implantation on the non-channel region of the active layer by using the grid electrode as a mask to form a source region and a drain region.
For example, in the present embodiment, an ion implantation system having a mass analyzer is used. As another example, the implant medium may be a boron-containing gas and/or a phosphorous-containing gas to form a P-type or N-type tft, depending on design requirements. For example, boron-containing elements, e.g. with B2H6/H2The mixed gas being an injection medium, e.g. B2H6And H2The proportion of (A) is 1% -30%; the implantation energy range is 5-50 KeV, and the preferable energy range is 20-30 KeV; the implantation dose range is 1 × 1013～1×1017atoms/cm3Preferably, the implantation dose range is 5 × 1014～5×1015atoms/cm3(ii) a As another example, phosphorus-containing elements, e.g. at pH3/H2The mixed gas of (2) is used as an injection medium. E.g. at pH3/H2The mixed gas being an injection medium, e.g. PH3And H2The proportion of (A) is 1% -30%; the implantation energy range is 20-110 KeV, and the preferable energy range is 50-70 KeV; the implantation dose range is 1 × 1013～1×1017atoms/cm3Preferably, the implantation dose range is 5 × 1014～5×1015atoms/cm3。
And S290, depositing a passivation layer on the grid electrode, forming a through hole on the grid electrode insulating layer and the passivation layer, and manufacturing a source electrode and a drain electrode.
Specifically, the passivation layer with a thickness of 200nm to 800nm may be deposited by a chemical vapor deposition process, for example, the passivation layer is an oxide, a nitride or an oxynitride, for example, the passivation layer has a single-layer structure or a multi-layer structure, and for example, the gas forming the passivation layer is SiH4，NH3，N2Or SiH4，N2O。
For example, a mask is formed by a photolithography process using a dry etching method, and a via hole is formed on the passivation layer and the gate insulating layer to expose the source region and the drain region. Wherein, in the dry etching process, gas containing fluorine or chlorine, such as SF6、CF4、CHF3、CCl2F2Equal gas or the aforementioned gas and O2The mixed gas is used as an etching medium, and a reactive ion etching method, a plasma etching method or an inductive coupling plasma etching method is adopted for etching.
Specifically, a metal layer is formed above the passivation layer by a sputtering method, a thermal evaporation method or a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method or an electron cyclotron resonance chemical vapor deposition method. And forming a photoresist mask by using photoresist through a photoetching process and forming a pattern comprising a source electrode and a drain electrode through wet etching or dry etching on the upper part of the metal layer.
Because the solid-liquid surface of the polycrystalline silicon grains is pushed from the low-temperature area to the high-temperature area in the cooling and recrystallization stage of the silicon film, the polycrystalline silicon grains are larger in grain size and more orderly in distribution in the beginning stage in the limited crystallization time of the laser annealing process; therefore, in the manufacturing process of the thin film transistor, the graphene layers are arranged on the buffer layers of the source region and the drain region corresponding to the active layer, and the temperature gradient is formed in the silicon thin film by utilizing the heat conductivity of the graphene, so that the polycrystalline silicon crystal grains of the active layer channel region close to the source region and the drain region are larger and are distributed more orderly, the carrier mobility of the active layer channel region is improved, the leakage current of the active layer channel region is reduced, and the quality of the thin film transistor is improved. In addition, graphene is a semiconductor without an energy gap and has high carrier mobility, so that graphene can be used as a part of an active layer to improve the carrier mobility of the whole thin film transistor.
The invention also provides a thin film transistor comprising the thin film transistor prepared by the method.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (8)

1. The preparation method of the low-temperature polycrystalline silicon film is characterized by comprising the following steps of:
forming a buffer layer on a substrate;
performing dry etching on the buffer layer of the non-channel region, and removing the buffer layer in the region corresponding to the non-channel region to form a patterned groove on the buffer layer, wherein the region corresponding to the groove is the non-channel region of the active layer in the thin film transistor to be formed;
depositing graphene on the buffer layer, and etching the graphene to retain the graphene corresponding to the non-channel region to form a graphene layer;
depositing an amorphous silicon layer on the buffer layer;
and carrying out laser annealing treatment on the amorphous silicon layer to enable the amorphous silicon layer to form a polycrystalline silicon layer.
2. The method of claim 1, wherein the graphene layer is deposited using a plasma enhanced chemical vapor deposition process.
3. The production method according to claim 1, wherein the buffer layer comprises a silicon nitride layer and a silicon oxide layer which are sequentially stacked on the substrate.
4. The method of claim 3, wherein the depth of the recess is less than the thickness of the silicon oxide layer.
5. The method of claim 1, wherein the laser annealing step uses a XeCl laser.
6. The method according to claim 1, wherein the amorphous silicon layer has a thickness of 40 to 60 nm.
7. A low-temperature polycrystalline silicon thin film, which is prepared by the preparation method of any one of claims 1 to 6.
8. A thin film transistor comprising the low temperature polysilicon thin film according to claim 7.
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