CN105513950A - Preparation method of low-temperature polycrystalline silicon thin film and thin film transistor - Google Patents
Preparation method of low-temperature polycrystalline silicon thin film and thin film transistor Download PDFInfo
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- CN105513950A CN105513950A CN201610032218.4A CN201610032218A CN105513950A CN 105513950 A CN105513950 A CN 105513950A CN 201610032218 A CN201610032218 A CN 201610032218A CN 105513950 A CN105513950 A CN 105513950A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 48
- 238000002360 preparation method Methods 0.000 title claims abstract description 39
- 239000010409 thin film Substances 0.000 title claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 91
- 239000010408 film Substances 0.000 claims abstract description 59
- 238000000151 deposition Methods 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000005224 laser annealing Methods 0.000 claims abstract description 23
- 239000010410 layer Substances 0.000 claims description 140
- 239000006117 anti-reflective coating Substances 0.000 claims description 94
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 82
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 74
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 72
- 238000000034 method Methods 0.000 claims description 50
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 46
- 229920005591 polysilicon Polymers 0.000 claims description 43
- 239000001272 nitrous oxide Substances 0.000 claims description 41
- 230000008569 process Effects 0.000 claims description 38
- 229910021529 ammonia Inorganic materials 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 33
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 33
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 32
- 229910000077 silane Inorganic materials 0.000 claims description 32
- WMIYKQLTONQJES-UHFFFAOYSA-N hexafluoroethane Chemical compound FC(F)(F)C(F)(F)F WMIYKQLTONQJES-UHFFFAOYSA-N 0.000 claims description 28
- 239000000377 silicon dioxide Substances 0.000 claims description 27
- 239000012212 insulator Substances 0.000 claims description 24
- 229910052757 nitrogen Inorganic materials 0.000 claims description 23
- 239000012528 membrane Substances 0.000 claims description 21
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 19
- 239000011229 interlayer Substances 0.000 claims description 16
- 230000008021 deposition Effects 0.000 claims description 13
- 238000005137 deposition process Methods 0.000 claims description 12
- 230000001105 regulatory effect Effects 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 7
- -1 grid Substances 0.000 claims description 6
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 15
- 239000011248 coating agent Substances 0.000 description 11
- 238000000576 coating method Methods 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 8
- 238000009826 distribution Methods 0.000 description 7
- 230000003287 optical effect Effects 0.000 description 7
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- 238000005499 laser crystallization Methods 0.000 description 6
- 238000002425 crystallisation Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 238000001259 photo etching Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 2
- 238000005660 chlorination reaction Methods 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000006356 dehydrogenation reaction Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000001953 recrystallisation Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000004050 hot filament vapor deposition Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- Condensed Matter Physics & Semiconductors (AREA)
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- Thin Film Transistor (AREA)
Abstract
The invention discloses a preparation method of a low-temperature polycrystalline silicon thin film. The preparation method comprises the following steps: forming an amorphous silicon layer on a substrate; depositing an antireflection film on the amorphous silicon layer, wherein the refractive index of the antireflection film is gradually reduced along with the increase of the depositing thickness, and a maximum refractive index of the antireflection film is less than that of the amorphous silicon layer; performing laser annealing on the amorphous silicon layer to convert the amorphous silicon layer into a polycrystalline silicon thin film. According to the preparation method of the low-temperature polycrystalline silicon thin film, the antireflection film is arranged on the amorphous silicon layer; the light refractive index of the antireflection film is between that of air and that of amorphous silicon; furthermore, the refractive index of the antireflection film is reduced gradually along with the increase of the depositing thickness; due to the antireflection film, a refractive index difference value between media on the two sides of the interface can be reduced, thus reflecting the interface reflection and increasing the utilization rate of light energy.
Description
Technical field
The present invention relates to technical field of semiconductor preparation, particularly relate to the preparation method of a kind of low-temperature polysilicon film and thin-film transistor.
Background technology
Polysilicon (p-Si) film has much larger than amorphous silicon (a-Si) and the high carrier mobility intended with monocrystalline silicon comparability, normal replacement amorphous silicon is applied to the active layer of thin-film transistor (TFT), therefore shows in (AMLCD) and active organic LED (AMOLED) at the active liquid crystal of integrated peripheral drive and has very important application.The substrate of the polysilicon membrane of flat-panel monitor is the glass being difficult to bear high-temperature technology, and under the restriction of this condition, low temperature polycrystalline silicon (LTPS) technology is industry inevitable choice.
With regard to current technology, low-temperature polysilicon silicon technology mainly contains following several: short annealing solid phase crystallization method (RTA), quasi-molecule laser annealing crystallization method (ELA), metal induced lateral crystallization (MILC) and heated filament catalytic chemical gaseous phase deposition (Cat-CVD) etc.Wherein, ELA and MILC is that the use of current industrial circle is the most extensive.
In ELA technique, along with panel development from generation to generation, the area of panel constantly increases, and required laser energy constantly increases.Such as 4.5 generation LTPS production line needs, two pulse energies are the laser of 1000mJ and use, then need the laser of four same specifications to the laser that 6 generation LTPS production lines are used.And number of lasers more, it is higher that it realizes technical difficulty, and manufacture, maintenance cost also increases sharply.Under the condition of same laser power, can only compress crystallization beam cross section and amass, what bring thus is the decline of production capacity.Therefore, how improving the utilance of laser energy, improve production capacity, is the significant problem that ELA technique faces.
Summary of the invention
Based on this, be necessary for the problems referred to above, the preparation method of a kind of low-temperature polysilicon film and thin-film transistor is provided, effectively can improve the utilance of laser energy.
A preparation method for low-temperature polysilicon film, comprises the steps:
Substrate forms amorphous silicon layer;
Depositing antireflection film on described amorphous silicon layer, the refractive index of described antireflective coating reduces gradually along with the increase of deposit thickness, and the largest refractive index of described antireflective coating is less than the refractive index of described amorphous silicon layer;
Laser annealing process is carried out to described amorphous silicon layer, makes described amorphous silicon layer be converted into polysilicon membrane.
Wherein in an embodiment, described antireflective coating obtains by regulating the flow-rate ratio of silane, ammonia, nitrogen, nitrous oxide and perfluoroethane.
Wherein in an embodiment, described substrate temperature be 340 ~ 350 DEG C, reative cell pressure deposits described antireflective coating by plasma chemical vapor deposition under being the condition of 1200 ~ 1800 millitorrs.
Wherein in an embodiment, the deposition process of described antireflective coating is specially:
Regulate the flow-rate ratio of silane, ammonia and nitrogen, to form silicon nitride film layer on described amorphous silicon layer;
Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia, to form silicon nitride and silica mixed membranous layer;
Stop passing into ammonia, and regulate the flow-rate ratio of silane, nitrous oxide, to form membranous layer of silicon oxide;
Increase the flow of perfluoroethane gradually, to form Fluorin doped membranous layer of silicon oxide.
Wherein in an embodiment, the deposition process of described antireflective coating is specially:
In the deposition incipient stage, the flow-rate ratio regulating silane, ammonia and nitrogen is (24 ~ 27): (160 ~ 220): (350 ~ 450), to form silicon nitride film layer;
Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia, to form silicon nitride and silica mixed membranous layer;
Stop passing into ammonia, and regulate the flow-rate ratio of silane, nitrous oxide for (24 ~ 27): (160 ~ 220), to form membranous layer of silicon oxide;
Increase the flow of perfluoroethane gradually, form Fluorin doped membranous layer of silicon oxide, when the flow-rate ratio of nitrous oxide and perfluoroethane is (160 ~ 220): time (60 ~ 85), stop described deposition process.
Wherein in an embodiment, the thickness of described antireflective coating: d=(K+1/2) × (λ/2n);
Wherein, d is the thickness of antireflective coating;
K is natural number;
The wavelength of laser when λ is laser annealing process;
N is antireflective coating refractive index.
Wherein in an embodiment, before laser annealing process is carried out to described amorphous silicon, also comprise: etching processing is carried out to described antireflective coating, to remove the part antireflective coating on described amorphous silicon layer.
A preparation method for thin-film transistor, comprises the steps:
Substrate forms polysilicon membrane, and is formed with active layer by patterning processes;
Wherein, described polysilicon membrane is obtained by the preparation method of above-mentioned arbitrary described low-temperature polysilicon film.
Wherein in an embodiment, also comprise the steps:
Above described active layer, form gate insulator, grid, interlayer insulating film and source electrode and drain electrode, described source electrode is connected with described active layer respectively by via hole with described drain electrode.
Wherein in an embodiment, gate insulator, grid, interlayer insulating film and source electrode and drain electrode are formed to the top of described active layer, specifically comprise:
Gate insulator is formed above described active layer;
Above described gate insulator, form gate metal layer, and form grid by patterning processes;
Interlayer insulating film is formed above described grid;
Described gate insulator and described interlayer insulating film form via hole;
In described via hole, form source electrode and drain electrode, and described source electrode is connected with described active layer respectively with described drain electrode.
The preparation method of above-mentioned low-temperature polysilicon film, by being provided with antireflective coating on amorphous silicon layer, because the optical index of antireflective coating is between air and amorphous silicon, and the refractive index of antireflective coating reduces gradually along with the increase of deposit thickness, the refractive index difference of interface media of both sides can be reduced by antireflective coating, and then can boundary reflection be reduced, improve the utilance of light energy.
In addition, by carrying out etching processing to antireflective coating, utilize on amorphous silicon layer and build temperature gradient with or without antireflective coating, realize the controllable super-lateral growth of the grain crystalline direction of growth, can expand ELA process energy window, and the polysilicon membrane crystallite dimension of preparation is comparatively large, distribution uniform.
Accompanying drawing explanation
Fig. 1 is preparation method's schematic flow sheet of low-temperature polysilicon film in one embodiment of the invention;
Fig. 2 A-2H is respectively the structural representation of each step of the low-temperature polysilicon film shown in Fig. 1 in preparation process.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar improvement when intension of the present invention, therefore the present invention is by the restriction of following public specific embodiment.
Refer to Fig. 1, it is the flow chart of low-temperature polysilicon film preparation method in one embodiment of the invention.
S110, on substrate, form amorphous silicon layer.
Such as, using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique deposition of amorphous silicon layers on clean substrate.Such as, substrate is glass substrate or flexible base, board.And for example, depositing temperature general control is below 500 DEG C.
In the present embodiment, the thickness of amorphous silicon layer is 40nm ~ 60nm.Certainly, also can need according to concrete technique to select suitable thickness.Such as, the thickness of amorphous silicon layer is 42nm ~ 55nm, and and for example, the thickness of amorphous silicon layer is 45nm, 48nm, 52nm or 54nm.
In order to improve the adhesive force between amorphous silicon layer and substrate, preferably, also resilient coating is deposited between described amorphous silicon layer and described substrate.That is, substrate forms resilient coating, at the side formation amorphous silicon layer of resilient coating away from described substrate.By arranging resilient coating, the degree of adhesion between amorphous silicon and substrate can be improved, being conducive to reducing heat-conduction effect, slowing down by the cooldown rate of the silicon of LASER HEATING, be conducive to the crystallization of polysilicon.Meanwhile, can also prevent the metal ion in substrate from diffusing to active layer, reduce impurity defect, and the generation of leakage current can be reduced.Such as, the deposition materials of resilient coating can be the silica (SiO of individual layer
x) layer or silicon nitride (SiN
x) layer, or be silica (SiO
x) and silicon nitride (SiN
x) lamination.In the present embodiment, resilient coating is the silicon nitride layer and silicon oxide layer that stack gradually.The thickness of silicon nitride layer is 40 ~ 180nm, and the thickness of silicon oxide layer is 100 ~ 200nm.
S120, on described amorphous silicon layer depositing antireflection film, the refractive index of described antireflective coating reduces gradually along with the increase of deposit thickness, and the largest refractive index of described antireflective coating is less than the refractive index of described amorphous silicon layer.
Because the optical index of antireflective coating is between air and amorphous silicon, and the refractive index of antireflective coating reduces gradually along with the increase of deposit thickness, the refractive index difference of interface media of both sides can be reduced by antireflective coating, according to fresnel formula, and then can boundary reflection be reduced, improve the utilance of light energy.
Particularly, described antireflective coating is by regulating the flow-rate ratio preparation of silane, ammonia, nitrogen, nitrous oxide and perfluoroethane.Further, substrate temperature be 340 ~ 450 DEG C, under radio-frequency power is 20 ~ 200W, plate clearance be 500 ~ 1200 mils (mil) and reative cell pressure is the condition of 1200 millitorrs (mtorr) ~ 1800mtorr, by the mixed proportion regulating the flow of silane, ammonia, nitrous oxide and perfluoroethane to control reacting gas, generate different component film at the rete of different-thickness.
Such as, the deposition process of described antireflective coating is specially:
Regulate the flow-rate ratio of silane, ammonia and nitrogen, to form silicon nitride film layer on described amorphous silicon layer;
Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia gradually, to form silicon nitride and silica mixed membranous layer;
Stop passing into ammonia, and regulate the flow-rate ratio of silane, nitrous oxide, to form membranous layer of silicon oxide;
Increase the flow of perfluoroethane gradually, to form Fluorin doped membranous layer of silicon oxide.
Particularly, in the deposition incipient stage, the flow-rate ratio regulating silane, ammonia and nitrogen is (24 ~ 27): (160 ~ 220): (350 ~ 450), such as flow-rate ratio is the volume ratio under identical input speed, to form silicon nitride (SiN
x) rete; Continue input silane and nitrogen, such as, both maintaining respectively, flow proportional is constant; Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia gradually, make reaction generate silicon nitride (SiN
x) while, to generate silica (SiO
x); When the flow of ammonia is reduced to zero, the flow of nitrous oxide reaches maximum, and namely the flow-rate ratio of silane and nitrous oxide is (24 ~ 27): (160 ~ 220), all generates silica (SiO to make reaction
x) rete; Such as, now the flow-rate ratio of silane, nitrous oxide and nitrogen is (24 ~ 27): (160 ~ 220): (350 ~ 450); Increase the flow of perfluoroethane gradually, make reaction generate the membranous layer of silicon oxide (SiO of Fluorin doped
xf
y), along with the continuous increase of perfluoroethane flow, Fluorin doped concentration constantly increases, when nitrous oxide and perfluoroethane flow-rate ratio reach set point, namely the flow-rate ratio of nitrous oxide and perfluoroethane is (160 ~ 220): time (60 ~ 85), stop deposition process, such as, the flow-rate ratio stopping silane, nitrous oxide, perfluoroethane and nitrogen during deposition process is (24 ~ 27): (160 ~ 220): (60 ~ 85): (350 ~ 450).A good example is, in the deposition incipient stage, the flow-rate ratio regulating silane, ammonia and nitrogen is 25:200:400, and overall formation silane, ammonia and nitrogen are the flux of 1:8:16, to form silicon nitride (SiN
x) rete; Then input silane, nitrogen flow constant rate is maintained, increase the flow of nitrous oxide gradually, and reduce the flow of ammonia gradually, make the total amount of ammonia and nitrous oxide, be 1:2 with the flow-rate ratio of nitrogen, namely overallly keep silane, the flow-rate ratio of (ammonia and nitrous oxide) and nitrogen is 25:200:400, make reaction generate silicon nitride (SiN
x) while, to generate silica (SiO
x); When the flow of ammonia is reduced to zero, the flow of nitrous oxide reaches maximum, and namely the flow-rate ratio of silane, nitrous oxide and nitrogen is 25:200:400, all generates silica (SiO to make reaction
x) rete; Then keep the flow of silane, nitrous oxide and nitrogen, increase the flow of perfluoroethane gradually, make reaction generate the membranous layer of silicon oxide (SiO of Fluorin doped
xf
y), along with the continuous increase of perfluoroethane flow, Fluorin doped concentration constantly increases, when nitrous oxide and perfluoroethane flow-rate ratio reach set point, namely when the flow-rate ratio of nitrous oxide and perfluoroethane is 200:72, stop deposition process, such as, during stopping, the flow-rate ratio of silane, nitrous oxide, perfluoroethane and nitrogen is 25:200:72:400.
Because the refractive index of amorphous silicon is generally between 3.0 ~ 4.0, and the refractive index of silicon nitride is generally between 1.9 ~ 2.2, the refractive index of silica is generally between 1.4 ~ 1.6, and the refractive index of the silica of Fluorin doped is generally below 1.4, and the refractive index of air is 1.0, when light is from air vertical incidence, successively through the silica of Fluorin doped, silica, silicon nitride, enter amorphous silicon, because the refractive index of the medium interface of light process reduces gradually, effectively can reduce boundary reflection like this, namely, more the beam energy of vast scale can be transmitted to the inside of amorphous silicon film, thus absorbed by amorphous silicon, improve the utilance of luminous energy.Compared with the structure without antireflective coating, amorphous silicon is when laser crystallization, and the energy of laser at least can reduce by tens MJs of every square centimeter of (mJ/cm
2).
Further, the thickness of described antireflective coating is d=(K+1/2) × (λ/2n); Wherein, d is the thickness of antireflective coating; K is natural number; The wavelength of laser when λ is laser annealing process; N is antireflective coating refractive index, and like this, the reverberation in the upper and lower two medium faces of antireflective coating can interfere counteracting, reduces boundary reflection further.Preferably, K equals 1 or 2.
S130, laser annealing process is carried out to described amorphous silicon layer, make described amorphous silicon layer be converted into polysilicon membrane.
Such as, laser annealing can adopt the excimer lasers such as chlorination xenon (XeCl), KrF (KrF), argon fluoride (ArF).In the present embodiment, wavelength is adopted to be that the XeCl laser of 308nm is to carry out quasi-molecule laser annealing.Laser beam is linear light sorurce after optical system.
Such as, the pulse frequency of quasi-molecule laser annealing is 300 ~ 800Hz, and and for example, the pulse frequency of quasi-molecule laser annealing is 400 ~ 600Hz; And for example, the burst length is 20 ~ 30nm; And for example, Duplication is 92% ~ 97%; And for example, laser energy density is 250 ~ 600mJ/cm
2, and for example, laser energy density is 400 ~ 480mJ/cm
2; And for example, between pulse, energy hunting 6sigma value is less than 2.7%, and the beam cross-section energy uniformity (uniformity) 2sigma value major axis is less than 1.8%, minor axis is less than 3%.
Preferably, before carrying out laser annealing technique, need to carry out dehydrogenation to amorphous silicon layer, make hydrogen content be down to less than 1%, prevent the generation of the quick-fried phenomenon of hydrogen.Such as, thermal anneal process is adopted to be got rid of from amorphous silicon layer by hydrogen.And for example, the temperature of thermal anneal process is 490 DEG C, and the time is 10min.
Further, before laser annealing process is carried out to described amorphous silicon layer, also comprise: etching processing is carried out to described antireflective coating, to remove the part antireflective coating on described amorphous silicon layer.Particularly, antireflective coating on described amorphous silicon layer non-channel region to be formed is etched, to remove the antireflective coating on non-channel region, retain the antireflective coating on channel region to be formed on amorphous silicon layer, namely, the top of channel region to be formed is provided with antireflective coating, the top of non-channel region is without antireflective coating, in laser crystallization process, the amorphous silicon layer efficiency of light energy utilization being provided with antireflective coating is higher, the amorphous silicon layer efficiency of light energy utilization without antireflective coating is lower, so there is the amorphous silicon layer melting completely of antireflective coating, amorphous silicon layer without antireflective coating is also in non-melt state, namely, when cooling recrystallization, recrystal grain will be " seed " with the solid-state crystallite that low-temperature region is remaining, grow to high-temperature area, realize the controllable super-lateral growth of the grain crystalline direction of growth, ELA process energy window can be expanded, and the polysilicon membrane crystallite dimension of preparation is larger, distribution uniform.In other words, in laser crystallization process, utilize channel region and non-channel region with or without the difference of antireflective coating, realize crystal grain from non-channel region to the super-lateral growth of channel region, the crystal grain making channel region is comparatively large, distribution uniform, thus reduce polysilicon membrane leakage current, improve carrier mobility.
In an embodiment of the present invention, make after described amorphous silicon layer is converted into polysilicon membrane, also to comprise step: remove described antireflective coating.Particularly, described antireflective coating is removed by lithographic method.It should be noted that, remove described antireflective coating and can adopt dry etching technology well known to those skilled in the art, do not repeat them here.
The preparation method of above-mentioned low-temperature polysilicon film, by being provided with antireflective coating on amorphous silicon layer, because the optical index of antireflective coating is between air and amorphous silicon, and the refractive index of antireflective coating reduces gradually along with the increase of deposit thickness, the refractive index difference of interface media of both sides can be reduced by antireflective coating, and then can boundary reflection be reduced, improve the utilance of light energy.
In addition, by carrying out etching processing to antireflective coating, utilize on amorphous silicon layer and build temperature gradient with or without antireflective coating, realize the controllable super-lateral growth of the grain crystalline direction of growth, can expand ELA process energy window, and the polysilicon membrane crystallite dimension of preparation is comparatively large, distribution uniform.
Preparation in accordance with the present invention obtains the making that low-temperature polysilicon film not only can be used for thin-film transistor, and can be used for solar cell material, or in the making of other semiconductor device.
Another embodiment of the present invention also provides a kind of preparation method of thin-film transistor, and it comprises the steps:
Substrate forms polysilicon membrane, and is formed with active layer by patterning processes;
Above described active layer, form gate insulator, grid, interlayer insulating film and source electrode and drain electrode, described source electrode is connected with described active layer respectively by via hole with drain electrode.
Wherein, described polysilicon membrane adopts step S110 ~ S130 to obtain.
Particularly, gate insulator, grid, interlayer insulating film and source electrode and drain electrode are formed to the top of described active layer, specifically comprise:
Gate insulator is formed above described active layer;
Above described gate insulator, form gate metal layer, and form grid by patterning processes;
Interlayer insulating film is formed above described grid;
Described gate insulator and described interlayer insulating film form via hole;
In described via hole, form source electrode and drain electrode, and described source electrode is connected with described active layer with drain electrode.
And for example, the preparation method of the thin-film transistor of another embodiment of the present invention.Refer to Fig. 2 A to Fig. 2 H, it is the structural representation that in the preparation method of thin-film transistor in one embodiment of the invention, each step is corresponding.
S101, on the substrate 100 formed resilient coating 200, its complete after sectional view refer to Fig. 2 A.
Such as, plasma chemical vapor deposition (PECVD) is utilized to deposit the certain thickness resilient coating of one deck on the glass substrate.Deposition materials can be the silica (SiO of individual layer
x) rete or silicon nitride (SiN
x) rete, or be silica (SiO
x) and silicon nitride (SiN
x) lamination.Such as, the deposition materials of resilient coating 200 can be the silica (SiO of individual layer
x) layer or silicon nitride (SiN
x) layer, or be silica (SiO
x) and silicon nitride (SiN
x) lamination.In the present embodiment, resilient coating is the silicon nitride layer and silicon oxide layer that stack gradually.The thickness of silicon nitride layer is 40 ~ 180nm, and the thickness of silicon oxide layer is 100 ~ 200nm.
S102, on resilient coating 200, form amorphous silicon layer 300, its complete after sectional view refer to Fig. 2 B.
Such as, using plasma strengthens chemical vapour deposition (CVD) (PECVD) technique deposition of amorphous silicon layers on the buffer layer.And for example, depositing temperature general control is below 500 DEG C.
In the present embodiment, the thickness of amorphous silicon layer is 40nm ~ 60nm.Certainly, also can need according to concrete technique to select suitable thickness.Such as, the thickness of amorphous silicon layer is 42nm ~ 55nm, and and for example, the thickness of amorphous silicon layer is 45nm, 48nm, 52nm or 54nm.
S103, on amorphous silicon layer 300 depositing antireflection film 400, the refractive index of antireflective coating 400 reduces gradually along with the increase of deposit thickness, and the largest refractive index of antireflective coating 400 is less than the refractive index of described amorphous silicon layer 300, its complete after sectional view refer to Fig. 2 C.
Because the optical index of antireflective coating is between air and amorphous silicon, and the refractive index of antireflective coating reduces gradually along with the increase of deposit thickness, the refractive index difference of interface media of both sides can be reduced by antireflective coating, according to fresnel formula, and then can boundary reflection be reduced, improve the utilance of light energy.
Particularly, described antireflective coating is by regulating the flow-rate ratio preparation of silane, ammonia, nitrogen, nitrous oxide and perfluoroethane.Further, the temperature of substrate be 340 ~ 450 DEG C, under radio-frequency power is 20 ~ 200W, plate clearance be 500 ~ 1200mil and reative cell pressure is the condition of 1200mtorr ~ 1800mtorr, by the mixed proportion regulating the flow of silane, ammonia, nitrous oxide and perfluoroethane to control reacting gas, generate different component film at the rete of different-thickness.
Such as, the deposition process of described antireflective coating is specially:
Regulate the flow-rate ratio of silane, ammonia and nitrogen, to form silicon nitride film layer on described amorphous silicon layer;
Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia gradually, to form silicon nitride and silica mixed membranous layer;
Stop passing into ammonia, and regulate the flow-rate ratio of silane, nitrous oxide to be, to form membranous layer of silicon oxide;
Increase the flow of perfluoroethane gradually, to form Fluorin doped membranous layer of silicon oxide.
Particularly, in the deposition incipient stage, the flow-rate ratio regulating silane, ammonia and nitrogen is (24 ~ 27): (160 ~ 220): (350 ~ 450), to form silicon nitride (SiN
x) rete; Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia gradually, make reaction generate silicon nitride (SiN
x) while, generate silica (SiO
x); When the flow of ammonia is reduced to zero, the flow of nitrous oxide reaches maximum, and namely the flow-rate ratio of silane and nitrous oxide is (24 ~ 27): (160 ~ 220), makes reaction all generate silica (SiO
x) rete; Increase the flow of perfluoroethane gradually, make reaction generate the membranous layer of silicon oxide (SiO of Fluorin doped
xf
y), along with the continuous increase of perfluoroethane flow, Fluorin doped concentration constantly increases, when nitrous oxide and perfluoroethane flow-rate ratio reach set point, namely the flow-rate ratio of nitrous oxide and perfluoroethane is (160 ~ 220): time (60 ~ 85), stops deposition process.
Because the refractive index of amorphous silicon is generally between 3.0 ~ 4.0, and the refractive index of silicon nitride is generally between 1.9 ~ 2.2, the refractive index of silica is generally between 1.4 ~ 1.6, and the refractive index of the silica of Fluorin doped is generally below 1.4, and the refractive index of air is 1.0, when light is from air vertical incidence, successively through the silica of Fluorin doped, silica, silicon nitride, enter amorphous silicon, because the refractive index of the medium interface of light process reduces gradually, effectively can reduce boundary reflection like this, namely, more the beam energy of vast scale can be transmitted to the inside of amorphous silicon film, thus absorbed by amorphous silicon, improve the utilance of luminous energy.Compared with the structure without antireflective coating, amorphous silicon is when laser crystallization, and the energy of laser at least can reduce by tens MJs of every square centimeter of (mJ/cm
2).
Further, the thickness of described antireflective coating is d=(K+1/2) × (λ/2n); Wherein, d is the thickness of antireflective coating; K is natural number; The wavelength of laser when λ is laser annealing process; N is antireflective coating refractive index, and like this, the reverberation in the upper and lower two medium faces of antireflective coating can interfere counteracting, reduces boundary reflection further.Preferably, K equals 1 or 2.
S104, etching processing is carried out to antireflective coating 400, to remove the part antireflective coating 400 on amorphous silicon layer 300, its complete after sectional view refer to Fig. 2 D.
Particularly, antireflective coating 400 on amorphous silicon layer 300 non-channel region to be formed is etched, to remove the antireflective coating 400 on non-channel region, retain the antireflective coating 400 on channel region to be formed on amorphous silicon layer 300, namely, the top of channel region to be formed is provided with antireflective coating, the top of non-channel region is without antireflective coating, in laser crystallization process, the amorphous silicon layer efficiency of light energy utilization being provided with antireflective coating is higher, the amorphous silicon layer efficiency of light energy utilization without antireflective coating is lower, so be provided with the amorphous silicon layer melting completely of antireflective coating, amorphous silicon layer without antireflective coating is also in non-melt state, namely, when cooling recrystallization, recrystal grain will be " seed " with the solid-state crystallite that low-temperature region is remaining, grow to high-temperature area, realize the controllable super-lateral growth of the grain crystalline direction of growth, ELA process energy window can be expanded, and the polysilicon membrane crystallite dimension of preparation is larger, distribution uniform.In other words, in laser crystallization process, utilize channel region and non-channel region with or without the difference of antireflective coating, realize crystal grain from non-channel region to the super-lateral growth of channel region, the crystal grain making channel region is comparatively large, distribution uniform, thus reduce polysilicon membrane leakage current, improve carrier mobility.
S105, laser annealing process is carried out to amorphous silicon layer 300, makes amorphous silicon layer 300 form polysilicon membrane 500, its complete after sectional view refer to Fig. 2 E.
Such as, laser annealing can adopt the excimer lasers such as chlorination xenon (XeCl), KrF (KrF), argon fluoride (ArF).In the present embodiment, wavelength is adopted to be that the XeCl laser of 308nm is to carry out quasi-molecule laser annealing.Laser beam is linear light sorurce after optical system.
Such as, the pulse frequency of quasi-molecule laser annealing is 300 ~ 800Hz, and and for example, the pulse frequency of quasi-molecule laser annealing is 400 ~ 600Hz; And for example, the burst length is 20 ~ 30nm; And for example, Duplication is 92% ~ 97%; And for example, laser energy density is 250 ~ 600mJ/cm
2, and for example, laser energy density is 400 ~ 480mJ/cm
2; And for example, between pulse, energy hunting 6sigma value is less than 2.7%, and the beam cross-section energy uniformity (uniformity) 2sigma value major axis is less than 1.8%, minor axis is less than 3%.
Preferably, before carrying out laser annealing technique, need to carry out dehydrogenation to amorphous silicon layer, make hydrogen content be down to less than 1%, prevent the generation of the quick-fried phenomenon of hydrogen.Such as, thermal anneal process is adopted to be got rid of from amorphous silicon layer by hydrogen.And for example, the temperature of thermal anneal process is 490 DEG C, and the time is 10min.
S106, removing polysilicon membrane 500 on antireflective coating 400, its complete after sectional view refer to Fig. 2 F.
Particularly, described antireflective coating is removed by lithographic method.It should be noted that, remove described antireflective coating and can adopt dry etching technology well known to those skilled in the art, do not repeat them here.
S107, patterning processes is carried out to polysilicon membrane 500, be formed with active layer 510, refer to Fig. 2 G.
Particularly, utilize photoetching process to form mask, adopt dry etching method to form silicon island, obtain the active layer comprising channel region and non-channel region.
It should be noted that, the order of step S106 and step S107 can be exchanged.
S108, above active layer 510, form gate insulator 600, grid 700, interlayer insulating film 800 and source electrode 910 and drain electrode, source electrode 910 and draining 920 is connected with active layer respectively by via hole, its complete after sectional view refer to Fig. 2 H.
Particularly, comprise the steps:
S1081, on active layer 510 deposition of gate insulating barrier 600.
Such as, adopt chemical gaseous phase depositing process, the substrate defining active layer forms gate insulator.And for example, depositing temperature general control is below 500 DEG C.And for example, the thickness of gate insulator can be 80 ~ 200nm, also can need to select suitable thickness according to concrete technology.And for example, gate insulator adopts silica, the silicon nitride of individual layer, or the lamination of the two.
S1082, on gate insulator 600 deposition of gate metal level, by patterning processes formed grid 700.
In the present embodiment, the process that gate insulator is formed gate metal layer can adopt the step of formation grid well known to those skilled in the art, as first formed gate metal layer at gate insulator, then the operation such as photoetching and wet etching is carried out to gate metal layer and finally on gate insulator, form grid, do not limit at this.
S1082, on grid 700, form interlayer insulating film 800.
S108, on gate insulator 600 and interlayer insulating film 800 etching formed via hole.
S109, in described via hole, form source electrode 910 and drain electrode 920, and source electrode 910 920 to be connected with active layer 510 respectively with draining.
In the present embodiment, the process forming source electrode and drain electrode in described via hole can adopt the step of formation grid well known to those skilled in the art.Such as, adopt the conventional thin film-forming methods such as magnetron sputtering in via hole and on interlayer insulating film, to form metal film, then the operation such as photoetching and wet etching is carried out to metal film and form source electrode and drain electrode.
The preparation method of above-mentioned thin-film transistor, by being provided with antireflective coating on amorphous silicon layer, because the optical index of antireflective coating is between air and amorphous silicon, and the refractive index of antireflective coating reduces gradually along with the increase of deposit thickness, the refractive index difference of interface media of both sides can be reduced by antireflective coating, and then can boundary reflection be reduced, improve the utilance of light energy.
In addition, by carrying out etching processing to antireflective coating, utilize on amorphous silicon layer and build temperature gradient with or without antireflective coating, realize the controllable super-lateral growth of the grain crystalline direction of growth, can expand ELA process energy window, and the polysilicon membrane crystallite dimension of preparation is comparatively large, distribution uniform.
Each technical characteristic of the above embodiment can combine arbitrarily, for making description succinct, the all possible combination of each technical characteristic in above-described embodiment is not all described, but, as long as the combination of these technical characteristics does not exist contradiction, be all considered to be the scope that this specification is recorded.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but can not therefore be construed as limiting the scope of the patent.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a preparation method for low-temperature polysilicon film, is characterized in that, comprises the steps:
Substrate forms amorphous silicon layer;
Depositing antireflection film on described amorphous silicon layer, the refractive index of described antireflective coating reduces gradually along with the increase of deposit thickness, and the largest refractive index of described antireflective coating is less than the refractive index of described amorphous silicon layer;
Laser annealing process is carried out to described amorphous silicon layer, makes described amorphous silicon layer be converted into polysilicon membrane.
2. the preparation method of low-temperature polysilicon film according to claim 1, is characterized in that, described antireflective coating obtains by regulating the flow-rate ratio of silane, ammonia, nitrogen, nitrous oxide and perfluoroethane.
3. the preparation method of low-temperature polysilicon film according to claim 2, it is characterized in that, described substrate temperature be 340 ~ 350 DEG C, reative cell pressure deposits described antireflective coating by plasma chemical vapor deposition under being the condition of 1200 ~ 1800 millitorrs.
4. the preparation method of low-temperature polysilicon film according to claim 3, is characterized in that, the deposition process of described antireflective coating is specially:
Regulate the flow-rate ratio of silane, ammonia and nitrogen, to form silicon nitride film layer on described amorphous silicon layer;
Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia, to form silicon nitride and silica mixed membranous layer;
Stop passing into ammonia, and regulate the flow-rate ratio of silane, nitrous oxide, to form membranous layer of silicon oxide;
Increase the flow of perfluoroethane gradually, to form Fluorin doped membranous layer of silicon oxide.
5. the preparation method of low-temperature polysilicon film according to claim 4, is characterized in that, the deposition process of described antireflective coating is specially:
In the deposition incipient stage, the flow-rate ratio regulating silane, ammonia and nitrogen is (24 ~ 27): (160 ~ 220): (350 ~ 450), to form silicon nitride film layer;
Increase the flow of nitrous oxide gradually, and reduce the flow of ammonia, to form silicon nitride and silica mixed membranous layer;
Stop passing into ammonia, and regulate the flow-rate ratio of silane, nitrous oxide for (24 ~ 27): (160 ~ 220), to form membranous layer of silicon oxide;
Increase the flow of perfluoroethane gradually, form Fluorin doped membranous layer of silicon oxide, when the flow-rate ratio of nitrous oxide and perfluoroethane is (160 ~ 220): time (60 ~ 85), stop described deposition process.
6. the preparation method of low-temperature polysilicon film according to claim 4, is characterized in that, the thickness of described antireflective coating: d=(K+1/2) × (λ/2n);
Wherein, d is the thickness of antireflective coating;
K is natural number;
The wavelength of laser when λ is laser annealing process;
N is antireflective coating refractive index.
7. the preparation method of low-temperature polysilicon film according to claim 1, it is characterized in that, before laser annealing process is carried out to described amorphous silicon, also comprise: etching processing is carried out to described antireflective coating, to remove the part antireflective coating on described amorphous silicon layer.
8. a preparation method for thin-film transistor, is characterized in that, comprises the steps:
Substrate forms polysilicon membrane, and is formed with active layer by patterning processes;
Wherein, described polysilicon membrane is obtained by the preparation method of described low-temperature polysilicon film arbitrary in claim 1 ~ 7.
9. the preparation method of thin-film transistor according to claim 8, is characterized in that, also comprises the steps:
Above described active layer, form gate insulator, grid, interlayer insulating film and source electrode and drain electrode, described source electrode is connected with described active layer respectively by via hole with described drain electrode.
10. the preparation method of thin-film transistor according to claim 9, is characterized in that, forms gate insulator, grid, interlayer insulating film and source electrode and drain electrode, specifically comprise the top of described active layer:
Gate insulator is formed above described active layer;
Above described gate insulator, form gate metal layer, and form grid by patterning processes;
Interlayer insulating film is formed above described grid;
Described gate insulator and described interlayer insulating film form via hole;
In described via hole, form source electrode and drain electrode, and described source electrode is connected with described active layer respectively with described drain electrode.
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