CN104465401A - Thin film transistor low-temperature polycrystalline silicon thin film manufacturing method - Google Patents
Thin film transistor low-temperature polycrystalline silicon thin film manufacturing method Download PDFInfo
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- CN104465401A CN104465401A CN201410776780.9A CN201410776780A CN104465401A CN 104465401 A CN104465401 A CN 104465401A CN 201410776780 A CN201410776780 A CN 201410776780A CN 104465401 A CN104465401 A CN 104465401A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 44
- 239000010409 thin film Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 238000000034 method Methods 0.000 claims abstract description 45
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 14
- 239000011521 glass Substances 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000009413 insulation Methods 0.000 claims description 110
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 58
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 40
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 239000013078 crystal Substances 0.000 claims description 30
- 239000010408 film Substances 0.000 claims description 30
- 238000002360 preparation method Methods 0.000 claims description 26
- 239000012528 membrane Substances 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 12
- 229910052760 oxygen Inorganic materials 0.000 claims description 12
- 239000001301 oxygen Substances 0.000 claims description 12
- 238000000059 patterning Methods 0.000 claims description 12
- 230000000694 effects Effects 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000002425 crystallisation Methods 0.000 claims description 7
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 6
- 230000008025 crystallization Effects 0.000 claims description 6
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000005224 laser annealing Methods 0.000 claims description 6
- 238000004781 supercooling Methods 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 2
- 239000011248 coating agent Substances 0.000 abstract description 2
- 238000000576 coating method Methods 0.000 abstract description 2
- 238000004321 preservation Methods 0.000 abstract 3
- 229910021419 crystalline silicon Inorganic materials 0.000 abstract 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 230000005012 migration Effects 0.000 abstract 1
- 238000013508 migration Methods 0.000 abstract 1
- 239000000203 mixture Substances 0.000 abstract 1
- 230000005855 radiation Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 230000003471 anti-radiation Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000001579 optical reflectometry Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
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- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Abstract
The invention discloses a thin film transistor low-temperature polycrystalline silicon thin film manufacturing method. The method includes the steps of firstly, sequentially depositing an isolation layer, a non-crystalline silicon layer and an anti-reflection heat preservation layer on a glass substrate where a TFT metal grid is plated in advance; secondly, coating the anti-reflection heat preservation layer with photoresist through a picture composition process, and conducting mask exposure and developing through the TFT metal grid; thirdly, etching the portion, in a non-channel area, of the anti-reflection heat preservation layer, and conducting demolding on the photoresist; fourthly, conducting laser radiation so that the non-crystalline silicon of a channel area can be converted into large-size polycrystalline silicon. By means of the technical scheme, the temperature gradient of the TFT channel area and the non-channel area can be formed, the manual-control super transverse growth of crystalline grain from the non-channel area to the channel area can be achieved, the TFT channel area has only one grain boundary, and therefore the carrier migration rate is increased, and the performance of a device in a channel is uniform.
Description
Technical field
The present invention relates to technical field of semiconductor device preparation, particularly relate to a kind of thin-film transistor low-temperature polysilicon film preparation method.
Background technology
Polysilicon (p-Si) film has much larger than amorphous silicon (a-Si) and the high carrier mobility intended with monocrystalline silicon comparability, usually be applied to thin-film transistor (TFT, Thin Film Transistor) active layer, such as active liquid crystal display (AMOLCD) and active organic LED (AMOLED) in there is very important application.
The substrate of the polysilicon membrane of flat-panel monitor is normally difficult to the glass bearing high-temperature technology, under the restriction of this condition, and industry inevitable choice development low temperature polycrystalline silicon (LTPS) technology.Inventor finds under study for action, and the crystal boundary number adopting low-temperature polysilicon film to contain at TFT raceway groove place in conventional art is different, can cause the problem of device performance inequality, and its carrier mobility can further improve.Solve this problem and certainly can carry out alternative polysilicon membrane with monocrystalline silicon thin film, but flat-panel monitor preparation cost can be improved.Therefore, only need the crystal grain-growth of control TFT channel region, make channel region in the ideal case only containing a crystal boundary, thus improve carrier mobility further, and make device performance even.
Summary of the invention
Based on this, be necessary to provide a kind of thin-film transistor low-temperature polysilicon film preparation method, application technical solution of the present invention, the temperature gradient of TFT channel region and non-channel region can be formed, realize crystal grain laterally to grow up from non-channel region to the Artificial Control of channel region is super, make TFT channel region only containing a crystal boundary, thus improve carrier mobility, and make device even in the performance at raceway groove place.
A kind of thin-film transistor low-temperature polysilicon film preparation method, is applied in the thin-film transistor of the structure of falling grid, comprises:
Layer deposited isolating, amorphous silicon layer and antireflection heat-insulation layer successively on the glass substrate being coated with TFT metal gates in advance;
Utilize patterning processes to apply photoresist on antireflection heat-insulation layer, and utilize TFT metal gates carry out mask exposure and develop;
The antireflection heat-insulation layer of non-channel region is etched, and demoulding process is carried out to photoresist, to make that the amorphous silicon layer at channel region place has antireflection heat-insulation layer, but not nonreactive reflective thermal-insulating layer on the amorphous silicon layer at channel region place;
Carry out laser irradiation, utilize channel region and non-channel region to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the non-channel region of crystal grain and laterally grow up to the Artificial Control of channel region is super, thus be large scale polysilicon by the amorphous silicon of channel region.
In one embodiment, described separator, described antireflection heat-insulation layer comprise the combination of silica membrane or silicon nitride film or two kinds of films;
The thickness of described antireflection heat-insulation layer is the odd-multiple of 1/4 wavelength of described laser;
Described antireflection heat-insulation layer extends the super cooling time of amorphous silicon crystallization, plays insulation effect.
In one embodiment, described separator, described amorphous silicon layer and described antireflection heat-insulation layer adopt PECVD method to prepare;
If described antireflection heat-insulation layer is silica membrane, the preparation method of described silica membrane also to comprise in ozone solution ablution, oxygen atmosphere heating in laser irradiation and oxygen atmosphere.
In one embodiment, the described patterning processes that utilizes applies photoresist on antireflection heat-insulation layer, and utilize TFT metal gates carry out mask exposure and development step comprise:
Utilize patterning processes to apply positive photoresist on antireflection heat-insulation layer, and carry out ultraviolet exposure and develop.
In one embodiment, describedly carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be the step of large scale polysilicon by the amorphous silicon of channel region, comprising:
Quasi-molecule laser annealing mode is adopted to carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be large scale polysilicon by the amorphous silicon of channel region.
A kind of thin-film transistor low-temperature polysilicon film preparation method, is applied in the thin-film transistor of top gate structure, comprises:
Layer deposited isolating, amorphous silicon layer and antireflection heat-insulation layer successively on the glass substrate;
Utilize patterning processes to apply photoresist on antireflection heat-insulation layer, and utilize TFT gate mask plate carry out mask exposure and develop;
The antireflection heat-insulation layer of non-channel region is etched, and demoulding process is carried out to photoresist, to make that the amorphous silicon layer at channel region place has antireflection heat-insulation layer, but not nonreactive reflective thermal-insulating layer on the amorphous silicon layer at channel region place;
Carry out laser irradiation, utilize channel region and non-channel region to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the non-channel region of crystal grain and laterally grow up to the Artificial Control of channel region is super, thus be large scale polysilicon by the amorphous silicon of channel region.
In one embodiment, described separator, described antireflection heat-insulation layer comprise the combination of silica membrane or silicon nitride film or two kinds of films;
The thickness of described antireflection heat-insulation layer is the odd-multiple of 1/4 wavelength of described laser;
Described anti-radiation heat-insulation layer extends the super cooling time of amorphous silicon crystallization, plays insulation effect.
In one embodiment, described separator, described amorphous silicon layer and described antireflection heat-insulation layer adopt PECVD method to prepare;
If be silica membrane in described antireflection heat-insulation layer, the preparation method of described silica membrane also to comprise in ozone solution ablution, oxygen atmosphere heating in laser irradiation and oxygen atmosphere.
In one embodiment, the described patterning processes that utilizes applies photoresist on antireflection heat-insulation layer, and utilize TFT gate mask plate carry out mask exposure and development step comprise:
If exposure area is channel region, then apply negative photoresist, and carry out ultraviolet exposure and develop;
If exposure area is non-channel region, then apply positive photoresist, and carry out ultraviolet exposure and develop.
In one embodiment, describedly carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be the step of large scale polysilicon by the amorphous silicon of channel region, comprising:
Quasi-molecule laser annealing mode is adopted to carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be large scale polysilicon by the amorphous silicon of channel region.
Above-mentioned thin-film transistor low-temperature polysilicon film preparation method, layer deposited isolating successively, amorphous silicon layer and antireflection heat-insulation layer, and photoresist is applied on antireflection heat-insulation layer, expose, and then the antireflection heat-insulation layer of non-channel region to be etched and to the process of photoresist demoulding, thus on formation channel region containing antireflection heat-insulation layer but not channel region not containing antireflection heat-insulation layer, so in the step that post laser irradiates, can formation temperature gradient, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, control the grain size of polysilicon membrane at TFT channel region, make this region only containing a crystal boundary, thus raising carrier mobility, and make the device performance at raceway groove place even.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the thin-film transistor low-temperature polysilicon film preparation method in an embodiment;
Fig. 2 (A) to Fig. 2 (C) is the certain applications scene graph of the thin-film transistor low-temperature polysilicon film preparation method in an embodiment;
Fig. 3 is the sharp light-struck application scenarios figure in an embodiment;
Fig. 4 is that in an embodiment, laser irradiates the principle schematic controlling grain growth;
Fig. 5 is the schematic flow sheet of the thin-film transistor low-temperature polysilicon film preparation method in an embodiment;
Fig. 6 (A) to Fig. 6 (C) is the certain applications scene graph of the thin-film transistor low-temperature polysilicon film preparation method in an embodiment.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
See Fig. 1, Fig. 2 (A) to Fig. 2 (C), provide a kind of thin-film transistor low-temperature polysilicon film preparation method in one embodiment.The method is applied in the preparation process of the thin-film transistor of the structure of falling grid, and the method comprises:
Step 101, layer deposited isolating, amorphous silicon layer and antireflection heat-insulation layer successively on the glass substrate being coated with TFT metal gates in advance.
Concrete, as Fig. 2 (A), in the thin-film transistor preparation process of the structure of falling grid, on glass substrate 1, be coated with TFT metal gates 2 in advance.This step, successively layer deposited isolating 3, amorphous silicon layer 4 and antireflection heat-insulation layer 5 successively on TFT metal gates 2 and glass substrate 1.Separator 3 is as the gate insulation layer in the structure of falling grid.
In one embodiment, separator 3, antireflection heat-insulation layer 5 comprise the combination of silica membrane or silicon nitride film or two kinds of films.Because the optical index of silicon dioxide or silicon nitride is between air and silicon, the refringence of medium interface effectively can be reduced by silicon dioxide or silicon nitride, according to fresnel formula, and then just can reduce light reflectivity, in addition, antireflection insulation layer thickness can be set to the odd-multiple of laser 1/4 wavelength further, and the reverberation in the upper and lower two medium faces of antireflection heat-insulation layer can interfere, and reduces reflection further.Therefore, antireflection heat-insulation layer plays antireflecting effect when laser irradiates, and plays insulation effect at the postradiation amorphous silicon of laser at crystallization cooling stage.
In one embodiment, separator 3, amorphous silicon layer 4 and antireflection heat-insulation layer 5 adopt plasma reinforced chemical vapour deposition (PECVD) method to prepare, if in antireflection heat-insulation layer be silica membrane, then the preparation method of silica membrane also to comprise in ozone solution ablution, oxygen atmosphere heating in laser irradiation and oxygen atmosphere.
Step 102, utilizes patterning processes to apply photoresist on antireflection heat-insulation layer, and utilizes TFT metal gates carry out mask exposure and develop.
Concrete, as Fig. 2 (B), antireflection heat-insulation layer 5 applies positive photoresist 6, utilize TFT metal gates 2 to carry out ultraviolet 8 and expose, exposure area is non-channel region.
Step 103, etches the antireflection heat-insulation layer of non-channel region, and carries out demoulding process to photoresist, to make that the amorphous silicon layer at channel region place has antireflection heat-insulation layer, but not nonreactive reflective thermal-insulating layer on the amorphous silicon layer at channel region place.
Concrete, the antireflection heat-insulation layer of non-channel region is etched, and demoulding process is carried out to photoresist, obtain the structure as Fig. 2 (C), containing antireflection heat-insulation layer above the amorphous silicon of channel region, and not containing antireflection heat-insulation layer above the amorphous silicon of non-channel region, in the step that post laser irradiates, with or without the effect of antireflection heat-insulation layer, just can formation temperature gradient.
Step 104, carry out laser irradiation, utilize channel region and non-channel region to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the non-channel region of crystal grain and laterally grow up to the Artificial Control of channel region is super, thus be large scale polysilicon by the amorphous silicon of channel region.
Concrete, as Fig. 3, wherein 9 is laser beam moving direction, 10 is laser beam, quasi-molecule laser annealing mode is adopted to carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be large scale polysilicon by the amorphous silicon of channel region, its principle is as Fig. 4: irradiated by laser and amorphous silicon is become molten state, because the top of channel region and non-channel region is with or without the difference of antireflection heat-insulation layer 5, there is temperature gradient in channel region and non-channel region, in the process of crystallisation by cooling, 11 are in the silicon thin film of complete molten state for channel region, 12 is non-channel region non-fully molten state silicon thin film, 13 is the direction of crystal grain-growth, 14 is the large-sized polysilicon grain for recrystallization, 15 crystal boundaries met in channels for the crystal grain-growth of raceway groove both sides.
Above-mentioned thin-film transistor low-temperature polysilicon film preparation method, be applied to the thin-film transistor of the structure of falling grid, layer deposited isolating successively on the glass substrate being coated with TFT metal gates in advance, amorphous silicon layer and antireflection heat-insulation layer, and photoresist is applied on antireflection heat-insulation layer, expose, and then the antireflection heat-insulation layer of non-channel region to be etched and to the process of photoresist demoulding, thus on formation channel region containing antireflection heat-insulation layer but not channel region not containing antireflection heat-insulation layer, so in the step that post laser irradiates, can formation temperature gradient, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, control the grain size of polysilicon membrane at TFT channel region, make this region only containing a crystal boundary, thus raising carrier mobility, and make the device performance at raceway groove place even.
See Fig. 5, Fig. 6 (A) to Fig. 6 (C), provide a kind of thin-film transistor low-temperature polysilicon film preparation method in one embodiment, be applied in the thin-film transistor of top gate structure, the method comprises:
Step 501, on the glass substrate layer deposited isolating, amorphous silicon layer and antireflection heat-insulation layer successively.
Concrete, as Fig. 6 (A), layer deposited isolating 3, amorphous silicon layer 4 and antireflection heat-insulation layer 5 successively on glass substrate 1 successively.Separator 3 is as the TFT resilient coating in top gate structure.
In one embodiment, separator 3, antireflection heat-insulation layer 5 comprise the combination of silica membrane or silicon nitride film or two kinds of films.Separator 3, amorphous silicon layer 4 and antireflection heat-insulation layer 5 adopt plasma reinforced chemical vapour deposition (PECVD) method to prepare, if antireflection heat-insulation layer is silica membrane, then the preparation method of silica membrane also to comprise in ozone solution ablution, oxygen atmosphere heating in laser irradiation and oxygen atmosphere.Antireflection heat-insulation layer plays antireflecting effect when laser irradiates, and plays insulation effect at the postradiation amorphous silicon of laser at crystallization cooling stage.
Step 502, utilizes patterning processes to apply photoresist on antireflection heat-insulation layer, and utilizes TFT gate mask plate carry out mask exposure and develop.
Concrete, as Fig. 6 (B), if exposure area is channel region, then apply negative photo 6, and utilize gate mask plate 7 to carry out ultraviolet 8 to expose, if exposure area is non-channel region, then apply positive photoresist 6, and utilize gate mask plate 7 to carry out ultraviolet 8 to expose.
Step 503, etches the antireflection heat-insulation layer of non-channel region, and carries out demoulding process to photoresist, to make that the amorphous silicon layer at channel region place has antireflection heat-insulation layer, but not nonreactive reflective thermal-insulating layer on the amorphous silicon layer at channel region place.
Concrete, the antireflection heat-insulation layer of non-channel region is etched, and demoulding process is carried out to photoresist, obtain the structure as Fig. 6 (C), containing antireflection heat-insulation layer above the amorphous silicon of channel region, and not containing antireflection heat-insulation layer above the amorphous silicon of non-channel region, in the step that post laser irradiates, with or without the effect of antireflection heat-insulation layer, just can formation temperature gradient.
Step 504, carry out laser irradiation, utilize channel region and non-channel region to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the non-channel region of crystal grain and laterally grow up to the Artificial Control of channel region is super, thus be large scale polysilicon by the amorphous silicon of channel region.
Concrete, quasi-molecule laser annealing mode is adopted to carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be large scale polysilicon by the amorphous silicon of channel region.Swash light-struck schematic diagram as Fig. 3, the schematic diagram of grain growth, as Fig. 4, does not repeat them here.
Above-mentioned thin-film transistor low-temperature polysilicon film preparation method, be applied to the thin-film transistor of top gate structure, layer deposited isolating successively on the glass substrate, amorphous silicon layer and antireflection heat-insulation layer, and photoresist is applied on antireflection heat-insulation layer, expose, and then the antireflection heat-insulation layer of non-channel region to be etched and to the process of photoresist demoulding, thus on formation channel region containing antireflection heat-insulation layer but not channel region not containing antireflection heat-insulation layer, so in the step that post laser irradiates, can formation temperature gradient, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, control the grain size of polysilicon membrane at TFT channel region, make this region only containing a crystal boundary, thus raising carrier mobility, and make the device performance at raceway groove place even.
The above embodiment only have expressed several execution mode of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection range of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a thin-film transistor low-temperature polysilicon film preparation method, is applied in the thin-film transistor of the structure of falling grid, it is characterized in that, described method comprises:
Layer deposited isolating, amorphous silicon layer and antireflection heat-insulation layer successively on the glass substrate being coated with TFT metal gates in advance;
Utilize patterning processes to apply photoresist on antireflection heat-insulation layer, and utilize TFT metal gates carry out mask exposure and develop;
The antireflection heat-insulation layer of non-channel region is etched, and demoulding process is carried out to photoresist, to make that the amorphous silicon layer at channel region place has antireflection heat-insulation layer, but not nonreactive reflective thermal-insulating layer on the amorphous silicon layer at channel region place;
Carry out laser irradiation, utilize channel region and non-channel region to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the non-channel region of crystal grain and laterally grow up to the Artificial Control of channel region is super, thus be large scale polysilicon by the amorphous silicon of channel region.
2. method according to claim 1, is characterized in that, described separator, described antireflection heat-insulation layer comprise the combination of silica membrane or silicon nitride film or two kinds of films;
The thickness of described antireflection heat-insulation layer is the odd-multiple of 1/4 wavelength of described laser;
Described antireflection heat-insulation layer extends the super cooling time of amorphous silicon crystallization, plays insulation effect.
3. method according to claim 1, is characterized in that, described separator, described amorphous silicon layer and described antireflection heat-insulation layer adopt PECVD method to prepare;
If described antireflection heat-insulation layer is silica membrane, the preparation method of described silica membrane also to comprise in ozone solution ablution, oxygen atmosphere heating in laser irradiation and oxygen atmosphere.
4. method according to claim 1, is characterized in that, the described patterning processes that utilizes applies photoresist on antireflection heat-insulation layer, and utilize TFT metal gates carry out mask exposure and development step comprise:
Utilize patterning processes to apply positive photoresist on antireflection heat-insulation layer, and carry out ultraviolet exposure and develop.
5. method according to claim 1, it is characterized in that, describedly carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be the step of large scale polysilicon by the amorphous silicon of channel region, comprising:
Quasi-molecule laser annealing mode is adopted to carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be large scale polysilicon by the amorphous silicon of channel region.
6. a thin-film transistor low-temperature polysilicon film preparation method, is applied in the thin-film transistor of top gate structure, it is characterized in that, described method comprises:
Layer deposited isolating, amorphous silicon layer and antireflection heat-insulation layer successively on the glass substrate;
Utilize patterning processes to apply photoresist on antireflection heat-insulation layer, and utilize TFT gate mask plate carry out mask exposure and develop;
The antireflection heat-insulation layer of non-channel region is etched, and demoulding process is carried out to photoresist, to make that the amorphous silicon layer at channel region place has antireflection heat-insulation layer, but not nonreactive reflective thermal-insulating layer on the amorphous silicon layer at channel region place;
Carry out laser irradiation, utilize channel region and non-channel region to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the non-channel region of crystal grain and laterally grow up to the Artificial Control of channel region is super, thus be large scale polysilicon by the amorphous silicon of channel region.
7. method according to claim 6, is characterized in that, described separator, described antireflection heat-insulation layer comprise the combination of silica membrane or silicon nitride film or two kinds of films;
The thickness of described antireflection heat-insulation layer is the odd-multiple of 1/4 wavelength of described laser;
Described antireflection heat-insulation layer extends the super cooling time of amorphous silicon crystallization, plays insulation effect.
8. method according to claim 6, is characterized in that, described separator, described amorphous silicon layer and described antireflection heat-insulation layer adopt PECVD method to prepare;
If described antireflection heat-insulation layer is silica membrane, the preparation method of described silica membrane also to comprise in ozone solution ablution, oxygen atmosphere heating in laser irradiation and oxygen atmosphere.
9. method according to claim 6, is characterized in that, the described patterning processes that utilizes applies photoresist on antireflection heat-insulation layer, and utilize TFT gate mask plate carry out mask exposure and development step comprise:
If exposure area is channel region, then apply negative photoresist, and carry out ultraviolet exposure and develop;
If exposure area is non-channel region, then apply positive photoresist, and carry out ultraviolet exposure and develop.
10. method according to claim 6, it is characterized in that, describedly carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be the step of large scale polysilicon by the amorphous silicon of channel region, comprising:
Quasi-molecule laser annealing mode is adopted to carry out laser irradiation, channel region and non-channel region is utilized to build temperature gradient with or without the difference of antireflection heat-insulation layer, realize the Artificial Control super laterally growth of the non-channel region of crystal grain to channel region, thus be large scale polysilicon by the amorphous silicon of channel region.
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