CN103762173A - Method for preparing polysilicon thin film - Google Patents

Method for preparing polysilicon thin film Download PDF

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CN103762173A
CN103762173A CN201110461864.XA CN201110461864A CN103762173A CN 103762173 A CN103762173 A CN 103762173A CN 201110461864 A CN201110461864 A CN 201110461864A CN 103762173 A CN103762173 A CN 103762173A
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preparation
nickel
thin film
polysilicon
amorphous
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赵淑云
郭海成
王文
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GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
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GUANGDONG ZHONGXIAN TECHNOLOGY Co Ltd
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Abstract

The invention provides a method for preparing a polysilicon thin film with a bridged-grain structure. The method includes the following steps that: 1) a polysilicon thin film is deposited on a glass substrate through using plasma enhanced chemical vapor deposition; 2) an amorphous Si thin film is deposited through using a low-pressure chemical vapor deposition method; 3) after an autoxidation layer is removed, a 100 nm-thick oxide layer is formed on the surface of the amorphous Si thin film through oxidation; 4) 8 micron-wide 100 micron-interval grooves which are adopted as inducing lines are formed in the oxide layer; 5) a sustained-release nickel/silicon oxidation source layer is sputtered on a SiO2 nano oxide layer, such that metal induced crystallization can be performed; 6) heating is performed under N2 atmosphere until amorphous Si is completely crystallized; 7) residual nickel on a surface is removed; and 8) parallel conductive strips or conductive wires can be formed in a polysilicon thin film obtained in the step 7) through doping, wherein the conductive strips or conductive wires are connected with multiple grains.

Description

A kind of method of preparing polysilicon membrane
Technical field
The present invention relates to polysilicon technology, relate more specifically to a kind of grained polysilicon thin film technique.
Background technology
In traditional Active Matrix LCD At field, TFT normally uses amorphous silicon (a-Si) material to make.This is mainly because its reduction process temperature and low manufacturing cost on large-area glass base plate.Polysilicon is for high-resolution liquid crystal display (LCD) and active organic electroluminescent display (AMOLED) recently.Polysilicon also has the advantage of integrated circuit on glass substrate.In addition, polysilicon has the possibility of larger pixel aperture ratio, has improved optical energy utilization efficiency and has reduced LC and the power consumption of bottom-emission OLED display.As everyone knows, multi-crystal TFT is more suitable for for driving OLED pixel, not only because OLED is current-driven apparatus, a-Si TFT has the long-term reliability problems of driving OLED, and be because amorphous silicon electron mobility is less, the ratio that needs large W/L, to provide enough OLED pixel driving currents.Therefore,, for High Resolution Display, high-quality multi-crystal TFT is absolutely necessary.
In order to realize the suitability for industrialized production of active matrix TFT display panel, need the quality of very much higher polycrystal silicon film.It need to meet K cryogenic treatment on large-area glass substrate, manufactures cheaply stable manufacturing process, high-performance, the high uniformity of device performance and high reliability.
High temperature polysilicon technology can be used for realizing high performance TFT, but it can not be used in the common glass substrates of using in business panel.In this case, must use low temperature polycrystalline silicon (LTPS).There are three main LTPS technology: (1) anneal solid-phase crystallization (SPC) of a very long time at 600 ℃; (2) excimer laser crystallization, annealing (ELC/ELA) or flash annealing; (3) crystallization inducing metal (MIC).ELC can produce optimum efficiency, but is limited to high equipment investment and maintenance cost, and the size of glass substrate is also difficult to further increase.SPC is the most cheap technology, but the just crystallization about 24 hours of need to annealing at 600 ℃.The shortcoming of MIC is the heterogeneity of metallic pollution and TFT device.Thereby, also without any a kind of technology, can meet all above-mentioned low costs and high performance requirement.
The common ground of all polycrystalline silicon film materials is that the size and shape of the crystallization direction of the crystal grain on film is random distribution in itself.When this polysilicon membrane is used as the active layer of TFT, the electrology characteristic of TFT is limited to the crystal boundary occurring in raceway groove.The distribution of crystal grain is random, makes the electrology characteristic of TFT of whole substrate inhomogeneous.This electrology characteristic discrete problem that distributes, makes final showing as the defect of mura and brightness heterogeneous just.
Summary of the invention
For overcoming above-mentioned defect, the application proposes a kind of new method and improves above TFT characteristic, comprises ELA, SPC and MIC technology.By doped polycrystalline silicon line, the polysilicon of intrinsic is by the parallel lines that adulterate, and is referred to as bridged-grain structures (BG) and connects.
The invention provides a kind of method of preparing the polysilicon membrane with bridged-grain structures, comprising:
1), on glass substrate, use plasma enhanced chemical vapor deposition cvd silicon oxide film;
2) with low-pressure chemical vapor deposition method deposited amorphous Si film;
3) remove after natural oxidizing layer, by oxidation, make amorphous Si film surface form the oxide skin(coating) of one deck 100 nanometer thickness;
4) in oxide skin(coating), forming width is that 8 microns of grooves that are spaced apart 100 μ m are as induction line;
5) at SiO 2on nano-oxide layer, sputter one deck slowly-releasing nickel/silicon oxidation source layer, carries out crystallization inducing metal;
6) at N 2under atmosphere, heat, to non-through the complete crystallization of Si;
7) remove the upper residual nickel in surface;
8) in step 7) in the polysilicon membrane that obtains, by doping, form parallel conductive strips or conductor wire, described conductive strips or conductor wire connect a plurality of crystal grain.
According to preparation method provided by the invention, wherein step 2) in, with low-pressure chemical vapor deposition method, under 550 ℃ of environment, deposit the amorphous Si film of 45 nanometers.
According to preparation method provided by the invention, wherein step 8) in, doped with boron or phosphorus.
According to preparation method provided by the invention, wherein step 4) in, adopt nickel silicon alloy as target, by sputter, form slowly-releasing nickel/silicon oxidation source layer.
According to preparation method provided by the invention, wherein, in nickel silicon alloy target, nisiloy ratio is: Ni: Si=1: 9.
According to preparation method provided by the invention, wherein sputter is to carry out in argon gas and the oxygen ratio hybird environment of 200: 1.
According to preparation method provided by the invention, wherein sputter DC power supply is 7W, and sputtering time is 6 minutes.
According to preparation method provided by the invention, wherein step 6) in heating-up temperature be 590 degrees Celsius.
According to preparation method provided by the invention, wherein step 8) comprising: on polysilicon membrane, form mask; Implantation forms conductive strips or the conductor wire adulterating in polysilicon membrane.
Use this BG polysilicon layer as active layer, assurance electric current vertical current is crossed parallel lines TFT design, and the impact of crystal boundary can reduce.Threshold voltage, switch ratio, device mobility, the uniformity of whole substrate, these important characteristics of the reliability of sub-threshold slope and device can be used present this technology to be improved.These improve, simultaneously also can be so that cost be lower, and price is more cheap, and high performance LTPS TFT is become a reality.
Accompanying drawing explanation
Referring to accompanying drawing, embodiments of the present invention is further illustrated, wherein:
Fig. 1 a and Fig. 1 b are respectively the schematic diagram of low-temperature polysilicon film and corresponding barrier Distribution;
Fig. 2 a and Fig. 2 b are respectively the schematic diagram of bridged-grain polysilicon membrane and corresponding barrier Distribution;
Fig. 3 is for forming the cross sectional representation of BG line structure;
Fig. 4 is for take the SEM picture that cycle that PR1075 forms is the BG line pattern of 1 μ m;
Fig. 5 is that Selwyn Lloyd is interfered schematic diagram;
Fig. 6 is for being used LIL to form the cross sectional representation of BG line;
The SEM picture that Fig. 7 is the positive photoresist film realized by LIL system;
The SEM picture that Fig. 8 is the negative film realized by LIL system;
Fig. 9 is NIL process schematic diagram, and Fig. 9 a is press mold, and Fig. 9 b is the demoulding;
Figure 10 a, 10b and 10c are respectively the cross sectional representation of sample A, sample B and sample C crystallization;
Figure 11 is that all samples forms the cross sectional representation after BG line by photoresist and Implantation;
Figure 12 a, 12b and 12c are the microphoto of TMAH etching macromeritic polysilicon, little grained polysilicon and SR-MILC polysilicon.
Embodiment
Generally, polysilicon is comprised of two parts, and a kind of is single grained region, and another kind is crystal boundary.Conductive characteristic in crystal grain is almost identical, and poor across the conduction of crystal boundary, this can cause the loss of whole mobility and the increase of threshold voltage.The active channel of the thin-film transistor of polysilicon membrane (TFT) is comprised of such polysilicon membrane conventionally.Conductive characteristic random and that change is unfavorable for display performance and image quality.As shown in Figure 1a, low-temperature polysilicon film comprises the border of crystal grain and crystal grain to typical polysilicon structure figure.Adjacent intergranule has obvious crystal boundary.Generally, the length of crystal grain is in tens nanometers, between several microns of sizes, is considered to a single crystal.Grain boundaries is distributed with a lot of dislocation conventionally, storehouse fault and hanging key defect.Due to different preparation methods, the crystal grain in low-temperature polysilicon film may be random distribution or be directional distribution.
At crystal boundary, there is major defect, will cause high potential barrier, as shown at Fig. 1 b.The carrier transport of potential barrier (or vertical component of oblique potential barrier) vertical direction can have influence on initial condition and current capacity.Thin-film transistor threshold voltage prepared by this low-temperature polysilicon film, field-effect mobility is all limited to crystal boundary potential barrier.When the grain boundary of playing link effect is applied to TFT, also can, under high reverse grid voltage, cause larger leakage current.
The polysilicon technology of bridged-grain (BG) is the active layer at TFT, by using parallel electrically conductive band or line to connect the technology of crystal grain.Form the crossover track of the crystal grain that the electric current of conductive strips or vertical direction flows through, can greatly improve the performance of TFT.These crossover tracks can reduce the impact of crystal grain boundary, as shown at Fig. 2 (b).This structure is defined as the structure of bridged-grain (BG).
Described " bridging " is comprised of parallel highly doped lines, and we are referred to as BG line.The BG line forming on polysilicon membrane should be narrow, very close to each other.The width of this line and spacing should be similar with the size of crystal grain.Conductor wire should not contact with each other, and should contain whole polysilicon membrane so that with reprocessing.The major function of BG line is to build bridge perpendicular to the flow direction of electric current at intergranule.Therefore, electric current is mobile along these circuits is no longer a major issue.
The polysilicon membrane schematic diagram of the bridged-grain structures of Fig. 2 a shown in being.Conductor wire is perpendicular to the flow direction of electric current.These conductor wires can form with p or N-shaped doped semiconductor doping ion.Doping can be adjusted, to create conductive channel, conventionally 10 12/ cm 2to 10 16/ cm 2scope.The pattern of doping can be undertaken by various methods, as simple photoetching, and laser interference, or nano imprint lithography etc.
Embodiment 1
The present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1) at polysilicon membrane surface spin coating one deck PR 1075 photoresists, after the spin coating of PR photoresist, sample is heated to 90 degree and carries out soft roasting, be 1 minute heating time, soft roasting object is in order to reduce the solvent of photoresist, from～20% to～5%, discharge the stress of induction spin-coated thin film simultaneously, after soft baking, use ASM PAS5000 step photo-etching machine photoresist to be exposed under for 365nm light at wavelength, after 110 ℃ of barbecues 1 minute, then sample is dipped into FHD-530 and carries out development treatment second, the photoresist being emerging under light is dissolved in lysate, the part that does not touch light is to keep intact, thereby make BG line graph transfer to (as shown in Figure 3) on photoresist, the formation cycle is the BG line pattern (its SEM photo as shown in Figure 4) of 1 μ m,
2) 120 ℃ hard roasting after, sample is sent to and in CF3000, carries out Implantation.
The step photo-etching machine of ASML 5000 types of NFF (The Nanoelectronics Fabrication Facility nanoelectronic manufacturing works), ratio is 5 to 1, this has guaranteed that minimum feature and minimum interval are 0.5 μ m.Therefore, minimum line cycle limit is at 1 μ m.
The present embodiment generates BG pattern and two steps of Implantation by photoetching, has obtained the BG line being comprised of the doped polycrystalline silicon parallel lines that the single repetition period is 1 μ m.
In other embodiments, again recrystallized amorphous silicon is become to polysilicon after also can first forming BG line on amorphous silicon, BG line can be formed on before or after crystallization.
This elder generation adulterates and forms the method for BG line recrystallization on amorphous silicon, and recrystallized amorphous silicon, then the method that forms BG line on polysilicon compares, and at least has the following advantages: when carry out the doping of P type on amorphous silicon, more can promote the crystallization of amorphous silicon during annealing with first; Because dopant can spread when the recrystallized amorphous silicon, utilize this point, the ratio of Yu Fei doped region, controlled doping district better, dwindles the probability of the crystal boundary that is present in non-doped region further, reduces the risk of short circuit simultaneously; Have again, because annealing process is after doping, in recrystallized amorphous silicon also electrode dopant activation.
Embodiment 2
BG line pattern also can be realized with laser interference photolithography technology (LIL), and this is easily at large-area substrates, to realize, and does not need a mask plate.Laser interference photolithography technology (LIL) is manufacturing cycle property and prefered method quasi periodicity pattern on a larger region substrate.
The device that the Selwyn Lloyd of use based on as shown in Figure 5 interfered.Regular pattern is to consist of coherence laser beam and reflection lasering beam.Because the second bundle laser beam is to be formed by the mirror that simultaneously approaches very much substrate, such setting two-beam interference setting real with compared, and it is not too responsive to vibration.The cycle of interference figure, and the resist layer grating record on substrate are to be determined by formula P=λ/(2sin θ).The light source that uses 363.8nm, in the cycle of 300 nanometer to 1000 nanometers, can be easy to recall.
The present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1) anti-reflection coating (ARC) of spin coating one deck 280nm firmly roasting at 175 ℃ on polysilicon membrane, then spin coating on ARC layer
Figure BSA00000653991200061
thick PR 1075 photoresists, are put into 90 degree environment heating 1mins sample, then photoresist are placed in LIL system and are exposed, and as for PR1075 photoresist, select
Figure BSA00000653991200062
luminous energy, after exposure, 110 ℃ of barbecues 1 minute, then sample was dipped into FHD-530 and carries out development treatment second, thereby BG line graph is transferred on photoresist, and its cross section structure schematic diagram is as shown in Figure 6;
2) after 120 ℃ of hard baking, sample is sent to CF3000 ion implant systems and carries out BG Implantation, and after BG Implantation, PR glue is deprived removal at oxygen plasma temperature 30min under 100 ℃ of environment.
The polysilicon membrane that the present embodiment obtains can be called as BG-poly-Si, can be used as TFT active layer and uses.
Fig. 7 is for being used the SEM photo of the positive glue of LIL system.Be noted that use positive photoresist forms the common PR line of grating pattern narrower than groove, as shown in Figure 7.In this case, Implantation and activate after, owing to injecting the phenomenon that laterally spreads and in the reasons such as diffusion of activation, contiguous BG line is too easily short-circuited.
Address this problem, after LIL system exposure, can be under ammonia environment 90 ℃ of heating 30 minutes.Then sample is pushed into and is exposed to 200mJ/cm 2the UV luminous environment of the energy.Finally, after treatment, positive glue becomes negative glue, after development, as shown in Figure 8, can make the BG distance between centers of tracks of follow-up formation increase, and prevents owing to injecting the phenomenon laterally spreading and the BG line short circuit that makes vicinity in the reasons such as diffusion of activation.
The present embodiment generates BG pattern and two steps of Implantation by laser interference photolithography technology (LIL), has obtained the BG line being comprised of the doped polycrystalline silicon parallel lines that the repetition period is 300 nanometer to 1000 nanometers.
In other embodiments, again recrystallized amorphous silicon is become to polysilicon after also can first forming BG line on amorphous silicon, BG line can form before or after crystallization.
Embodiment 3
The another kind of mode that can realize undersized BG line pattern is nano-imprint lithography (NIL) technology.NIL is a simple photoetching process, has cost low, high volume production and high-resolution.It is to form patterning by the mechanical deformation of the marking on resist and subsequent handling.The marking of resist is normally formed in heat or ultraviolet light polymerization process through being printed on by a monomer or polymer formulations.
The principle of NIL as shown in Figure 9, will have the hard mold on the undulations surface of nanoscale to be pressed into polymeric material on substrate, thereby on polymeric material, forms the thickness contrast that height rises and falls.The eluvium of very thin polymeric material has a mind to stay under mold tabs part, as soft resilient coating, to prevent that hard mold from directly having influence on substrate, also effectively protects undulations surface and the equipment surface of the nanoscale of die surface exquisiteness simultaneously.After processing through NIL, make BG shape design transfer to substrate, and then carry out BG Implantation.
Embodiment 4
The present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1), on Eagel2000 glass substrate, use the silica (SiO of plasma enhanced chemical vapor deposition (PEVCD) deposition 300nm 2).Then use low-pressure chemical vapor deposition (LPCVD) method under 550 ℃ of environment, to deposit the a-Si of 45 nanometers;
2) at 1% hydrofluoric acid, hold that liquid (HF) is inner floods 1 minute after the natural oxidizing layer of removing, put temperature into and be the oxidation environment 15 minutes of 550 degree, make a-Si surface form one deck SiO 2nano-oxide layer;
3) in this nanometer layer, sputter one deck slowly-releasing (SR) nickel/silicon oxidation source layer carries out crystallization inducing metal, adopt nickel silicon alloy as target, nisiloy ratio is: Ni: Si=1: 9, sputter is to carry out in argon gas and the oxygen ratio hybird environment of 200: 1, sputter DC power supply is 7W, and sputtering time is 90 seconds;
4) under 590 degree N2 atmosphere, heat 6 hours, till the complete crystallization of a-Si, the schematic cross-section that Figure 10 a is this crystallization protocol;
5) soak 120 ℃ of mixed solution H 2sO 4+ H 2o 2in 10 minutes, to remove the upper residual nickel in surface.Then be put into 1% etching acid (HF) and soak 1 minute, to remove nano coating, then deposit the LTO of 100nm;
6) use the ASM PAS5000 step photo-etching machine that the wavelength described in embodiment 1 is 365nm to form BG pattern, the BG line cycle is 1 micron.
7) at 120 ℃, toast after 30 minutes, for all P channel TFT, at energy and the 2E15/cm of 40KeV 2under dosage, using boron to adulterate for BG, for all N-type TFT, is BG doping with phosphorus, and the BG doping is here to be undertaken by two steps, at the dosage of each step, is 1E15/cm 2, Implantation Energy is respectively 80KeV and 130KeV, obtains structure as shown in figure 11;
8) use oxygen plasma at 100 degrees Celsius of lower 30 minutes stripping photoresists, after removing PR photoresist, the LTO of 100nm is also used 777 wet etching removal.After this step of BG completes, whole part doped polycrystalline silicon film can be called BG-poly-Si, can be used for TFT active layer.
Utilize slowly-releasing nickel/silicon oxidation source layer to carry out in the process of crystallization inducing metal, slowly-releasing nickel/silicon oxidation source is a supplementary source as nickel in a relatively slow speed.The nickel of this Ni source slowly provides in silicon and the reaction of nisiloy oxide, and this provides a large amount of pure nickel atoms to be very different with pure nickel source.Therefore, the nickel amount that nickel oxide provides is less than pure nickel source, and this slow release reaction nickel can reduce the content of residual nickel in polysilicon.
The internal structure of the film that the step 4 of the method providing in the present embodiment) resulting polysilicon membrane is shown after room temperature etching by Tetramethylammonium hydroxide (TMAH) etching solution is as shown in Figure 12 a, the polysilicon that the present embodiment obtains is large-scale grained polysilicon, has high mobility, low cost and stress relief annealed feature.
Embodiment 5
The present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1), on Eagel2000 glass substrate, use the silica (SiO of plasma enhanced chemical vapor deposition (PEVCD) deposition 300nm 2).Then use low-pressure chemical vapor deposition (LPCVD) method under 550 ℃ of environment, to deposit the a-Si of 45 nanometers;
2) 1% inner dipping of hydrofluoric acid appearance liquid (HF), within 1 minute, arrive after the natural oxidizing layer of removing, immersing temperature is the H of 120 degree 2sO 4+ H 2o 2mixed solution 10 minutes, makes a-Si surface form one deck SiO 2nanometer layer;
3) in this nanometer layer, sputter one deck slowly-releasing (SR) nickel/silicon oxidation source layer carries out crystallization inducing metal, adopt nickel silicon alloy as target, nisiloy ratio is: Ni: Si=1: 9, sputter is to carry out in argon gas and the oxygen ratio hybird environment of 200: 1, sputter DC power supply is 7W, and sputtering time is 2 minutes;
4) under 590 degree N2 atmosphere, heat 6 hours, till the complete crystallization of a-Si, the schematic cross-section that Figure 10 b is this crystallization protocol;
5) soak 120 ℃ of mixed solution H 2sO 4+ H 2o 2in 10 minutes, to remove the upper residual nickel in surface.Then be put into 1% etching acid (HF) and soak 1 minute, to remove nano coating, then deposit the LTO (low temperature oxide) of 100nm;
6) use the ASM PAS5000 step photo-etching machine that the wavelength described in embodiment 1 is 365nm to form BG pattern, the BG line cycle is 1 micron;
7) at 120 ℃, toast after 30 minutes, for all P channel TFT, under the energy of 40KeV and 2E15/cm2 dosage, use boron to adulterate for BG, for all N-type TFT, with phosphorus, be BG doping, the BG doping is here to be undertaken by two steps, at the dosage of each step, is 1E15/cm2, Implantation Energy is respectively 80KeV and 130KeV, obtains structure as shown in figure 11;
8) use oxygen plasma 30 minutes stripping photoresists at 100 ℃ of temperature, after removing PR photoresist, the LTO of 100nm is also used 777 wet etching removal.After this step of BG completes, whole part doped polycrystalline silicon film can be called BG-poly-Si, can be used for TFT active layer.
The internal structure of the film that the step 4 of the method providing in the present embodiment) resulting polysilicon membrane is shown after room temperature etching by Tetramethylammonium hydroxide (TMAH) etching solution is as shown in Figure 12 b, the polysilicon that the present embodiment obtains is the polysilicon membrane of little crystal grain (flocculent structure), there are less mobility and higher nickel residual quantity, yet this technology has good uniformity, cost is low, annealing time is short, the wider advantages such as PROCESS FOR TREATMENT window.
Embodiment 6
The present embodiment provides a kind of formation to have the method for the polysilicon membrane of bridged-grain (BG) line, comprising:
1), on Eagel2000 glass substrate, use the silica (SiO of plasma enhanced chemical vapor deposition (PEVCD) deposition 300nm 2).Then use low-pressure chemical vapor deposition (LPCVD) method under 550 ℃ of environment, to deposit the a-Si of 45 nanometers;
2) 1% inner dipping of hydrofluoric acid appearance liquid (HF), within 1 minute, arrive after the natural oxidizing layer of removing the low temperature oxide (LTO) of deposition one deck 100 nanometer thickness;
3) by chemical etching technique, on LTO layer, form width and be 8 microns of grooves that are spaced apart 100 μ m as induction line (IL), as shown in Figure 10 C, be dipped into the H of 120 degree 2sO 4+ H 2o 2in mixed solution 10 minutes to remove photoresist, sputter one deck slowly-releasing (SR) nickel/silicon oxidation source layer carries out crystallization inducing metal, adopt nickel silicon alloy as target, nisiloy ratio is: Ni: Si=1: 9, sputter is to carry out in argon gas and the oxygen ratio hybird environment of 200: 1, sputter DC power supply is 7W, and sputtering time is 6 minutes;
4) at 590 ℃, N 2crystallization, the schematic cross-section that Figure 10 c is this crystallization protocol are carried out in atmosphere heating for 2 hours;
5) be immersed to the H of 120 degree 2sO 4+ H 2o 2mixed solution 10 minutes, to remove the upper residual nickel in surface;
6) use the ASM PAS5000 step photo-etching machine that the wavelength described in embodiment 1 is 365nm to form BG pattern, the BG line cycle is 1 micron;
7) at 120 ℃, toast after 30 minutes, for all P channel TFT, under the energy of 40KeV and 2E15/cm2 dosage, use boron to adulterate for BG, for all N-type TFT, with phosphorus, be BG doping, the BG doping is here to be undertaken by two steps, at the dosage of each step, is 1E15/cm2, Implantation Energy is respectively 80KeV and 130KeV, obtains structure as shown in figure 11;
8) use oxygen plasma 30 minutes stripping photoresists at 100 ℃ of temperature, after removing PR photoresist, the LTO of 100nm is also used 777 wet etching removal.After this step of BG completes, whole part doped polycrystalline silicon film can be called BG-poly-Si, can be used for TFT active layer.
The internal structure of the film that the step 4 of the method providing in the present embodiment) resulting polysilicon membrane is shown after room temperature etching by Tetramethylammonium hydroxide (TMAH) etching solution is as shown in Figure 12 c, the polysilicon that the present embodiment obtains is slowly-releasing nickel induction transverse crystallizing (SR-MILC) polysilicon membrane, a process window is widely provided, can have prevented the impact of batch processing on the changes in process parameters between polycrystalline SiTFT.

Claims (9)

1. a method of preparing the polysilicon membrane with bridged-grain structures, comprising:
1), on glass substrate, use plasma enhanced chemical vapor deposition cvd silicon oxide film;
2) with low-pressure chemical vapor deposition method deposited amorphous Si film;
3) remove after natural oxidizing layer, by oxidation, make amorphous Si film surface form the oxide skin(coating) of one deck 100 nanometer thickness;
4) in oxide skin(coating), forming width is that 8 microns of grooves that are spaced apart 100 μ m are as induction line;
5) at SiO 2on nano-oxide layer, sputter one deck slowly-releasing nickel/silicon oxidation source layer, carries out crystallization inducing metal;
6) at N 2under atmosphere, heat, to non-through the complete crystallization of Si;
7) remove the upper residual nickel in surface;
8) in step 7) in the polysilicon membrane that obtains, by doping, form parallel conductive strips or conductor wire, described conductive strips or conductor wire connect a plurality of crystal grain.
2. preparation method according to claim 1, wherein step 2) in, with low-pressure chemical vapor deposition method, under 550 ℃ of environment, deposit the amorphous Si film of 45 nanometers.
3. preparation method according to claim 1, wherein step 8) in, doped with boron or phosphorus.
4. preparation method according to claim 1, wherein step 4) in, adopt nickel silicon alloy as target, by sputter, form slowly-releasing nickel/silicon oxidation source layer.
5. preparation method according to claim 4, wherein, in nickel silicon alloy target, nisiloy ratio is: Ni: Si=1: 9.
6. preparation method according to claim 4, wherein sputter is to carry out in argon gas and the oxygen ratio hybird environment of 200: 1.
7. preparation method according to claim 4, wherein sputter DC power supply is 7W, sputtering time is 6 minutes.
8. preparation method according to claim 1, wherein step 6) in heating-up temperature be 590 degrees Celsius.
9. preparation method according to claim 1, wherein step 8) comprising: on polysilicon membrane, form mask; Implantation forms conductive strips or the conductor wire adulterating in polysilicon membrane.
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Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103151388B (en) * 2013-03-05 2015-11-11 京东方科技集团股份有限公司 A kind of polycrystalline SiTFT and preparation method thereof, array base palte
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US9793361B2 (en) 2014-09-10 2017-10-17 Boe Technology Group Co., Ltd. Thin film transistor, array substrate and display device
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CN106033707A (en) * 2015-03-10 2016-10-19 上海和辉光电有限公司 Preparation method for polysilicon film
CN105575974B (en) * 2015-12-14 2018-08-14 深圳市华星光电技术有限公司 The production method of low temperature polycrystalline silicon TFT backplate
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CN106328506B (en) * 2016-08-31 2020-04-10 上海华力微电子有限公司 Method for reducing photoresist stripping risk of ion implantation layer
CN106601873B (en) * 2016-12-16 2018-06-29 苏州腾晖光伏技术有限公司 A kind of spin coating device for CZTS films and the method for preparing CZTS batteries
RU2747443C2 (en) * 2017-01-04 2021-05-05 Ших-Сиэнь ТСЭН Pixel block structure and its manufacturing method
CN106876479B (en) * 2017-04-19 2020-03-06 京东方科技集团股份有限公司 Thin film transistor and preparation method thereof, array substrate and preparation method thereof, and display panel
CN109742028B (en) * 2018-12-25 2021-04-02 惠科股份有限公司 Manufacturing method of thin film transistor, thin film transistor and display panel
DE102019100312A1 (en) * 2019-01-08 2020-07-09 Parcan NanoTech Co. Ltd. Controlled ion implantation substrate and method of making a controlled ion implantation substrate
CN112736087B (en) * 2019-10-10 2024-03-05 京东方科技集团股份有限公司 Manufacturing method of array substrate, array substrate and display panel
CN110660869A (en) * 2019-10-27 2020-01-07 南京飞芯电子科技有限公司 Method for forming enhancement mode field effect transistor
CN112563197B (en) * 2020-11-24 2022-03-22 惠科股份有限公司 Active switch, manufacturing method thereof and display panel

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903372B1 (en) * 1999-10-29 2005-06-07 Hitachi, Ltd. Semiconductor device, method of making the same and liquid crystal display device
CN101681930A (en) * 2007-06-22 2010-03-24 香港科技大学 Polycrystalline silicon thin film transistors with bridged-grain structures
CN101814438A (en) * 2010-05-17 2010-08-25 广东中显科技有限公司 Preparation method of thin film transistor based on induced longitudinal crystallization polycrystalline silicon
CN101834211A (en) * 2010-02-09 2010-09-15 广东中显科技有限公司 Polycrystalline silicon thin film based on metal induction

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5783047A (en) * 1980-11-10 1982-05-24 Matsushita Electric Ind Co Ltd Polycrystalline semiconductor resistor
TW520072U (en) * 1991-07-08 2003-02-01 Samsung Electronics Co Ltd A semiconductor device having a multi-layer metal contact
JPH06104438A (en) * 1992-09-22 1994-04-15 Casio Comput Co Ltd Film transistor
JPH08139335A (en) * 1994-11-14 1996-05-31 Casio Comput Co Ltd Method of manufacturing thin film transistor
US6108058A (en) * 1997-04-30 2000-08-22 Tohoku Techno-Brains Corporation Field sequential Pi cell LCD with compensator
JPH11354800A (en) * 1998-06-04 1999-12-24 Hitachi Ltd Thin-film transistor, its forming method, and liquid crystal display device
JP4436469B2 (en) * 1998-09-30 2010-03-24 三洋電機株式会社 Semiconductor device
JP2000133807A (en) * 1998-10-22 2000-05-12 Seiko Epson Corp Polycrystalline silicon thin-film transistor
JP2000208771A (en) * 1999-01-11 2000-07-28 Hitachi Ltd Semiconductor device, liquid cystal display device, and their manufacturing
JP3873811B2 (en) * 2002-05-15 2007-01-31 日本電気株式会社 Manufacturing method of semiconductor device
KR100930362B1 (en) * 2002-11-04 2009-12-08 엘지디스플레이 주식회사 Polycrystalline Silicon Film Formation Method And Manufacturing Method Of Thin Film Transistor Including The Same
KR100577795B1 (en) * 2003-12-30 2006-05-11 비오이 하이디스 테크놀로지 주식회사 Method for forming polycrystalline silicon film
TWI266427B (en) * 2004-06-01 2006-11-11 Yamanashi Tlo Co Ltd Field-effect transistor and method of manufacturing same
TWI241027B (en) * 2004-09-30 2005-10-01 Ind Tech Res Inst Method of preparing electronic device
US8088676B2 (en) * 2005-04-28 2012-01-03 The Hong Kong University Of Science And Technology Metal-induced crystallization of amorphous silicon, polycrystalline silicon thin films produced thereby and thin film transistors produced therefrom
US8013957B2 (en) * 2005-05-21 2011-09-06 The Hong Kong University Of Science And Technology Transflective liquid crystal device and method of manufacturing the same
US7790580B2 (en) * 2006-03-13 2010-09-07 Hong Kong University Of Science And Technology Metal-induced crystallization of amorphous silicon in thin film transistors
JP5295529B2 (en) * 2007-08-13 2013-09-18 株式会社ジャパンディスプレイ Semiconductor device
CN101834138A (en) * 2010-02-09 2010-09-15 广东中显科技有限公司 Method for preparing transistor device of crystallized thin film
CN101853784B (en) * 2010-05-17 2012-07-04 广东中显科技有限公司 Method for transversely inducing and crystallizing low-temperature polycrystalline silicon film
CN101819999A (en) * 2010-05-17 2010-09-01 广东中显科技有限公司 Multilayer film structure for transverse induced crystallization of low-temperature poly-silicon film
CN102129962A (en) * 2010-10-28 2011-07-20 广东中显科技有限公司 Controllable method for manufacturing polysilicon thin film through metal induction
CN102082098A (en) * 2010-12-15 2011-06-01 四川虹视显示技术有限公司 Method for producing low-temperature polysilicon thin-film transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6903372B1 (en) * 1999-10-29 2005-06-07 Hitachi, Ltd. Semiconductor device, method of making the same and liquid crystal display device
CN101681930A (en) * 2007-06-22 2010-03-24 香港科技大学 Polycrystalline silicon thin film transistors with bridged-grain structures
CN101834211A (en) * 2010-02-09 2010-09-15 广东中显科技有限公司 Polycrystalline silicon thin film based on metal induction
CN101814438A (en) * 2010-05-17 2010-08-25 广东中显科技有限公司 Preparation method of thin film transistor based on induced longitudinal crystallization polycrystalline silicon

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Application publication date: 20140430