CN105304641A - Manufacturing method of low temperature polysilicon TFT array substrate - Google Patents
Manufacturing method of low temperature polysilicon TFT array substrate Download PDFInfo
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- CN105304641A CN105304641A CN201510617534.3A CN201510617534A CN105304641A CN 105304641 A CN105304641 A CN 105304641A CN 201510617534 A CN201510617534 A CN 201510617534A CN 105304641 A CN105304641 A CN 105304641A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 47
- 239000000758 substrate Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 74
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 20
- 230000008569 process Effects 0.000 claims abstract description 16
- 238000000137 annealing Methods 0.000 claims abstract description 10
- 230000004888 barrier function Effects 0.000 claims description 23
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000002161 passivation Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000004913 activation Effects 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000001816 cooling Methods 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 150000002500 ions Chemical class 0.000 description 16
- 239000010408 film Substances 0.000 description 14
- 238000001994 activation Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000010792 warming Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention provides a manufacturing method of a low temperature polysilicon TFT array substrate. The manufacturing method comprises the following steps that A. a substrate is provided, and a buffer layer and an amorphous silicon layer are deposited on the substrate in turn; B. patterning processing is performed on the amorphous silicon layer; C. ion doping is performed on the amorphous silicon layer; D. annealing processing is performed on the amorphous silicon layer so that a polysilicon layer is formed; E. a first insulating layer and a first metal film are deposited on the polysilicon layer in turn, and a grid electrode is manufactured; F. a second insulating layer is deposited on the first metal film, and then a second metal film is deposited on the second insulating layer and a source electrode and a drain electrode are formed; and G. flat layer is formed on the second insulating layer, and an electrode is formed on the flat layer. According to the manufacturing method, annealing processing is arranged after the ion doping technology so that ion activation processing is additionally completed in the process of annealing cooling to room temperature without additional arrangement of an activation step, and thus the technological process is simplified and the phenomenon of thermal shrinkage increasing of the substrate caused by secondary temperature rise can be avoided.
Description
[technical field]
The present invention relates to liquid crystal display and manufacture field, particularly relate to a kind of manufacture method of low temperature polycrystalline silicon tft array substrate.
[background technology]
At present, owing to adopting low temperature polycrystalline silicon (LowTemperaturePoly-Silicon, LTPS) thin-film transistor (ThinFilmTransistor, TFT) display floater manufactured has the advantages such as resolution is high, reaction speed fast, high brightness, high aperture, and the application of LTPS-TFT display floater is more and more extensive.
As shown in Figure 1, the manufacture of existing LTPSTFT array base palte mainly comprises the following steps:
Step S1, provides a substrate 10, deposits light shield layer 20 on the substrate 10, to reduce leakage current;
Step S2, utilize chemical phase deposition method on light shield layer 20, form resilient coating 30 (main material is silicon nitride and silica) and amorphous silicon layer 40m successively, and make amorphous silicon layer 40m crystalline transition be polysilicon layer 40n by quasi-molecule laser annealing (ELA);
Step S3, by etching processing procedure, patterned process is carried out to polysilicon layer 40n, it is made to form spaced the N raceway groove polysilicon section 401 and the P raceway groove polysilicon section (not shown) that are positioned at drive area, and define N channel region 4011 in N raceway groove polysilicon section 401 respectively, first source region 4012a and the first drain region 4012b, P channel region is defined in P raceway groove polysilicon section, second source region and the second drain region (not shown), and lay respectively at the first source region 4012a/ second source region and the shallow doped region 4013 between the first drain region 4012b/ second drain region and 4011/P channel region, N channel region,
Step S4, carries out ion doping, comprises channel doping, N-type doping and the doping of P type, carries out activation processing afterwards;
Step S5, depositing first insulator layer 50 and the first metal film (not shown) successively on polysilicon layer 40n, and on the first metal film, make grid 60 by etching processing procedure, afterwards ion doping is carried out to the shallow doped region 4013 on polysilicon layer 40n.
Step S6, grid 60 deposits the second insulating barrier 70, and form multiple through hole 701 by etching, the second metal film (not shown) is deposited afterwards on described second insulating barrier 70, second metal film makes the first source electrode 802a/ second source electrode (not shown) and first drain electrode 802b/ second drain, first source electrode 802a/ second source electrode and the first drain electrode 802b/ second are drained to be communicated with the first drain region 4012b/ second drain region with the first source region 4012a/ second source region of polysilicon section 401/P channel region, N channel region polysilicon section respectively via through hole 701,
Step S7, the second metal film deposits organic film (not shown) and the first electrode layer (not shown) successively, and forms the first electrode (not shown);
Step S8, depositing insulating layer (not shown) and the second electrode lay (not shown) successively on the first electrode layer, and form the second electrode (not shown).
In above-mentioned manufacturing process, amorphous silicon needs to be cooled to room temperature after carrying out ELA (annealing temperature can up to 1000 DEG C) and carries out follow-up ion doping technique (i.e. step 4), because the ion of doping might not form chemical bond with surrounding ions, namely there are certain dangling bonds, therefore we need be warming up to 590 DEG C and activate after doping, dangling bonds are made to form stable chemical bond, this technological process is more loaded down with trivial details, and the second time intensification needed for activation can increase the thermal contraction of substrate.
[summary of the invention]
The object of the present invention is to provide a kind of manufacture method of low temperature polycrystalline silicon tft array substrate, to solve the problem that existing tft array substrate manufacturing process is loaded down with trivial details, substrate heat shrinkage is large.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of low temperature polycrystalline silicon tft array substrate, it comprises the following steps:
A, provide a substrate, on the substrate side's buffer layer and amorphous silicon layer successively;
B, by etching patterned process is carried out to described amorphous silicon layer, amorphous silicon section needed for formation, and the shallow doped region defining channel region, source region, drain region respectively in described amorphous silicon section and lay respectively between described source region and channel region and between described drain region and channel region;
C, ion doping is carried out to described amorphous silicon layer, the semiconductor needed for formation;
D, annealing in process is carried out to described amorphous silicon layer, make recrystallized amorphous silicon be transformed into polysilicon, form polysilicon layer;
E, on described polysilicon layer depositing first insulator layer and the first metal film successively, and on described first metal film, make grid by etching processing procedure, afterwards ion doping carried out to the shallow doped region on described polysilicon layer;
F, on described first metal film, deposit the second insulating barrier, multiple first through hole is formed by being etched on described second insulating barrier, described first through hole runs through described first insulating barrier and the second insulating barrier, on described second insulating barrier, deposit the second metal film afterwards and form source electrode and drain electrode, described source electrode is communicated with drain region with described source region via described first through hole respectively with drain electrode;
G, on described second insulating barrier, deposit the organic photoresistance of one deck, form flatness layer, and form electrode above described flatness layer.
Further, amorphous silicon section in described step B comprises N-type doped amorphous silicon section, described channel region comprises the N channel region being positioned at described N-type doped amorphous silicon section, described source region comprises the first source region being positioned at described N-type doped amorphous silicon section, described drain region comprises the first drain region being positioned at described N-type doped amorphous silicon section, and described shallow doped region lays respectively at described first source region, between the first drain region and described N channel region.
Further, ion doping in described step C comprises channel doping and N-type doping, described channel doping is used for carrying out ion implantation to described N-type doped amorphous silicon section, and described N-type doping is used for carrying out ion implantation to described first source region and the first drain region.
Further, the source electrode in described step F comprises the first source electrode, and described drain electrode comprises the first drain electrode, and described first source electrode is communicated with the first drain region with the first source region of described N-type doped amorphous silicon section via described first through hole respectively with the first drain electrode.
Further, amorphous silicon section in described step B comprises P type doped amorphous silicon section, described channel region comprises the P channel region being positioned at described P type doped amorphous silicon section, described source region comprises the second source region being positioned at described P type doped amorphous silicon section, described drain region comprises the second drain region being positioned at described P type doped amorphous silicon section, and described shallow doped region lays respectively at described second source region, between the second drain region and described P channel region.
Further, the ion doping in described step C comprises the doping of P type, and described P type doping is used for carrying out ion implantation to described second source region and the second drain region.
Further, the source electrode in described step F comprises the second source electrode, and described drain electrode comprises the second drain electrode, and described second source electrode is communicated with the second drain region with the second source region of described P type doped amorphous silicon section via described first through hole respectively with the second drain electrode.
Further, before depositing described resilient coating in described steps A, also comprise:
Deposit light shield layer on the substrate, described resilient coating is positioned on described light shield layer.
Further, described electrode comprises the first electrode and the second electrode, and described step G specifically comprises the following steps:
G1, described second insulating barrier deposits the organic photoresistance of one deck, forms flatness layer, and form the second through hole on described flatness layer;
G2, described flatness layer deposits the first nesa coating, and forms the first electrode;
G3, described first nesa coating deposits the passivation layer for the protection of peripheral circuit;
G4, described passivation layer deposits the second nesa coating, and forms the second electrode, and described second electrode is communicated with described drain electrode by described second through hole.
Further, the material of described resilient coating is mainly silicon nitride and silica.
Beneficial effect of the present invention: the manufacture method that the invention provides a kind of low temperature polycrystalline silicon tft array substrate, this manufacture method is by after being arranged on ion doping technique by annealing in process, be cooled to so after anneal in the process of room temperature, incidentally complete ion activation process, without the need to arranging activation step again, simplify technological process, avoid the phenomenon of the heat-shrinkable increase that substrate causes due to secondary temperature elevation.
[accompanying drawing explanation]
Fig. 1 is the part manufacturing process sectional schematic diagram of low temperature polycrystalline silicon tft array substrate N-type doped amorphous silicon section in prior art;
Fig. 2 is the manufacturing process schematic diagram of low temperature polycrystalline silicon tft array substrate in the embodiment of the present invention.
Fig. 3 is the part manufacturing process sectional schematic diagram of low temperature polycrystalline silicon tft array substrate N-type doped amorphous silicon section in the embodiment of the present invention.
[embodiment]
For making technical problem to be solved by this invention, technical scheme and beneficial effect clearly understand, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the present invention, be not intended to limit the present invention.
Refer to Fig. 2 and Fig. 3, the invention provides a kind of manufacture method of low temperature polycrystalline silicon tft array substrate, it comprises the following steps in a better embodiment:
A, provide a substrate 1, buffer layer 3 and amorphous silicon layer 4M successively above this substrate 1.
Preferably, before buffer layer 3, also comprise and deposit light shield layer 2 on substrate 1, to reduce photo-generated carrier, resilient coating 3 is positioned on light shield layer 2.The material of resilient coating 3 is mainly silicon nitride and silica.
B, by etching patterned process is carried out to amorphous silicon layer 4M, amorphous silicon section needed for formation, and the shallow doped region 413 defining channel region, source region, drain region (not shown) respectively in amorphous silicon section and lay respectively between source region and channel region and between drain region and channel region.
C, ion doping is carried out to amorphous silicon layer 4M, the semiconductor needed for formation.
D, annealing in process is carried out to amorphous silicon layer 4M, make recrystallized amorphous silicon be transformed into polysilicon, form polysilicon layer 4N.
Preferably, this is annealed into laser annealing, and annealing temperature can up to 1000 DEG C.
E, on polysilicon layer 4N depositing first insulator layer 5 and the first metal film (not shown) successively, and on the first metal film, make grid 6 by etching processing procedure, afterwards ion doping carried out to the shallow doped region 414 on polysilicon layer 4N.
F, on the first metal film, deposit the second insulating barrier 7, multiple first through hole 71 is formed by being etched on the second insulating barrier 7, this first through hole 71 runs through the first insulating barrier 5 and the second insulating barrier 7, on the second insulating barrier 7, deposit the second metal film (not shown) afterwards and form source electrode and drain electrode, source electrode is communicated with drain region with source region via this first through hole 71 respectively with drain electrode.
G, on the second insulating barrier 7, deposit the organic photoresistance (not shown) of one deck, form flatness layer, and form electrode (not shown) above this flatness layer.
Preferably, this electrode comprises the first electrode (not shown) and the second electrode (not shown), this first electrode is as the bottom electrode making liquid crystal deflection, and this second electrode is as the top electrode making liquid crystal deflection, and this step G specifically comprises the following steps:
G1, the second insulating barrier 7 deposits the organic photoresistance of one deck, forms flatness layer (not shown), and on this flatness layer, forms the second through hole (not shown).
G2, this flatness layer deposits the first nesa coating (not shown), and forms the first electrode.
G3, this first nesa coating deposits the passivation layer (not shown) for the protection of peripheral circuit.
G4, this passivation layer deposits the second nesa coating (not shown), and forms the second electrode, and this second electrode is communicated with this drain electrode by this second through hole.
Concrete, this amorphous silicon section comprises N-type doped amorphous silicon section 41 and P type doped amorphous silicon section (not shown), channel region comprises the N channel region 411 being positioned at N-type doped amorphous silicon section 41 and the P channel region (not shown) being positioned at P type doped amorphous silicon section, source region comprises the first source region 412a being positioned at N-type doped amorphous silicon section 41 and the second source region (not shown) being positioned at P type doped amorphous silicon section, drain region comprises the first drain region 412b being positioned at N-type doped amorphous silicon section 41 and the second drain region (not shown) being positioned at P type doped amorphous silicon section, shallow doped region 413 lays respectively at the first source region 412a, between first drain region 412b and N channel region 411, and second source region, between second drain region and P channel region.
This source electrode comprises the first source electrode 8a corresponding to N-type doped amorphous silicon section 41 and the second source electrode corresponding to P type doped amorphous silicon section, drain electrode comprises corresponding to N-type doped amorphous silicon section 41 first drain electrode 8b and the second drain electrode corresponding to P type doped amorphous silicon section, first source electrode 8a is communicated with the first drain region 412b with the first source region 412a of N-type doped amorphous silicon section via the first through hole 71 respectively with the first drain electrode 8b, and the second source electrode is communicated with the second drain region with the second source region of P type doped amorphous silicon section via the first through hole respectively with the second drain electrode.
In addition, this ion doping comprises channel doping, N-type doping and the doping of P type successively, and channel doping is used for carrying out ion implantation to N-type doped amorphous silicon section 41.N-type doping is used for carrying out ion implantation to the first source region 412a of N-type doped amorphous silicon section 41 and the first drain region 412b, forms N type semiconductor.The doping of P type is used for carrying out ion implantation to the second source region of P type doped amorphous silicon section and the second drain region, forms P type semiconductor.
The manufacture method of above-mentioned low temperature polycrystalline silicon tft array substrate is by after being arranged on ion doping technique by annealing in process, be cooled to so after anneal in the process of room temperature, incidentally complete ion activation process, without the need to arranging activation step again, simplify technological process, avoid the phenomenon of the heat-shrinkable increase that substrate 1 causes due to secondary temperature elevation.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, all any amendments done within the spirit and principles in the present invention, equivalent replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a manufacture method for low temperature polycrystalline silicon tft array substrate, is characterized in that, comprises the following steps:
A, provide a substrate, on the substrate side's buffer layer and amorphous silicon layer successively;
B, by etching patterned process is carried out to described amorphous silicon layer, amorphous silicon section needed for formation, and the shallow doped region defining channel region, source region, drain region respectively in described amorphous silicon section and lay respectively between described source region and channel region and between described drain region and channel region;
C, ion doping is carried out to described amorphous silicon layer, the semiconductor needed for formation;
D, annealing in process is carried out to described amorphous silicon layer, make recrystallized amorphous silicon be transformed into polysilicon, form polysilicon layer;
E, on described polysilicon layer depositing first insulator layer and the first metal film successively, and on described first metal film, make grid by etching processing procedure, afterwards ion doping carried out to the shallow doped region on described polysilicon layer;
F, on described first metal film, deposit the second insulating barrier, multiple first through hole is formed by being etched on described second insulating barrier, described first through hole runs through described first insulating barrier and the second insulating barrier, on described second insulating barrier, deposit the second metal film afterwards and form source electrode and drain electrode, described source electrode is communicated with drain region with described source region via described first through hole respectively with drain electrode;
G, on described second insulating barrier, deposit the organic photoresistance of one deck, form flatness layer, and form electrode above described flatness layer.
2. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 1, it is characterized in that, amorphous silicon section in described step B comprises N-type doped amorphous silicon section, described channel region comprises the N channel region being positioned at described N-type doped amorphous silicon section, described source region comprises the first source region being positioned at described N-type doped amorphous silicon section, described drain region comprises the first drain region being positioned at described N-type doped amorphous silicon section, and described shallow doped region lays respectively at described first source region, between the first drain region and described N channel region.
3. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 2, it is characterized in that, ion doping in described step C comprises channel doping and N-type doping, described channel doping is used for carrying out ion implantation to described N-type doped amorphous silicon section, and described N-type doping is used for carrying out ion implantation to described first source region and the first drain region.
4. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 2, it is characterized in that, source electrode in described step F comprises the first source electrode, described drain electrode comprises the first drain electrode, and described first source electrode is communicated with the first drain region with the first source region of described N-type doped amorphous silicon section via described first through hole respectively with the first drain electrode.
5. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 1, it is characterized in that, amorphous silicon section in described step B comprises P type doped amorphous silicon section, described channel region comprises the P channel region being positioned at described P type doped amorphous silicon section, described source region comprises the second source region being positioned at described P type doped amorphous silicon section, described drain region comprises the second drain region being positioned at described P type doped amorphous silicon section, and described shallow doped region lays respectively at described second source region, between the second drain region and described P channel region.
6. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 5, is characterized in that, the ion doping in described step C comprises the doping of P type, and described P type doping is used for carrying out ion implantation to described second source region and the second drain region.
7. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 5, it is characterized in that, source electrode in described step F comprises the second source electrode, described drain electrode comprises the second drain electrode, and described second source electrode is communicated with the second drain region with the second source region of described P type doped amorphous silicon section via described first through hole respectively with the second drain electrode.
8. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 1, is characterized in that, before depositing described resilient coating, also comprise in described steps A:
Deposit light shield layer on the substrate, described resilient coating is positioned on described light shield layer.
9. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 1, it is characterized in that, described electrode comprises the first electrode and the second electrode, and described step G specifically comprises the following steps:
G1, described second insulating barrier deposits the organic photoresistance of one deck, forms flatness layer, and form the second through hole on described flatness layer;
G2, described flatness layer deposits the first nesa coating, and forms the first electrode;
G3, described first nesa coating deposits the passivation layer for the protection of peripheral circuit;
G4, described passivation layer deposits the second nesa coating, and forms the second electrode, and described second electrode is communicated with described drain electrode by described second through hole.
10. the manufacture method of low temperature polycrystalline silicon tft array substrate as claimed in claim 1, it is characterized in that, the material of described resilient coating is mainly silicon nitride and silica.
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| CN106128940A (en) * | 2016-08-15 | 2016-11-16 | 武汉华星光电技术有限公司 | A kind of preparation method of low-temperature polysilicon film |
| CN106407963A (en) * | 2016-11-16 | 2017-02-15 | 信利（惠州）智能显示有限公司 | Fabrication method of fingerprint identification structure |
| CN106682626A (en) * | 2016-12-29 | 2017-05-17 | 信利（惠州）智能显示有限公司 | Fingerprint identification structure and manufacturing method thereof |
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| WO2018035902A1 (en) * | 2016-08-24 | 2018-03-01 | 武汉华星光电技术有限公司 | Method for preparing low-temperature polycrystalline silicon array substrate, array substrate and display panel |
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| US10020382B1 (en) | 2016-08-24 | 2018-07-10 | Wuhan China Star Optoelectronics Technology Co., Ltd | Method of manufacturing low temperature poly-silicon array substrate, array substrate, and display panel |
| CN106407963A (en) * | 2016-11-16 | 2017-02-15 | 信利（惠州）智能显示有限公司 | Fabrication method of fingerprint identification structure |
| CN106682626A (en) * | 2016-12-29 | 2017-05-17 | 信利（惠州）智能显示有限公司 | Fingerprint identification structure and manufacturing method thereof |
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| CN108538860A (en) * | 2018-04-27 | 2018-09-14 | 武汉华星光电技术有限公司 | The production method of top gate type amorphous-silicon TFT substrate |
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