WO2019085013A1

WO2019085013A1 - Fabrication method for low-temperature polycrystalline silicon thin-film and transistor

Info

Publication number: WO2019085013A1
Application number: PCT/CN2017/110836
Authority: WO
Inventors: 何怀亮
Original assignee: 惠科股份有限公司
Priority date: 2017-11-03
Filing date: 2017-11-14
Publication date: 2019-05-09
Also published as: CN107919270A

Abstract

Provided is a fabrication method for a low-temperature polycrystalline silicon thin-film, comprising: forming a buffer layer (32) on a substrate (31); forming a silicon layer (33) on the buffer layer (32), and forming an impurity trapping layer (34) on the silicon layer (33), wherein the impurity trapping layer (34) is porous in order to accommodate the impurities diffused from the substrate (31); and retaining the impurity trapping layer (34) on the silicon layer (33) and annealing the silicon layer (33) by means of laser illumination so as to form a polycrystalline silicon layer.

Description

Low-temperature polysilicon film and transistor manufacturing method

Technical field

The present application relates to a method for fabricating a silicon thin film and a transistor, and more particularly to a method for manufacturing a low temperature polysilicon film and a transistor.

Background technique

Planar display devices have been widely used in various fields. Due to their superior characteristics such as slimness, low power consumption and no radiation, liquid crystal display devices have gradually replaced traditional cathode ray tube display devices and applied to many kinds of electronic products. Among them, such as mobile phones, portable multimedia devices, notebook computers, LCD TVs, and LCD screens, and the like.

The liquid crystal display device includes components such as a display panel, and the active matrix type liquid crystal display panel is a general display panel including an active matrix substrate, a counter substrate, and a liquid crystal layer interposed between the two substrates. The active matrix substrate has a plurality of row wires, column wires and pixels, and the pixel has a pixel driving component, and the pixel driving component is connected with the row wires and the column wires. A typical pixel drive component is a thin film transistor, and the row and column conductors are typically metal wires.

The thin film transistor of the active matrix substrate can be divided into a conventional amorphous silicon thin film transistor and a low temperature polysilicon thin film transistor with better conductivity. Low-temperature polysilicon process often uses excimer laser annealing technology, that is, using excimer laser as heat source, laser illumination sets amorphous silicon film to recrystallize amorphous silicon, and transform into polysilicon structure, because the whole process is 600. It is completed below °C, so general glass substrates are applicable. However, in laser annealing, in addition to the heating of the silicon film, the glass substrate under the silicon film also rises in temperature due to absorption of thermal energy, causing impurities in the glass substrate to diffuse into the silicon film, and these impurities reduce the semiconductor of the silicon film. characteristic.

Summary of the invention

In view of the deficiencies of the prior art, the inventors have obtained this application after research and development. SUMMARY OF THE INVENTION An object of the present application is to provide a low-temperature polysilicon film capable of reducing diffusion of a substrate impurity in a silicon film and a method of manufacturing the same.

The present application provides a method for fabricating a low temperature polysilicon film, comprising: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; forming an impurity trap layer on the silicon On the layer, the impurity-trapping layer has porosity to accommodate impurities diffused from the substrate; and leaving the impurity-trapping layer on the silicon layer and performing laser irradiation on the silicon layer Annealing to form a polysilicon layer.

In an embodiment, the manufacturing method further includes: defining a pattern in the impurity trapping layer by a photolithography etching process, wherein a direction of travel of the laser irradiation is from the side of the pattern across the pattern to the On the other side of the pattern, the polysilicon layer serves as a source and a drain of a transistor on one side and the other side of the impurity trap layer, and the polysilicon layer functions as a transistor directly under the impurity trap layer. Channel area.

In an embodiment, the impurity trapping layer is a photoresist.

In one embodiment, wherein the impurity trapping layer is a low density porous silicon oxide layer having a pore size of less than 20 nm.

In an embodiment, the pores of the impurity trapping layer serve as a recrystallization growth space.

In an embodiment, the step of forming the silicon layer on the buffer layer comprises: forming a first silicon layer on the buffer layer; and forming a second silicon layer on the first silicon layer And forming an anti-diffusion interface between the first silicon layer and the second silicon layer, wherein the second silicon layer is thicker than the first silicon layer.

In one embodiment, wherein the first silicon layer and the second silicon layer are discontinuously deposited, a discontinuous deposition interface between the first silicon layer and the second silicon layer serves as the barrier substrate Impurity interface.

In an embodiment, the manufacturing method further includes: roughening a surface of the first silicon layer to form the barrier substrate impurity interface, wherein the second silicon layer and the barrier substrate impurity interface are formed in the The roughened surface of the first silicon layer.

In an embodiment, the step of roughening the surface of the first silicon layer is etching the surface of the first silicon layer.

In an embodiment, wherein the impurity concentration in the second silicon layer is lower than the impurity concentration in the first silicon layer.

In an embodiment, wherein the buffer layer comprises a multilayer sub-buffer layer.

In one embodiment, the topmost sub-buffer layer comprises a plurality of apertures as a recrystallized growth space.

In an embodiment, the manufacturing method further includes: defining a picture in the silicon layer before annealing In this case, the pattern leaves a space for recrystallization growth.

In an embodiment, wherein the recrystallized growth space is located on a side of the pattern.

In an embodiment, the manufacturing method further includes roughening the surface of the second silicon layer as a recrystallization growth space.

The present application provides a method for fabricating a low temperature polysilicon thin film transistor, comprising: a step of a method for fabricating a low temperature polysilicon film; forming a gate insulating layer on the polysilicon layer; and forming a gate on the gate insulating layer a gate electrode; a source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically connected to the polysilicon layer.

In summary, in the method for fabricating a low temperature polysilicon thin film transistor of the present application, an impurity trap layer is formed on the silicon layer before annealing. During annealing, impurities of the substrate are also diffused to the impurity trap layer, and at least impurities in the channel region may remain in the impurity trap layer instead of all in the polysilicon layer, thereby reducing the amount of impurities in the polysilicon layer, thereby making the polysilicon film Maintain a certain level of semiconductor properties.

In addition, the method for manufacturing the low-temperature polysilicon film and the transistor of the present application can also provide a space for recrystallization of amorphous silicon, which can relieve the intergranular extrusion during the recrystallization of the amorphous silicon, thereby causing the protrusion on the surface of the polysilicon layer. The size is significantly smaller. In the preferred case, the aspect ratio of the protrusions is less than 0.3 or even less than 0.2. Therefore, in addition to reducing the amount of impurities of the polysilicon layer, the problem of protrusion on the surface of the low-temperature polysilicon film can be improved.

DRAWINGS

The drawings are included to provide a further understanding of the embodiments of the present application, and are intended to illustrate the embodiments of the present application Obviously, the drawings in the following description are only some of the embodiments of the present application, and those skilled in the art can obtain other drawings according to the drawings without any inventive labor. In the drawing:

1A to 1D are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.

1E is a schematic view of an embodiment of a method of fabricating a low temperature polysilicon thin film transistor of the present application.

2 is a schematic view of an embodiment of an impurity concentration distribution of the present application.

3A to 3G are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.

4A to 4E are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application.

5A to 5C are schematic views showing an embodiment of a modified embodiment of the low temperature polysilicon film of the present application.

Detailed ways

The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present application. The present application, however, may be embodied in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

In the description of the present application, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", The orientation or positional relationship of the "bottom", "inside", "outside" and the like is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description of the present application and simplified description, and does not indicate or imply the indicated device. The components or components must have a particular orientation, are constructed and operated in a particular orientation, and are therefore not to be construed as limiting. Moreover, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first" and "second" may include one or more of the features either explicitly or implicitly. In the description of the present application, "a plurality" means two or more unless otherwise stated. In addition, the term "comprises" and its variations are intended to cover a non-exclusive inclusion.

In the description of the present application, it should be noted that the terms "installation", "connected", and "connected" are to be understood broadly, and may be fixed or detachable, for example, unless otherwise specifically defined and defined. Connection, or integral connection; may be mechanical connection or electrical connection; may be directly connected, or may be indirectly connected through an intermediate medium, and may be internal communication between the two components. The specific meanings of the above terms in the present application can be understood in the specific circumstances for those skilled in the art.

The terminology used herein is for the purpose of describing the particular embodiments, The singular forms "a", "an", It should also be understood that the term "includes" is used herein. And/or "comprises" the existence of the stated features, integers, steps, operations, units and/or components, and does not exclude the presence or addition of one or more other features, integers, steps, operations, units, components and/or Or a combination thereof.

In the following, the in-cell touch display device according to the preferred embodiment of the present application will be described with reference to the related drawings, wherein the same components will be described with the same reference numerals.

1A to 1D are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application. As shown in FIG. 1A, a method of manufacturing a low-temperature polysilicon film first provides a substrate 11, which is, for example, a light-transmitting insulating substrate, which may be composed of glass, quartz, or the like. Then, a buffer layer 12 is formed on the substrate 11. The buffer layer 12 may be deposited by chemical vapor deposition (CVD) or sputtering, and the buffer layer 12 may be made of a material such as SiN _x , SiO _x or SiO _x N _y .

As shown in FIG. 1B, a first silicon layer 131 is formed on the buffer layer 12. The first silicon layer 131 may be deposited on the buffer layer 12 in a conventional manner, and the material of the first silicon layer 131 is amorphous silicon.

As shown in FIG. 1C, a second silicon layer 132 is formed on the first silicon layer 131, and a barrier substrate impurity interface 130 is formed between the first silicon layer 131 and the second silicon layer 132. The second silicon layer 132 may be deposited on the first silicon layer 131 in a conventional manner, and the material of the second silicon layer 132 is amorphous silicon. The second silicon layer 132 is thicker than the first silicon layer 131. The silicon layer 13 includes a first silicon layer 131 and a second silicon layer 132.

For example, the first silicon layer 131 and the second silicon layer 132 are discontinuously deposited. After the first silicon layer 131 is continuously deposited, the second silicon layer 132 is deposited at intervals, and the first silicon layer 131 and the second silicon layer are deposited. The difference between the layers 132 due to discontinuous deposition serves as the barrier substrate impurity interface 130.

In addition, the manufacturing method may further include roughening the surface of the first silicon layer 131 to form the barrier substrate impurity interface 133 before forming or depositing the second silicon layer 132 in FIG. 1B, and then proceeding as in FIG. 1C. A second silicon layer is formed or deposited on the roughened surface of a silicon layer 131, and a barrier substrate impurity interface 133 is formed. The roughened surface of the first silicon layer 131 serves as a barrier substrate impurity interface 133. The roughened surface is an uneven surface, and the step of roughening the surface of the first silicon layer 131 is to etch the surface of the first silicon layer 131, for example, the surface roughness of the roughened surface is between 5 nm and 30 nm.

Roughening may include etching, and etching may be dry etching or wet etching, dry etching process parameters The numbers include frequency, gas pressure, ion density, etching time, etc., and the process parameters of the wet etching include solution concentration, etching time, reaction temperature, stirring of the solution, and the like. By adjusting the aforementioned etching parameters, the surface after etching can have different roughness.

The roughening process eliminates the need for photomask pattern transfer, eliminating the need for photoresist on the buffer layer, and eliminating the need for a photomask and exposure.

As shown in FIG. 1D, after the silicon layer 13 of amorphous silicon is formed, the first silicon layer 131 and the second silicon layer 132 are annealed to form a polysilicon layer 13. After annealing, in the polysilicon layer 13, the impurity concentration in the second silicon layer 132 is lower than the impurity concentration in the first silicon layer 131.

Annealing is, for example, laser annealing, and the annealing process temperature is below 600 degrees Celsius. The polycrystalline silicon film obtained by such a process can be called low temperature poly-silicon (LTPS). Compared with the process temperature of the early polysilicon film up to 1000 degrees Celsius, the process temperature of the low temperature polysilicon is relatively low, so the substrate material is not limited, for example, the substrate 11 can use a glass substrate.

The polysilicon layer 13 is formed by converting an original amorphous silicon layer into a polysilicon layer by an annealing process such as laser crystalization or excimer laser annealing (ELA).

Although the impurities of the substrate 11 are still diffused during annealing and recrystallization, the barrier substrate impurity interface 133 is between the first silicon layer 131 and the second silicon layer 132, thereby increasing the diffusion of blocking impurities from the substrate 11 to the upper layer. The effect of the silicon layer 132 and the concentration distribution of the impurities are as shown in FIG. In the preferred case, most of the impurities in the silicon layer 13 are diffused to the underlying first silicon layer 131. Since the second silicon layer 132 is thicker than the first silicon layer 133, even if the first silicon layer 131 has more impurities, the entire polysilicon film 13 retains a certain level of semiconductor characteristics.

In addition, during the annealing process, the amorphous silicon in the silicon layer 13 is melted, recrystallized, and rearranged to become polycrystalline silicon, thereby forming the polysilicon layer 13, and a plurality of protrusions are formed on the surface of the polysilicon layer 13, and the protrusions may be formed. It is formed on the upper surface or the lower surface of the polysilicon layer 13.

When amorphous silicon recrystallizes, part of the amorphous silicon first acts as a recrystallized seed, and then the crystal grows into a larger crystal, and these crystals continuously grow and combine to form larger crystals. However, during the bonding process, since the crystals interact with each other, a part of the crystal is pushed onto the surface of the polysilicon layer 14 to form a protrusion.

In order to reduce the aspect ratio of the protrusions, a recrystallization space may be left in the vicinity of the silicon layer 13. For example, the surface of the buffer layer 12 in FIG. 1A may have a plurality of pores that serve as a space for subsequent silicon layer recrystallization. Before the silicon layer is formed on the buffer layer 12, the manufacturing method may further include roughening the buffer layer 12 to form voids on the surface of the buffer layer 12.

Then, after the first silicon layer 131 in FIG. 1B is formed on the surface of the buffer layer 12, the pores of the buffer layer 12 still have a space which is not filled by the material of the first silicon layer 131. Subsequently, the silicon layer 13 is annealed as shown in FIG. 1D to form a polysilicon layer 13, and a part of the silicon material of the first silicon layer 131 of the polysilicon layer 13 is filled into the pores.

Since the buffer layer 12 leaves pores for the recrystallized protrusions, at least the protrusions on the lower surface of the polysilicon layer 13 can be filled into the pores. The pores also constrain the size and shape of the protrusions to prevent the protrusions from being too large. Although protrusions (not shown) are generated on the upper surface of the polysilicon layer 13, since the partial protrusions are changed to the lower surface of the polysilicon layer 13, the protrusion of the upper surface is improved. The aspect ratio of the protrusion of the polysilicon layer of the conventional process is about 0.45. Compared with the conventional process, the aspect ratio of the protrusion of the polysilicon layer 13 can be lowered to 0.3 or less, and can even be reduced to 0.2 or less. Although the upper and lower surfaces of the polysilicon layer 13 have protrusions, the aspect ratio of the protrusions is not excessively large and affects the performance of the module.

Since the manufacturing method of the low-temperature polysilicon film can also provide a space for recrystallization of amorphous silicon, the intergranular extrusion during the recrystallization of the amorphous silicon can be relieved, and the size of the protrusion on the surface of the polysilicon layer can be significantly reduced. In the preferred case, the aspect ratio of the protrusions is less than 0.3 or even less than 0.2. Therefore, in addition to reducing the amount of impurities in the polysilicon layer, the problem of protrusion on the surface of the low-temperature polysilicon film can be improved.

1E is a schematic view of an embodiment of a method of fabricating a low temperature polysilicon thin film transistor of the present application. As shown in FIG. 1E, after the polysilicon layer 13 is formed on the substrate 11 of FIG. 1D, a subsequent process is performed to form a thin film transistor. The manufacturing method of the low temperature polysilicon thin film transistor comprises: forming a gate insulating layer 14 on the polysilicon layer 13; and forming a gate 15 on the gate insulating layer 14; forming a source electrode 17 and a drain electrode 18, the source electrode 17 The drain electrode 18 is electrically connected to the polysilicon layer 13.

For example, the low temperature polysilicon thin film transistor includes a polysilicon layer 13, a gate insulating layer 14, a gate 15, a dielectric layer 16, a source electrode 17, and a drain electrode 18. The polysilicon layer 13 is patterned first, and the patterned polysilicon layer 13 includes three regions as a source 133, a drain 135, and a channel region 134, respectively, and a channel region 134 is located between the source 133 and the drain 135. Then, after patterning A gate insulating layer 14 is formed over the polysilicon layer 13 and the substrate 11. The gate insulating layer 14 is made of, for example, silicon oxide or silicon nitride. Then, a gate 15 is formed over the gate insulating layer 14 and the channel region 134. Next, a dielectric layer 16 is formed on the gate 15 and the gate insulating layer 14, and the dielectric layer 16 and the gate insulating layer 14 are patterned to form via holes, and the via holes expose the source 133 and the drain. 135. Then, the source electrode 17 and the drain electrode 18 are formed on the surface of the dielectric layer 16 and the via hole. The source electrode 17 passes through the via hole to contact the source electrode 133, and the drain electrode 18 passes through the via hole to contact the drain electrode 135. Therefore, the source electrode 17 and The drain electrode 18 is electrically connected to the source 133 and the drain 135 of the polysilicon layer 13, respectively.

In addition, the low temperature polysilicon thin film transistor is not limited to a liquid crystal display panel or an organic light emitting diode panel.

3A to 3G are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application. As shown in FIG. 3A, a method of manufacturing a low-temperature polysilicon film first provides a substrate 21 which is, for example, a light-transmitting insulating substrate which may be composed of glass, quartz, or the like. Then, a buffer layer 22 is formed on the substrate 21. The buffer layer 22 may be deposited by chemical vapor deposition (CVD) or sputtering, and the buffer layer 22 may be made of a material such as SiN _x , SiO _x or SiO _x N _y .

As shown in FIG. 3B, a gate electrode 23 is formed on the buffer layer 22. For example, a metal layer is first deposited on the buffer layer 22, and then the metal layer is patterned to form the gate electrode 23. The metal layer is patterned by a photomask pattern transfer process. For example, an entire layer of photoresist is deposited on the unpatterned metal layer, and then the photoresist is exposed through the photomask, and the photomask pattern is first transferred to On the photoresist. Then, an etching process is used to etch the metal layer not protected by the photoresist, and thus the photomask pattern (gate pattern and wiring pattern) is transferred to the metal layer.

As shown in FIG. 3C, a patterned pad layer 26 is formed on the gate electrode 23. The pattern of the patterned pad layer 26 is the same as the pattern of the subsequent silicon layer. The patterned pad layer 26 covers the top surface and the side surface of the gate electrode 23. For example, a non-conductive material is first deposited on the gate electrode 23 and the buffer layer 22, and then the deposited non-conductive material is patterned to form a patterned pad high layer 26.

The patterned high-level pattern 26 is patterned by a photomask pattern transfer process. For example, an unpatterned non-conductive material is first deposited with a full layer of photoresist, and then the photoresist is exposed through a photomask, and the photomask is exposed. The pattern will first be transferred to the photoresist. Then, an etching process is used to etch the non-conductive material that is not protected by the photoresist, and thus the photomask pattern (using the same pattern as the subsequent channel region) Transfer to a non-conductive material. Since the pattern of the patterned pad high layer 26 is the same as the pattern of the subsequent silicon layer (only the patterned region 25a is retained in FIG. 3G), the same photomask can be shared.

The material of the patterned pad high layer 26 is made of a material such as SiN _x , SiO _x or SiO _x N _y , and can be deposited by chemical vapor deposition (CVD) or sputtering.

As shown in FIG. 3D, a first anti-diffusion layer 241 is formed on the patterned pad layer 26 and the buffer layer 22, and then a second anti-diffusion layer 242 is formed on the first anti-diffusion layer 241. The first anti-diffusion layer 241 may be deposited by chemical vapor deposition (CVD) or sputtering, and may be composed of a material such as SiN _x , SiO _x or SiO _x N _y .

Before the second anti-diffusion layer 242 is deposited, the first anti-diffusion layer 241 may be subjected to surface roughening treatment, for example, using a corrosive plasma (using NF3 or SF6 gas) to etch the surface of the first anti-diffusion layer 241 to increase the number a diffusion prevention layer 241 has surface roughness, and defects are generated on the upper surface of the first diffusion prevention layer 241. These defects catch impurity atoms diffused from the substrate 21 due to subsequent heating, so that they do not continue to diffuse into the upper layer. Therefore, it is possible to effectively block impurities from diffusing to the polysilicon layer. Next, a second anti-diffusion layer 242 is deposited, the anti-diffusion structure 24 having two layers of diffusion barrier layers.

As shown in FIG. 3E, a silicon layer 25 is formed on the second anti-diffusion layer 242, and the silicon layer 25 can be deposited on the second anti-diffusion layer 242 in a conventional manner. The material of the silicon layer 25 is amorphous silicon.

As shown in FIG. 3F, the silicon layer 25 is annealed to form a polysilicon layer 25 including a patterned region 25a and a region 25b to be removed (hereinafter referred to as region 25b), and the region 25b is a patterned region 25a. In the other portions, the patterned region 25a has the same pattern as the patterned pad layer 26, and the patterned regions 25a are all located directly above the patterned pad upper layer 26.

Compared to the region 25b, the patterned region 25a is farther from the substrate 21, and the region 25b is closer to the substrate 21. By the configuration of the patterned pad high layer 26, the patterned region 25a to be left is raised, and the region 25b where the silicon layer 25 is to be removed is closer to the substrate 21, and the impurity diffusion concentration due to the substrate 21 varies with distance. Decreasing, the impurities from the substrate 21 are more likely to accumulate in the region 25b which is closer. Therefore, the impurity concentration of the substrate 21 in the patterned region 25a is lower than that of the region 25b, and the region 25b accumulates a large amount of impurities from the substrate 21, so that the patterning region 25a which is really left remains less lining. Bottom impurities. In addition, the patterned pad high layer 26 also has a function of blocking impurities from the substrate 21.

As shown in FIG. 3G, the region 25b to be removed in the polysilicon layer 25 is removed, leaving only the patterned region 25a. The patterned region 25a includes an intermediate portion A2 and two side portions A1 and A3. The intermediate portion A2 is positioned between the side portions A1 and A3 and directly above the gate electrode 23. The side portions A1 and A3 are not located at the gate. Directly above the electrode 23. The patterned region 25a includes at least a channel region. The patterned region 25a further includes a drain and a source under a general transistor structure. For example, the middle portion of the patterned region 25a is a channel region, and the side portion is a drain and a source. . Since the polysilicon layer 25 is formed in a similar manner and structure to the polysilicon layer 13, it will not be described.

After the polysilicon layer 25 is formed, a subsequent process can be performed to form a thin film transistor. The method for manufacturing a low-temperature polysilicon thin film transistor includes the steps of a method for fabricating a low-temperature polysilicon film, forming a source electrode and a drain electrode, and electrically connecting the source electrode and the drain electrode to the polysilicon layer.

In addition, in FIG. 3B, the manufacturing method may further include: generating a defect on the upper surface of the buffer layer 22. For example, before depositing the first anti-diffusion layer 241, the buffer layer 22 may be subjected to surface roughening treatment, for example, using a corrosive plasma (using NF3 or SF6 gas) to erode the surface of the buffer layer 22 to increase the buffer layer 22 Surface roughness, and defects on the upper surface of the buffer layer 22, which trap the impurity atoms diffused from the substrate 21 due to subsequent heating, so that it does not continue to diffuse to the upper layer, thereby effectively preventing the impurities from diffusing to Polysilicon layer. Next, a first anti-diffusion layer 241 is deposited, and the overall anti-diffusion structure has three diffusion barrier layers, namely, a buffer layer 22, a first anti-diffusion layer 241, and a second anti-diffusion layer 242. Further, the surface roughening treatment of the buffer layer 22 may be performed earlier, before the gate electrode 23 is formed.

In addition, in FIG. 3C, the manufacturing method may further include: forming an impurity trap layer on the first anti-diffusion layer 241 before forming the second anti-diffusion layer 242, and then forming the second anti-diffusion layer 242 on the impurity trap layer. The impurity trap layer is, for example, a low-density porous silicon oxide layer having a pore diameter of less than 20 nm.

The material of the impurity trapping layer is, for example, a material such as SiN _x , SiO _x or SiO _x N _y . For example, the trapping layer can be achieved by adjusting the process parameters, for example, the low density SiO _x film layer can be adjusted by adjusting the ratio of the reactant SiH ₄ to N ₂ O, or the reactants TEOS and O ₂ or O _{3 .} The ratio is formed. Generally, the larger the proportion of SiH ₄ is, the more porous the SiO _x film layer is; if the proportion of gas is smaller, the density of the SiO _x film layer is smaller.

In summary, in the manufacturing method of the low temperature polysilicon thin film transistor of the present application, the lower gate structure is adopted, and the gate insulating layer on the gate electrode adopts a multi-layer diffusion barrier layer structure. Thereby, not only the gate can be used to block the diffusion of impurities from the substrate to the silicon layer, but also the diffusion barrier layer structure further blocks the diffusion of impurities from the substrate to the silicon layer. The polysilicon film is maintained at a certain level of semiconductor characteristics.

Since the polysilicon layer has different distances from the substrate, the patterned region (subsequently as a portion of the channel region) is far from the substrate, and other regions are closer to the substrate, so impurities from the substrate are not only blocked by the gate. It also diffuses first in other regions, so that the substrate in the patterned region has less impurities. In addition, the patterned pad high layer can also provide the function of blocking impurities and also help to reduce the impurity concentration of the substrate in the patterned region.

In addition, the second diffusion prevention layer 242 in FIG. 3C may also have pores for the recrystallized protrusions similar to the buffer layer 12 of the foregoing embodiment, and therefore, at least the protrusions on the lower surface of the polysilicon layer 25 may be filled into the pores. Since the relevant description can refer to the previous paragraph, it will not be described.

4A to 4D are schematic views showing an embodiment of a method for producing a low-temperature polysilicon film of the present application. As shown in FIG. 4A, a method of manufacturing a low-temperature polysilicon film first provides a substrate 31 which is, for example, a light-transmitting insulating substrate which may be composed of glass, quartz, or the like. Then, a buffer layer 32 is formed on the substrate 31. The buffer layer 32 may be deposited by chemical vapor deposition (CVD) or sputtering, and the buffer layer 32 may be made of a material such as SiN _x , SiO _x or SiO _x N _y .

As shown in FIG. 4B, a silicon layer 33 is formed on the buffer layer 32, and the silicon layer 33 can be deposited on the buffer layer 32 in a conventional manner, and the material of the silicon layer 33 is amorphous silicon.

As shown in FIG. 4C, an impurity trap layer 34 is formed on the silicon layer 33, and the impurity trap layer 34 has porosity to accommodate impurities diffused from the substrate 31.

The impurity trap layer 33 may be a low-density porous silicon oxide layer having a pore diameter of, for example, less than 20 nm. The material of the impurity trapping layer is, for example, a material such as SiN _x , SiO _x or SiO _x N _y . For example, the trapping layer can be achieved by adjusting the process parameters, for example, the low density SiO _x film layer can be adjusted by adjusting the ratio of the reactant SiH ₄ to N ₂ O, or the reactants TEOS and O ₂ or O _{3 .} The ratio is formed. Generally, the larger the proportion of SiH ₄ is, the more porous the SiO _x film layer is; if the proportion of gas is smaller, the density of the SiO _x film layer is smaller.

The impurity trap layer 33 may also be a photoresist, which is low in density compared to the impurity trap layer 33. The porous silicon oxide layer is relatively simple to use by using a photoresist.

In the example of FIG. 4C, the fabrication method defines a pattern in the impurity trap layer 34 using a photolithography etching process. This pattern can be the same as the gate. If the thin film transistor is the upper gate, the gate will be fabricated in a subsequent process. Since the impurity trap layer 34 has the same pattern as the subsequently fabricated gate, the same photomask can be shared. The impurity trap layer 33 may also be a photoresist, which is a low-density porous silicon oxide layer compared to the impurity trap layer 33, and is preferably made of a photoresist.

As shown in FIG. 4D, the impurity trap layer 34 is left on the silicon layer 33 and the silicon layer 33 is annealed by laser irradiation to form the polysilicon layer 33. In the example of FIG. 4D, the direction of travel of the laser irradiation is as shown by an arrow in the figure from the side of the impurity trap layer 34 across the impurity trap layer 34 to the other side of the impurity trap layer 34.

As shown in FIG. 4E, the impurities from the substrate 31 remain in the silicon layer 33 after being cooled by heat dissipation. During the laser annealing, the

portions

33, 333 of the silicon layer 33 which are not covered by the impurity trap layer 34 are dissipated. The speed is faster, and the impurity trapping layer 34 causes the lower portion 332 of the silicon layer 33 to dissipate heat more slowly due to the heat retention effect. Therefore, the time required for the impurities from the glass to remain in the silicon layer 33 is different, and the silicon layer 33 is different. The

portions

331, 333 that are not covered by the impurity trap layer 34 require a shorter time, and the portion 332 of the silicon layer 33 under the impurity trap layer 34 takes a longer time.

By the traveling direction of the laser irradiation across the impurity trap layer 34 as in FIG. 4D, the impurities from the glass are left earlier in the portion 331 of the silicon layer 33 on the side of the impurity trap layer 34, making the portion 331 as much as possible. The impurities in the do not spread to the portion 332. When the portion 332 is irradiated with laser light, impurities from the substrate 31 may also diffuse to the impurity trap layer 34, thereby making the impurity concentration in the portion 332 lower than that of the portion 331. After the portion 333 is irradiated by the laser, since the heat dissipation rate of the portion 333 is faster than the portion 332, the impurities remaining in the portion 333 are prevented from diffusing to the portion 332 as much as possible.

In addition, a portion 331 of the polysilicon layer 33 on one side of the impurity trap layer 34 and a portion 333 on the other side may serve as a source and a drain of the thin film transistor, and a portion of the polysilicon layer 33 under the impurity trap layer 34 may serve as a thin film transistor. Channel area.

Since the polysilicon layer 33 can refer to the related description of the foregoing polysilicon layer 13, it will not be described again.

After the polysilicon layer 33 is formed, a subsequent process may be performed as shown in FIG. 1E to form a thin film transistor. Since the manufacturing method of the transistor can refer to the related description of FIG. 1E, it will not be described again.

In addition, the impurity trap layer 34 in FIG. 4C may have a plurality of pores as a recrystallization growth space. For related explanations, reference may be made to the foregoing paragraphs, and thus will not be described again.

As shown in FIG. 5A, the buffer layer 52 may have multiple layers. For example, the buffer layer 52 includes a plurality of sub-buffer layers 521, 522. In this embodiment, two layers are taken as an example, but the number of layers is not limited to two layers, and more layers may be provided.

For example, the topmost sub-buffer layer 522 of the sub-buffer layers 521, 522 includes a plurality of apertures as a recrystallized growth space. The pores serve as a space for recrystallization growth.

The buffer layer 52 includes a first sub-buffer layer 521 and a second sub-buffer layer 522. The step of forming the buffer layer 52 includes: forming a first sub-buffer layer 521 on the substrate 51, and then forming a first sub-buffer layer 521 The second sub-buffer layer 522.

These sub-buffer layers may have different fineness, and the uppermost sub-buffer layer of the buffer layer 52 may have lower fineness, thereby forming pores on the upper surface of the uppermost sub-buffer layer to be required for recrystallization of the silicon layer. Space. For example, the second sub-buffer layer 522 is lower in fineness than the first sub-buffer layer 521. Therefore, the upper surface of the second sub-buffer layer 522 has a plurality of pores, and the pores can serve as a space for re-crystallization of the subsequent silicon layer.

In addition, before the formation of the silicon layer on the buffer layer, the manufacturing method may roughen the second sub-buffer layer 522 to form voids on the surface of the buffer layer.

The first sub-buffer layer is a diffusion barrier layer. Due to the diffusion of impurities in the substrate 51 to other layers during the annealing process, the diffusion barrier layer can block at least part of the impurities and prevent excessive impurities from diffusing into the silicon layer. The first sub-buffer layer has a higher degree of fineness than the second sub-buffer layer, thereby having a better diffusion barrier effect.

In addition, before the formation of the second sub-buffer layer 522, the manufacturing method may roughen the first sub-buffer layer 521 to have a better diffusion barrier effect.

A silicon layer 53 is formed on the second sub-buffer layer 522 of the buffer layer 52, and the silicon layer 53 includes a first silicon layer 531 and a second silicon layer 532. At this time, most of the first silicon layer 531 is formed on the upper surface of the second sub-buffer layer 522, and the pores of the second sub-buffer layer 522 still have a space not filled by the material of the first silicon layer 531. The first silicon layer 531 can be deposited on the second sub-buffer layer 222 in a conventional manner, and the material of the silicon layer 23 is amorphous silicon. For the implementation and changes of the first silicon layer 531 and the second silicon layer 532, reference may be made to the descriptions of the first silicon layer 131 and the second silicon layer 132, and thus no further description is provided.

After the first silicon layer 531 and the second silicon layer 532 of amorphous silicon are formed, the first silicon layer 531 and the second silicon layer 532 are annealed to form a polysilicon layer 53 and a part of the silicon material of the polysilicon layer 53 is filled. To the pores of the second sub-buffer layer 522. Since the description of annealing and recrystallization can be referred to the aforementioned paragraphs, it will not be described.

As shown in FIG. 5B, the buffer layer 52 can have a multi-layer structure. For reference, the description of FIG. 5A is omitted, and thus no further details are provided. The silicon layer 53 on the buffer layer 52 is a single layer, but may have a multilayer structure as shown in FIG. 1C.

Before the silicon layer 53 is annealed to form a polysilicon layer, a repair layer 54 is formed on the silicon layer 53. The complement layer 54 can be referred to the description of the trap layer 34 in FIG. 4C, and thus will not be described again.

As shown in FIG. 5C, under the lower gate structure, the substrate 61 has a buffer layer 62, a patterned pad high layer 66, a gate electrode 63, a diffusion prevention structure 64, and a silicon layer 65. The buffer layer 62 includes a first sub-buffer layer 621 and a second sub-buffer layer 622. The anti-diffusion structure 64 includes a first anti-diffusion layer 241 and a second anti-diffusion layer 242. The silicon layer 64 includes a first silicon layer 651 and For the second silicon layer 652, the related embodiments and variations may be referred to the description of the corresponding components in the foregoing embodiments, and thus are not described again.

In addition, in FIG. 1C, the method of manufacturing the low temperature polysilicon film may further include roughening the surface of the second silicon layer 132 to form a recrystallization growth space. A part of the silicon material of the polysilicon layer 13 is formed into a recrystallization growth space. The surface of the roughened second silicon layer 132 is, for example, a surface on which the second silicon layer 132 is etched. Thereby, since more recrystallization growth space is provided, the intergranular pressing during recrystallization can be relieved, and the size of the protrusion on the surface of the polysilicon layer 13 can be remarkably reduced. The silicon layer or the uppermost silicon layer in FIGS. 3D, 4B, 5A, and 5C may also be subjected to the foregoing deal with.

In addition, in FIG. 1C, the method for fabricating the low-temperature polysilicon film can further include: forming a pattern on the silicon layer 13 before annealing the amorphous silicon-silicon layer 13 to form a polysilicon layer, the pattern leaving recrystallization growing space. The recrystallized growth space is located on the side of the pattern. Thereby, since more recrystallization growth space is provided, the intergranular pressing during recrystallization can be relieved, and the size of the protrusion on the surface of the polysilicon layer 13 can be remarkably reduced. The silicon layer in FIGS. 3D, 4B, 4C, 5A, 5B, and 5C can also be subjected to the foregoing processing.

In summary, in the manufacturing method of the low-temperature polysilicon thin film transistor of the present application, the silicon layer is divided into secondary deposition, so that a barrier substrate impurity interface is between the first silicon layer and the second silicon layer, thereby increasing blocking impurities. The effect of the substrate diffusing into the upper silicon layer, in the preferred case, most of the impurities diffuse into the underlying silicon layer. The second silicon layer is thicker than the first silicon layer. Therefore, even if the first silicon layer has more impurities, the entire polysilicon film retains a certain level of semiconductor characteristics.

In summary, in the method for fabricating a low temperature polysilicon thin film transistor of the present application, an impurity trap layer is formed on the silicon layer before annealing. During annealing, impurities of the substrate are also diffused to the impurity trap layer, so that the impurities are more likely to remain in the impurity trap layer than the polysilicon layer, thereby reducing the amount of impurities in the polysilicon layer, so that the polysilicon film maintains a certain level of semiconductor characteristics.

In addition, the method for manufacturing the low-temperature polysilicon film and the transistor of the present application can also provide a space for recrystallization of amorphous silicon, which can relieve the intergranular extrusion during the recrystallization of the amorphous silicon, thereby causing the protrusion on the surface of the polysilicon layer. The size is significantly smaller. In the preferred case, the aspect ratio of the protrusions is less than 0.3 or even less than 0.2. Therefore, in addition to reducing the amount of impurities in the polysilicon layer, the problem of protrusion on the surface of the low-temperature polysilicon film can be improved.

In addition, since the aspect ratio of the surface protrusions of the polysilicon layer is less than 0.3, the component characteristics of the components can be made uniform. When such a low temperature polysilicon thin film transistor is used as the switch or driver of the display panel, the color uniformity of the display panel can be improved.

The above is a further detailed description of the present application in connection with a specific preferred embodiment. It is to be understood that the specific implementation of this application is not limited to these descriptions. It will be apparent to those skilled in the art that the present invention can be made in the form of the present invention without departing from the scope of the present invention.

Claims

A method for manufacturing a low temperature polysilicon film, comprising:

Forming a buffer layer on a substrate;

Forming a silicon layer on the buffer layer;

Forming an impurity trap layer on the silicon layer, the impurity trap layer being porous to accommodate impurities diffused from the substrate;

The impurity trapping layer is left on the silicon layer and the silicon layer is annealed by laser irradiation to form a polysilicon layer.
The method of manufacturing of claim 1 further comprising:

Defining a pattern in the impurity trapping layer by a photolithography etching process, wherein a direction of travel of the laser illumination is from the side of the pattern across the pattern to the other side of the pattern, the polysilicon layer being One side and the other side of the impurity trap layer serve as a source and a drain of a transistor, and the polysilicon layer is a channel region of a transistor directly under the impurity trap layer.
The manufacturing method according to claim 2, wherein said impurity trap layer is a photoresist.
The manufacturing method according to claim 1, wherein said impurity trap layer is a low-density porous silicon oxide layer having a pore diameter of less than 20 nm.
The manufacturing method according to claim 1, wherein the pores of the impurity-trapping layer serve as a recrystallization growth space.
The manufacturing method according to claim 1, wherein the step of forming the silicon layer on the buffer layer comprises:

Forming a first silicon layer on the buffer layer;

Forming a second silicon layer on the first silicon layer and forming an anti-diffusion interface between the first silicon layer and the second silicon layer, wherein the second silicon layer is thicker than the first Silicon layer.
The manufacturing method according to claim 6, wherein said first silicon layer and said second silicon layer are discontinuously deposited, and said discontinuous deposition interface between said first silicon layer and said second silicon layer serves as The barrier substrate impurity interface.
The method of manufacturing of claim 6 further comprising:

The surface of the first silicon layer is roughened to form the barrier substrate impurity interface, wherein the second silicon layer and the barrier substrate impurity interface are formed on a roughened surface of the first silicon layer.
The manufacturing method according to claim 8, wherein the step of roughening the surface of said first silicon layer The step is to etch the surface of the first silicon layer.
A method for manufacturing a low temperature polysilicon film, comprising:

Forming a buffer layer on a substrate;

Forming a silicon layer on the buffer layer;

Forming a first silicon layer on the buffer layer;

Forming a second silicon layer on the first silicon layer and forming a barrier substrate impurity interface between the first silicon layer and the second silicon layer;

Forming an impurity trap layer on the second silicon layer, the impurity trap layer having porosity to accommodate impurities diffused from the substrate, wherein the impurity trap layer is a photoresist;

Defining a pattern in the impurity trapping layer by a photolithography etching process, wherein a direction of travel of the laser illumination is from the side of the pattern across the pattern to the other side of the pattern, the polysilicon layer being One side and the other side of the impurity trap layer are used as a source and a drain of a transistor, and the polysilicon layer is a channel region as a transistor directly under the impurity trap layer;

The impurity trapping layer is left on the silicon layer and the first silicon layer and the second silicon layer are annealed by laser irradiation to form a polysilicon layer.
The method according to claim 10, wherein the impurity-trapping layer is a photoresist or a low-density porous silicon oxide layer having a pore diameter of less than 20 nm, wherein pores of the impurity-trapping layer serve as a recrystallization growth space.
A method for manufacturing a low temperature polysilicon thin film transistor, comprising:

Forming a buffer layer on a substrate;

Forming a silicon layer on the buffer layer;

Forming an impurity trap layer on the silicon layer, the impurity trap layer having porosity to accommodate impurities diffused from the substrate;

The impurity trapping layer is left on the silicon layer and the silicon layer is annealed by laser irradiation to form a polysilicon layer;

Forming a gate insulating layer on the polysilicon layer;

Forming a gate on the gate insulating layer;

A source electrode and a drain electrode are formed, and the source electrode and the drain electrode are electrically connected to the polysilicon layer.
The method of manufacturing of claim 12, further comprising:

Defining a pattern in the impurity trapping layer by a photolithography etching process, wherein a direction of travel of the laser illumination is from the side of the pattern across the pattern to the other side of the pattern, the polysilicon layer being One side and the other side of the impurity trap layer serve as a source and a drain of a transistor, and the polysilicon layer is a channel region of a transistor directly under the impurity trap layer.
The manufacturing method according to claim 13, wherein said impurity trap layer is a photoresist.
The manufacturing method according to claim 12, wherein said impurity trap layer is a low-density porous silicon oxide layer having a pore diameter of less than 20 nm.
The manufacturing method according to claim 12, wherein the pores of the impurity trap layer serve as a recrystallization growth space.
The manufacturing method according to claim 12, wherein the step of forming said silicon layer on said buffer layer comprises:

Forming a first silicon layer on the buffer layer;

Forming a second silicon layer on the first silicon layer and forming an anti-diffusion interface between the first silicon layer and the second silicon layer, wherein the second silicon layer is thicker than the first Silicon layer.
The manufacturing method according to claim 17, wherein said first silicon layer and said second silicon layer are discontinuously deposited, and said discontinuous deposition interface between said first silicon layer and said second silicon layer serves as a The barrier substrate impurity interface.
The method of manufacturing of claim 17 further comprising:

The surface of the first silicon layer is roughened to form the barrier substrate impurity interface, wherein the second silicon layer and the barrier substrate impurity interface are formed on a roughened surface of the first silicon layer.
The manufacturing method according to claim 19, wherein the step of roughening the surface of the first silicon layer is etching the surface of the first silicon layer.