CN103972050A - Preparation method of polycrystalline silicon thin film, polycrystalline silicon thin film transistor and array substrate - Google Patents
Preparation method of polycrystalline silicon thin film, polycrystalline silicon thin film transistor and array substrate Download PDFInfo
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- CN103972050A CN103972050A CN201410203194.5A CN201410203194A CN103972050A CN 103972050 A CN103972050 A CN 103972050A CN 201410203194 A CN201410203194 A CN 201410203194A CN 103972050 A CN103972050 A CN 103972050A
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- amorphous silicon
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- polysilicon
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 86
- 239000000758 substrate Substances 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title claims abstract description 30
- 239000010409 thin film Substances 0.000 title claims abstract description 29
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 101
- 238000000034 method Methods 0.000 claims abstract description 88
- 238000005224 laser annealing Methods 0.000 claims abstract description 28
- 150000002815 nickel Chemical class 0.000 claims abstract description 27
- 239000012266 salt solution Substances 0.000 claims abstract description 27
- 239000012528 membrane Substances 0.000 claims description 114
- 229920005591 polysilicon Polymers 0.000 claims description 76
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 34
- 229920002120 photoresistant polymer Polymers 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 23
- 239000010408 film Substances 0.000 claims description 19
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- 238000002425 crystallisation Methods 0.000 claims description 14
- 230000008025 crystallization Effects 0.000 claims description 14
- 238000009413 insulation Methods 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 239000000203 mixture Substances 0.000 claims description 11
- 238000010129 solution processing Methods 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000001312 dry etching Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims description 6
- 238000007654 immersion Methods 0.000 claims description 2
- 239000013078 crystal Substances 0.000 abstract description 16
- 239000010410 layer Substances 0.000 description 60
- 239000002585 base Substances 0.000 description 11
- 239000007789 gas Substances 0.000 description 10
- 239000011521 glass Substances 0.000 description 10
- 239000011229 interlayer Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 238000000137 annealing Methods 0.000 description 6
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 238000002513 implantation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000003595 mist Substances 0.000 description 4
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 4
- 229910021334 nickel silicide Inorganic materials 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000009616 inductively coupled plasma Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000003475 lamination Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- PEUPIGGLJVUNEU-UHFFFAOYSA-N nickel silicon Chemical compound [Si].[Ni] PEUPIGGLJVUNEU-UHFFFAOYSA-N 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 241000931526 Acer campestre Species 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- -1 as CF 4 Chemical compound 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000003795 desorption Methods 0.000 description 2
- 229910001092 metal group alloy Inorganic materials 0.000 description 2
- 229910021645 metal ion Inorganic materials 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 239000004338 Dichlorodifluoromethane Substances 0.000 description 1
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 229910001413 alkali metal ion Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000003197 catalytic effect Effects 0.000 description 1
- 238000006555 catalytic reaction Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- 235000019404 dichlorodifluoromethane Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007715 excimer laser crystallization Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000009938 salting Methods 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000011734 sodium Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
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Abstract
The embodiment of the invention provides a preparation method of a polycrystalline silicon thin film, a polycrystalline silicon thin film transistor and an array substrate and relates to the technical field of display. By means of the preparation method, polycrystalline silicon crystals are uniform, the grain size is increased, crystal quality is improved, and therefore the electrical properties of the thin film transistor are improved. The preparation method of the polycrystalline silicon thin film comprises the steps that an amorphous silicon thin film is formed on a substrate; the amorphous silicon thin film is treated through an excimer laser annealing method, so that the amorphous silicon thin film is crystallized into the polycrystalline silicon thin film. Furthermore, after the amorphous silicon thin film is formed and before the amorphous silicon thin film is treated though the excimer laser annealing method, the preparation method further comprises the steps that the surface of the amorphous silicon thin film is subjected to nickel salt solution treatment, so that a nickel salt solution is uniformly smeared on the surface of the amorphous silicon thin film. The method is used for preparation of the polycrystalline silicon thin film, the low-temperature polycrystalline silicon thin film transistor and the array substrate requiring that the uniformity of the polycrystalline silicon crystals is improved, the grain size is increased, and crystal quality is improved.
Description
Technical field
The present invention relates to Display Technique field, relate in particular to the preparation method of a kind of preparation method of polysilicon membrane, the preparation method of low-temperature polysilicon film transistor and array base palte.
Background technology
Low-temperature polysilicon film transistor (Low Temperature Poly-Silicon-ThinFilm Transistor, being called for short LTPS-TFT) display has the advantages such as high-resolution, reaction speed are fast, high brightness, high aperture, add due to LTPS, make it there is high electron mobility; In addition, peripheral drive circuit can also be produced on glass substrate simultaneously, reach the cost of target, saving space and the drive IC of system combination, and can reduce product fraction defective.
At present, described low-temperature polysilicon film transistor comprises active layer, gate insulation layer, gate electrode, source electrode and the drain electrode being arranged on underlay substrate; Described active layer comprises source region, drain region and the channel region between described source region and drain region etc.
Wherein, active layer is by carrying out obtaining after ion implantation technology to polysilicon layer, described polysilicon layer generally by forming amorphous silicon membrane on underlay substrate, adopt afterwards quasi-molecule laser annealing method that amorphous silicon is converted into polysilicon, then by composition technique, make polysilicon membrane form the polysilicon layer of specific pattern.
Yet excimer laser is as a kind of gas laser, its stability is poor, and preparation-obtained polysilicon grain uniformity is poor, thereby causes the electrology characteristic uniformity of thin-film transistor poor.In addition, common Excimer-Laser Crystallization technique makes amorphous silicon melting recrystallization in a short period of time, and its crystallite dimension is less, and crystalline quality is not high yet, has limited the lifting of film transistor device electric property.
Summary of the invention
Embodiments of the invention provide the preparation method of a kind of polysilicon membrane, polycrystalline SiTFT and array base palte, can make polysilicon crystal even, and increase crystallite dimension, crystalline quality is improved, thereby the electric property of thin-film transistor is got a promotion.
For achieving the above object, embodiments of the invention adopt following technical scheme:
On the one hand, provide a kind of preparation method of polysilicon membrane, comprising: on underlay substrate, form amorphous silicon membrane; Adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is polysilicon membrane; Further, after forming described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises: nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
On the other hand, provide a kind of preparation method of polycrystalline SiTFT, comprising: on underlay substrate, form active layer, be positioned at gate insulation layer, gate electrode, source electrode and drain electrode above described active layer; Described active layer comprises source area, drain region, the channel region between described source area and described drain region; Wherein, described active layer is to carry out doping process formation by the region corresponding with described source area and described drain region to polysilicon layer; Described polysilicon layer is that above-mentioned polysilicon membrane carries out composition technique and obtains.
Again on the one hand, provide a kind of preparation method of array base palte, comprising: form thin-film transistor and pixel electrode; Wherein, described thin-film transistor forms by the preparation method of above-mentioned polycrystalline SiTFT.
The embodiment of the present invention provides the preparation method of a kind of polysilicon membrane, polycrystalline SiTFT and array base palte, and the preparation method of described polysilicon membrane is included in and on underlay substrate, forms amorphous silicon membrane; Adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is polysilicon membrane; Further, after forming described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises: nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
Before described amorphous silicon membrane being processed in employing quasi-molecule laser annealing method, nickel salt solution processing has been carried out in the surface of amorphous silicon membrane, the residual nickel of meeting is on the surface of amorphous silicon membrane, through quasi-molecule laser annealing, process, the nickel silicide that nickel and silicon form, as the seed crystal of amorphous silicon crystallization, can promote that amorphous silicon changes to polysilicon, and make polysilicon crystal even, crystallite dimension is large, and crystalline quality is high, thereby the electric property of the thin-film transistor of preparation is got a promotion.
Accompanying drawing explanation
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The preparation method's of a kind of polycrystalline SiTFT that Fig. 1 provides for the embodiment of the present invention schematic flow sheet;
A kind of process schematic diagram of preparing polycrystalline SiTFT that Fig. 2-7 provide for the embodiment of the present invention;
The structural representation one of a kind of array base palte that Fig. 8 provides for the embodiment of the present invention;
The structural representation two of a kind of array base palte that Fig. 9 provides for the embodiment of the present invention.
Reference numeral:
10-underlay substrate; 20-resilient coating; 30-polysilicon layer; 301-amorphous silicon membrane; 302-polysilicon membrane; 40-gate insulation layer; 50-gate electrode; 60-active layer; 601-source area; 602-drain region; 603-channel region; 70-interlayer insulating film; 801-source electrode; 802-drain electrode; 90-planarization layer; 100-pixel electrode; 110-passivation layer; 120-public electrode.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of preparation method of polysilicon membrane, comprising: on underlay substrate, form amorphous silicon membrane; Adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is polysilicon membrane; Further, after forming described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises: nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
Wherein, adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is that polysilicon membrane passes through following process implementation, that is: adopt excimer laser irradiation to process, at about 50～150ns, in the time, make amorphous silicon membrane surface moment reach more than 1000 ℃ high temperature and become molten condition; Then the amorphous silicon of molten condition is annealed, make it crystallization and form polysilicon membrane.
In this process, can also guarantee that the temperature of glass substrate substrate is 400 ℃ of left and right or following.Its mechanism is: first laser pulse inspires hot electron-hole pair in amorphous silicon membrane, and electron-hole pair passes to lattice atoms in non-radiative compound mode by energy more afterwards, thereby realizes the transient heating of amorphous silicon membrane.Wherein, because the transient energy of laser pulse is absorbed by amorphous silicon membrane and is converted into phase-change energy, therefore do not have too much thermal energy conduction to glass substrate substrate, can avoid in general furnace annealing, glass substrate substrate temperature being raise and producing the problem of being out of shape.
On the basis of the above, before described amorphous silicon membrane being processed in employing quasi-molecule laser annealing method, nickel (Ni) salting liquid has been carried out in the surface of amorphous silicon membrane to be processed, the residual nickel of meeting is on the surface of amorphous silicon membrane, thereby, through quasi-molecule laser annealing, to process, nickel and silicon can react, generating nickel-silicon key, the mixture of formation nickel-silicon.Because the free energy of crystallization of silicon state is lower than amorphous state, the fracture of nickel-silicon key has promoted amorphous silicon to polysilicon local crystal lattice recombination with this heat balance process of restructuring.Wherein, the nickel silicide (SiN that nickel and silicon form
2) at 350 ℃, be easy to form, the lattice constant of its lattice constant and silicon only differs 0.4%, be suitable as very much the seed crystal of amorphous silicon crystallization, can promote that amorphous silicon changes to polysilicon on the one hand, owing to there being more uniform nucleating center (seed crystal), can make polysilicon crystal even on the other hand, and owing to there being the catalytic action of nickel, under same temperature-time, the longer crystallite dimension of catalysis is larger, thereby makes crystalline quality higher.
The embodiment of the present invention provides a kind of preparation method of polysilicon membrane, comprising: on underlay substrate, form amorphous silicon membrane; Adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is polysilicon membrane; Further, after forming described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises: nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.Before described amorphous silicon membrane being processed in employing quasi-molecule laser annealing method, nickel salt solution processing has been carried out in the surface of amorphous silicon membrane, the residual nickel of meeting is on the surface of amorphous silicon membrane, through quasi-molecule laser annealing, process, the nickel silicide that nickel and silicon form, as the seed crystal of amorphous silicon crystallization, can promote that amorphous silicon changes to polysilicon, and make polysilicon crystal even, crystallite dimension is large, and crystalline quality is high; When this polysilicon membrane is during for the preparation of the active layer of thin-film transistor, can make the electric property of thin-film transistor get a promotion.
Optionally, can adopt the method for immersion or splash, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
Consider when the concentration of nickel is excessive in nickel salt solution and can cause more nickel metal ion to enter amorphous silicon layer, cause nucleating center to affect too much the growth of crystal grain, crystallite dimension is reduced, meanwhile, also likely cause metal ion pollution; Therefore, the nickel salt solution in the embodiment of the present invention only need adopt the solution containing micro-nickel, and the concentration that preferably adopts nickel is the solution of 1～1000 μ g/mg.
Description based on above-mentioned, for fear of when adopting quasi-molecule laser annealing method to process described amorphous silicon membrane, produces the problem of quick-fried hydrogen.Preferred after nickel salt solution processing is carried out in the surface of described amorphous silicon membrane in the embodiment of the present invention, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described amorphous silicon membrane is carried out to dehydrogenating technology processing, make hydrogen content in described amorphous silicon membrane below 3%.
Herein, desorption temperature can be at 400～600 ℃, and the processing time can be at 20～120 minutes.
It should be noted that, if adopt additive method that hydrogen content in amorphous silicon membrane has been controlled at below 3%, this step can be omitted, and specifically can carry out according to actual conditions.
The embodiment of the present invention also provides a kind of preparation method of polycrystalline SiTFT, comprising: on underlay substrate, form active layer, be positioned at gate insulation layer, gate electrode, source electrode and drain electrode above described active layer; Described active layer comprises source area, drain region, the channel region between described source area and described drain region; Wherein, described active layer is to carry out doping process formation by the region corresponding with described source area and described drain region to polysilicon layer; Described polysilicon layer obtains for polysilicon membrane obtained above is carried out to composition technique.
Before described amorphous silicon membrane being processed in employing quasi-molecule laser annealing method, nickel salt solution processing has been carried out in the surface of amorphous silicon membrane, the residual nickel of meeting is on the surface of amorphous silicon membrane, through quasi-molecule laser annealing, process, the nickel silicide that nickel and silicon form, as the seed crystal of amorphous silicon crystallization, can promote that amorphous silicon changes to polysilicon, and make polysilicon crystal even, crystallite dimension is large, and crystalline quality is high, and the electric property of thin-film transistor is got a promotion.
Preferably, the thickness of described polysilicon layer is
Preferably, described polysilicon layer obtains for polysilicon membrane is carried out to composition technique, specifically can realize as follows:
S101, be formed with on the substrate of polysilicon membrane, form photoresist film.
S102, employing normal masks plate are to being formed with the base board to explosure of described photoresist film, and after developing, the formation complete reserve part of photoresist and photoresist are removed part completely; Wherein, the complete reserve part of described photoresist is corresponding with described polysilicon layer, and photoresist is removed the corresponding remainder of part completely.
S103, employing dry etching are removed the described polysilicon membrane that described photoresist is removed part completely, form described polysilicon layer.
Wherein, dry etching can be selected the methods such as plasma etching, reactive ion etching, inductively coupled plasma etching, and etching gas can be selected gas fluorine-containing, chlorine, as carbon tetrafluoride (CF
4), fluoroform (CHF
3), sulphur hexafluoride (SF
6), dichlorodifluoromethane (CCl
2f
2) etc. or these gases and oxygen (O
2) mist.
S104, employing stripping technology are removed the complete reserve part of described photoresist.
In the embodiment of the present invention, adopt dry etching to form described polysilicon layer, be because dry etching can be extraordinary the sidewall profile of the described polysilicon layer that forms of control, can control the both sides sidewall energy vertical substrates substrate of described polysilicon layer, like this, make the performance of the final active layer forming better, avoided the impact on thin-film transistor performance.
On the basis of the above, consider in glass substrate substrate and include harmful substances, as alkali metal ion, can impact polysilicon layer performance, therefore, the invention process is preferably: before forming described polysilicon membrane, on described underlay substrate surface, form resilient coating.
Based on the above-mentioned description to the preparation method of polycrystalline SiTFT, the embodiment of the present invention provides a specific embodiment, to describe the preparation method of described polycrystalline SiTFT in detail.As shown in Figure 1, the method comprises the steps:
S201, as shown in Figure 2 forms resilient coating 20 on underlay substrate 10.
Concrete, on the transparent substrates substrates 10 such as glass through cleaning in advance, with methods such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapour deposition (APCVD), electron cyclotron resonance chemical vapour deposition (CVD) (ECR-CVD) or sputters, form resilient coating 20, for stopping that the contained Impurity Diffusion of glass enters in active layer, prevents the characteristics such as the threshold voltage of thin-film transistor element and leakage current to exert an influence.
Wherein, this resilient coating 20 can be silica, silicon nitride or the lamination of the two of individual layer.The thickness of described resilient coating 20 can be
preferred thickness is
When adopting deposition process to form described resilient coating 20, depositing temperature is controlled under 600 ℃ or lower temperature.
In addition, because the metals content impurities such as aluminium, barium and sodium in traditional alkali glass are higher, the diffusion of metal impurities easily occurs in high-temperature processing technology, therefore, the glass substrate substrate in the embodiment of the present invention preferably adopts alkali-free glass.
S202, as shown in Figure 2, completes on the basis of S201, on described resilient coating 20, forms amorphous silicon membrane 301.
Concrete, can adopt PECVD, LPCVD or sputtering method to form described amorphous silicon membrane 301.When adopting deposition process to form described amorphous silicon membrane 301, depositing temperature is controlled at below 600 ℃.
Wherein, amorphous silicon membrane 301 thickness can be
preferred thickness is
S203, complete on the basis of S202, with nickel salt solution, described amorphous silicon membrane is being soaked or splash is processed, making described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
Concrete, preferably adopting nickel concentration is that the nickel salt solution of 1～1000 μ g/mg soaks described amorphous silicon membrane or splash is processed.
S204, completing on the basis of S203, the substrate that is formed with amorphous silicon membrane is placed in to annealing furnace and carries out dehydrogenation processing.
Concrete, this substrate is placed in to annealing furnace and is incubated certain hour, the hydrogen content in amorphous silicon is reduced, conventionally need be controlled at below 3%, to avoid in the follow-up quick-fried problem of hydrogen that produces while carrying out laser annealing technique.
Wherein, desorption temperature can be at 400～600 ℃, and the processing time can be at 20～120 minutes.
S205, complete on the basis of S204, adopt quasi-molecule laser annealing method to process described amorphous silicon membrane 301, making described amorphous silicon membrane 301 crystallization for polysilicon membrane 302 as shown in Figure 3.
The adoptable laser of this step has: ArF, KrF and XeCl, and corresponding optical maser wavelength is respectively 193nm, 248nm and 308nm, and pulsewidth is between 10～50ns.Because the optical maser wavelength of XeCl laser is longer, laser energy injection amorphous silicon membrane is darker, and crystallization effect is better, and therefore, the embodiment of the present invention preferably adopts XeCl laser.
S206, complete on the basis of S205, polysilicon membrane 302 is being carried out to composition PROCESS FOR TREATMENT, forming polysilicon layer 30 as shown in Figure 4.
Concrete, on described polysilicon membrane 302, form photoresist film; And adopt normal masks plate to being formed with the base board to explosure of described photoresist film, after developing, the formation complete reserve part of photoresist and photoresist are removed part completely; Wherein, the complete reserve part of described photoresist is corresponding with described polysilicon layer, and photoresist is removed the corresponding remainder of part completely; Adopt dry etching to remove the described polysilicon membrane that described photoresist is removed part completely, form described polysilicon layer; Adopt stripping technology that the complete reserve part of described photoresist is removed.
Wherein, dry etching can be selected the methods such as plasma etching, reactive ion etching, inductively coupled plasma etching, and etching gas can be selected gas fluorine-containing, chlorine, as CF
4, CHF
3, SF
6, CCl
2f
2deng or these gases and O
2mist.
S207, as shown in Figure 5, completes on the basis of S206, forms gate insulation layer 40 and gate electrode 50.
Concrete, can adopt the method deposition gate insulation layers 40 such as PECVD, LPCVD, APCVD or ECR-CVD.Then adopt the methods such as sputter, thermal evaporation or PECVD, LPCVD, APCVD, ECR-CVD on gate insulation layer 40, to form grid metal level, and form described gate electrode 50 by composition technique.
Wherein, this gate insulation layer 40 can be silica, silicon nitride or the lamination of the two of individual layer.The thickness of gate insulation layer 40 can be
preferred thickness is
Gate electrode 50 can consist of as electric conducting materials such as molybdenum, molybdenum alloys metal, metal alloy.Thickness can be
preferred thickness is
S208, complete on the basis of S207, ion implantation technology is being carried out in the region corresponding with described source area and described drain region of polysilicon layer 30, forming active layer 60 as shown in Figure 6.Described active layer 60 comprises source area 601, drain region 602, the channel region 603 between described source area 601 and described drain region 602.
Concrete, Implantation can adopt the methods such as the injection of ion cloud formula, plasma injection or the injection of solid-state diffusion formula that have the Implantation of mass-synchrometer, do not have mass-synchrometer, can need to adopt boracic as B according to design
2h
6/ H
2, or phosphorous as PH
3/ H
2mist inject, ion implantation energy can be 10～200keV, preferred energy is at 40～100keV, implantation dosage can be at 1x10
11～1x10
20atoms/cm
3in scope, preferred dose is at 1x10
13～8x10
15atoms/cm
3.
In addition after Implantation, can activate by the method for rapid thermal annealing, laser annealing or furnace annealing.Wherein, the method for furnace annealing is comparatively economical, simple, and uniformity is better, preferably adopts in embodiments of the present invention in annealing furnace and processes with 300～600 ℃ of activation heats that carry out 0.5～4 hour (being preferably 1～3 hour).
S209, as shown in Figure 7, completes on the basis of S208, forms interlayer insulating film 70, and on described interlayer insulating film 70, forms source electrode 801 and drain electrode 802.Wherein, described source electrode 801 contacts with 601He drain region, described source area 602 with the via hole on described gate insulation layer 40 by being formed on described interlayer insulating film 70 respectively with drain electrode 802.
Concrete, can adopt the methods such as PECVD, LPCVD, APCVD or ECR-CVD at the temperature below 600 ℃, to deposit described interlayer insulating film 70.Then adopt the methods such as sputter, thermal evaporation or PECVD, LPCVD, APCVD, ECR-CVD formation source on gate insulation layer to leak metal level, and form described source electrode 801 and drain electrode 802 by composition technique.
Wherein, this interlayer insulating film 70 can be the silica of individual layer or the lamination of silica and silicon nitride.The thickness of interlayer insulating film 70 can be
preferred thickness is
During via hole on forming described interlayer insulating film 70, can adopt dry etching, that is: can select the methods such as plasma etching, reactive ion etching, inductively coupled plasma etching, etching gas can be selected gas fluorine-containing, chlorine, as CF
4, CHF
3, SF
6, CCl
2f
2deng or these gases and O
2mist.
Source electrode 801 and drain electrode 802 can consist of as electric conducting materials such as molybdenum, molybdenum alloy, aluminium, aluminium alloy, titaniums metal, metal alloy.Thickness can be
preferred thickness is
When forming source electrode 801 and drain electrode 802 by composition technique, can adopt wet etching or dry etching.
By above-mentioned steps S201～S209, just can prepare high-quality low-temperature polysilicon film transistor.
On the basis of the polycrystalline SiTFT of above-mentioned formation, the embodiment of the present invention also provides a kind of preparation method of array base palte, comprising:
S301, as shown in Figure 8, on the basis of above-mentioned steps S209, forms planarization layer 90, and form the pixel electrode 100 being electrically connected to described drain electrode 802 on described planarization layer 90.
Wherein, the material of described planarization layer 100 can be for example photonasty or non-photosensitive resin material, and thickness can be 1.5 μ m～5 μ m.
The material of described pixel electrode 100 can be tin indium oxide (ITO), and thickness can be
On this basis, described method can also comprise:
S302, as shown in Figure 9, on the basis of above-mentioned S301, forms passivation layer 110, and form public electrode 120 on described passivation layer 110.
Here, only take described pixel electrode 100 and described public electrode 120 different layers to describe as example, but the embodiment of the present invention is not limited to this, described pixel electrode 100 and described public electrode 120 with interlayer every formation.
Certainly, the array base palte that the embodiment of the present invention provides is also used in OLED escope, does not repeat them here.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (10)
1. a preparation method for polysilicon membrane, comprising: on underlay substrate, form amorphous silicon membrane; Adopt quasi-molecule laser annealing method to process described amorphous silicon membrane, making described amorphous silicon membrane crystallization is polysilicon membrane; It is characterized in that, after forming described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises:
Nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, make described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
2. method according to claim 1, is characterized in that, described nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, makes described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane, comprising:
The method that adopts immersion or splash, makes described nickel salt solution evenly be applied to the surface of described amorphous silicon membrane.
3. method according to claim 1, is characterized in that, in described nickel salt solution, the concentration of nickel is 1～1000 μ g/mg.
4. according to the method described in claims 1 to 3 any one, it is characterized in that, after nickel salt solution processing is carried out in the surface of described amorphous silicon membrane, before employing quasi-molecule laser annealing method is processed described amorphous silicon membrane, described method also comprises:
Described amorphous silicon membrane is carried out to dehydrogenating technology processing, make hydrogen content in described amorphous silicon membrane below 3%.
5. a preparation method for polycrystalline SiTFT, comprising: on underlay substrate, form active layer, be positioned at gate insulation layer, gate electrode, source electrode and drain electrode above described active layer; Described active layer comprises source area, drain region, the channel region between described source area and described drain region; Wherein, described active layer is to carry out doping process formation by the region corresponding with described source area and described drain region to polysilicon layer; It is characterized in that,
Described polysilicon layer obtains for the polysilicon membrane described in claim 1 to 4 any one is carried out to composition technique.
6. method according to claim 5, is characterized in that, described polysilicon layer obtains for polysilicon membrane is carried out to composition technique, comprising:
Be formed with on the substrate of polysilicon membrane, forming photoresist film;
Adopt normal masks plate to being formed with the base board to explosure of described photoresist film, after developing, the formation complete reserve part of photoresist and photoresist are removed part completely; Wherein, the complete reserve part of described photoresist is corresponding with described polysilicon layer, and photoresist is removed the corresponding remainder of part completely;
Adopt dry etching to remove the described polysilicon membrane that described photoresist is removed part completely, form described polysilicon layer;
Adopt stripping technology that the complete reserve part of described photoresist is removed.
7. method according to claim 5, is characterized in that, the thickness of described polysilicon layer is
8. according to the method described in claim 5 to 7 any one, it is characterized in that, described method also comprises: before forming described polysilicon membrane, on described underlay substrate surface, form resilient coating.
9. a preparation method for array base palte, comprising: form thin-film transistor and pixel electrode; It is characterized in that, described thin-film transistor forms by the preparation method of the polycrystalline SiTFT described in claim 5 to 8 any one.
10. method according to claim 9, is characterized in that, also comprises formation public electrode.
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| WO2017210923A1 (en) * | 2016-06-07 | 2017-12-14 | 深圳市华星光电技术有限公司 | Method for manufacturing tft backplane and tft backplane |
| US10283355B2 (en) | 2016-10-27 | 2019-05-07 | Boe Technology Group Co., Ltd. | Method for manufacturing poly-silicon layer, thin film transistor, array substrate and display device |
| CN106548926A (en) * | 2016-10-27 | 2017-03-29 | 京东方科技集团股份有限公司 | The preparation method of polysilicon layer, thin film transistor (TFT), array base palte and display device |
| CN106548926B (en) * | 2016-10-27 | 2018-04-10 | 京东方科技集团股份有限公司 | Preparation method, thin film transistor (TFT), array base palte and the display device of polysilicon layer |
| CN109643657A (en) * | 2017-06-22 | 2019-04-16 | 深圳市柔宇科技有限公司 | The production method of the making apparatus and array substrate of array substrate |
| CN109643657B (en) * | 2017-06-22 | 2022-08-16 | 深圳市柔宇科技股份有限公司 | Manufacturing equipment and manufacturing method of array substrate |
| CN107369613A (en) * | 2017-07-21 | 2017-11-21 | 京东方科技集团股份有限公司 | Polysilicon membrane, the preparation method of thin film transistor (TFT), equipment, display base plate |
| CN111162000A (en) * | 2018-11-08 | 2020-05-15 | 陕西坤同半导体科技有限公司 | Polycrystalline silicon film and preparation method thereof |
| CN111223754A (en) * | 2018-11-23 | 2020-06-02 | 陕西坤同半导体科技有限公司 | Polycrystalline silicon film and preparation method thereof |
| CN109712933A (en) * | 2019-02-19 | 2019-05-03 | 合肥鑫晟光电科技有限公司 | Production method, display base plate and the display panel of display base plate |
| CN114496737A (en) * | 2020-11-12 | 2022-05-13 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
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| WO2015172543A1 (en) | 2015-11-19 |
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