CN105140180A - Manufacturing method of thin-film transistor array substrate and preparation method of polycrystalline silicon material - Google Patents
Manufacturing method of thin-film transistor array substrate and preparation method of polycrystalline silicon material Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 55
- 239000002210 silicon-based material Substances 0.000 title claims abstract description 54
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 38
- 239000010409 thin film Substances 0.000 title claims abstract description 37
- 239000000758 substrate Substances 0.000 title claims abstract description 14
- 238000002360 preparation method Methods 0.000 title abstract 2
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 87
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 32
- 239000001257 hydrogen Substances 0.000 claims abstract description 32
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 238000002425 crystallisation Methods 0.000 claims abstract description 7
- 230000008025 crystallization Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 48
- 239000011248 coating agent Substances 0.000 claims description 12
- 238000000576 coating method Methods 0.000 claims description 12
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 description 6
- 150000002431 hydrogen Chemical class 0.000 description 5
- 238000005224 laser annealing Methods 0.000 description 3
- KZMAWJRXKGLWGS-UHFFFAOYSA-N 2-chloro-n-[4-(4-methoxyphenyl)-1,3-thiazol-2-yl]-n-(3-methoxypropyl)acetamide Chemical compound S1C(N(C(=O)CCl)CCCOC)=NC(C=2C=CC(OC)=CC=2)=C1 KZMAWJRXKGLWGS-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000004992 fission Effects 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B28/00—Production of homogeneous polycrystalline material with defined structure
- C30B28/02—Production of homogeneous polycrystalline material with defined structure directly from the solid state
-
- C—CHEMISTRY; METALLURGY
- C30—CRYSTAL GROWTH
- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
- C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
- C30B29/02—Elements
- C30B29/06—Silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
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- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
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- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Thin Film Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a thin-film transistor array substrate and a preparation method of a polycrystalline silicon material. The manufacturing method of the thin-film transistor array substrate comprises the steps as follows: (A) a buffer layer and an amorphous silicon layer are arranged on a substrate; (B) the amorphous silicon layer is irradiated by ultraviolet light, so that a silicon-hydrogen bond in the amorphous silicon layer is broken; and the irradiation time is first preset time; (C) the amorphous silicon layer which is irradiated by the ultraviolet light is heated by infrared light, so that hydrogen in the amorphous silicon layer is separated from the amorphous silicon layer; and the heating time is second preset time; (D) the heated amorphous silicon layer is cleaned; (E) the cleaned amorphous silicon layer is subjected to annealing crystallization treatment by laser to form a polysilicon layer; and (F) a display device is arranged on the polysilicon layer and/or the buffer layer. According to the manufacturing method, the manufacturing cost of the thin-film transistor array substrate can be effectively reduced; the manufacturing time of the thin-film transistor array substrate can be effectively shortened; and the manufacturing efficiency of the thin-film transistor array substrate is improved.
Description
[technical field]
The present invention relates to Display Technique field, particularly a kind of manufacture method of thin-film transistor array base-plate and the manufacture method of polycrystalline silicon material.
[background technology]
Quasi-molecule laser annealing (ELA, ExcimerLaserAnnealing) is the important procedure in traditional LTPS-TFT-LCD (LowTemperaturePolySiliconThinFilmTransistorLiquidCrystal Display), amorphous silicon being made into polysilicon.
In general, the hydrogen content in amorphous silicon is approximately 10%.Produce the good polysilicon of quality, need to heat-treat amorphous silicon, to remove the hydrogen in amorphous silicon.And in ELA operation, require that the content of hydrogen reaches less than 1%, otherwise in amorphous silicon membrane, there will be the quick-fried phenomenon of hydrogen, this can cause the surface of polysilicon to there is serious defect.
Will heat-treat amorphous silicon, generally need amorphous silicon to be heated to higher temperature (such as, 490 degrees Celsius to 520 degrees Celsius), the time of heating is more than 20 minutes.This considerably increases manufacturing cost and manufacturing time.
Therefore, be necessary to propose a kind of new technical scheme, to solve the problems of the technologies described above.
[summary of the invention]
The object of the present invention is to provide a kind of manufacture method of thin-film transistor array base-plate and the manufacture method of polycrystalline silicon material, it effectively can reduce manufacturing cost and the manufacturing time of thin-film transistor array base-plate, improves the manufacture efficiency of thin-film transistor array base-plate.
For solving the problem, technical scheme of the present invention is as follows:
A kind of manufacture method of thin-film transistor array base-plate, said method comprising the steps of: A, resilient coating and amorphous silicon layer are set on substrate, wherein, described resilient coating is positioned on described substrate, described amorphous silicon layer is positioned on described resilient coating, and described amorphous silicon layer is the material layer formed by amorphous silicon material; B, utilize amorphous silicon layer described in UV-irradiation, to make the silicon-hydrogen bond in described amorphous silicon layer rupture, irradiation time was first scheduled time; C, utilize infrared ray to heat the described amorphous silicon layer after described UV-irradiation, to make the hydrogen in described amorphous silicon layer depart from from described amorphous silicon layer, heating time was second scheduled time; D, to through heating after described amorphous silicon layer clean; E, utilize laser by cleaning after described amorphous silicon layer carry out annealing crystallization process, to form polysilicon layer; And F, display device is set on described polysilicon layer and/or on described resilient coating, to form thin-film transistor array base-plate, wherein, described display device at least comprises holding wire, pixel electrode.
In the manufacture method of above-mentioned thin-film transistor array base-plate, described first scheduled time is in the scope of 20 seconds to 300 seconds.
In the manufacture method of above-mentioned thin-film transistor array base-plate, described second scheduled time is in the scope of 1 minute to 20 minutes.
In the manufacture method of above-mentioned thin-film transistor array base-plate, the temperature of the described amorphous silicon layer after described Infrared irradiation is in predetermined temperature range, and described predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius.
In the manufacture method of above-mentioned thin-film transistor array base-plate, the hydrogen content in the described amorphous silicon layer after heating is less than or equal to 1.0%.
A manufacture method for polycrystalline silicon material, said method comprising the steps of: A, utilize UV-irradiation amorphous silicon material, and to make the silicon-hydrogen bond in described amorphous silicon material rupture, irradiation time was first scheduled time; B, utilize infrared ray to heat the described amorphous silicon material after described UV-irradiation, to make the hydrogen in described amorphous silicon material depart from from described amorphous silicon material, heating time was second scheduled time; C, to through heating after described amorphous silicon material clean; And D, utilize laser by cleaning after described amorphous silicon material carry out annealing crystallization process, to form polycrystalline silicon material.
In the manufacture method of above-mentioned polycrystalline silicon material, described first scheduled time is in the scope of 20 seconds to 300 seconds.
In the manufacture method of above-mentioned polycrystalline silicon material, described second scheduled time is in the scope of 1 minute to 20 minutes.
In the manufacture method of above-mentioned polycrystalline silicon material, the temperature of the described amorphous silicon layer after described Infrared irradiation is in predetermined temperature range, and described predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius.
In the manufacture method of above-mentioned polycrystalline silicon material, the hydrogen content in the described amorphous silicon layer after heating is less than or equal to 1.0%.
Hinge structure, the present invention effectively reduces manufacturing cost and the manufacturing time of thin-film transistor array base-plate or polycrystalline silicon material, improves the manufacture efficiency of described thin-film transistor array base-plate or described polycrystalline silicon material.
For foregoing of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, be described in detail below.
[accompanying drawing explanation]
Fig. 1 to Fig. 5 is the schematic diagram of the manufacture method of thin-film transistor array base-plate of the present invention;
Fig. 6 is the flow chart of the manufacture method of thin-film transistor array base-plate of the present invention;
Fig. 7 is the flow chart of the manufacture method of polycrystalline silicon material of the present invention.
[embodiment]
The word " embodiment " that this specification uses means example, example or illustration.In addition, the article " " used in this specification and claims usually can be interpreted as " one or more ", can know unless otherwise or from context and determine singulative.
Be the schematic diagram of the manufacture method of thin-film transistor array base-plate of the present invention referring to figs. 1 to Fig. 6, Fig. 1 to Fig. 5, Fig. 6 is the flow chart of the manufacture method of thin-film transistor array base-plate of the present invention.
The manufacture method of the thin-film transistor array base-plate of the present embodiment comprises the following steps:
Step 601, resilient coating 102 and amorphous silicon layer 103 are set on the substrate 101, wherein, described resilient coating 102 is positioned on described substrate 101, and described amorphous silicon layer 103 is positioned on described resilient coating 102, and described amorphous silicon layer 103 is the material layers formed by amorphous silicon material.
Step 602, utilize ultraviolet light 201 to irradiate described amorphous silicon layer 103, to make silicon-hydrogen (Si-H) bond fission in described amorphous silicon layer 103, irradiation time was first scheduled time.
Step 603, infrared ray 301 is utilized to heat through the postradiation described amorphous silicon layer 103 of described ultraviolet light 201, depart from (such as from described amorphous silicon layer 103 to make the hydrogen (element) of the amorphous silicon molecule 1 031 in described amorphous silicon layer 103, hydrogen in described amorphous silicon layer 103 is overflowed from described amorphous silicon layer 103 with the form of hydrogen), heating time was second scheduled time.
Step 604, to through heating after described amorphous silicon layer 103 clean.
Step 605, utilize laser by cleaning after described amorphous silicon layer 103 carry out annealing crystallization process, to form polysilicon layer 401.Technology corresponding to this step is ELA (ExcimerLaserAnnealing, quasi-molecule laser annealing) technology.
Step 606, display device 501 is set on described polysilicon layer 401 and/or on described resilient coating 102, to form thin-film transistor array base-plate, wherein, described display device 501 at least comprises holding wire, pixel electrode, and described holding wire comprises scan line, data wire.
In the present embodiment, described first scheduled time is in the scope of 20 seconds to 300 seconds (5 minutes), such as, described first scheduled time is 20 seconds, 25 seconds, 30 seconds, 35 seconds, 40 seconds, 45 seconds, 50 seconds, 55 seconds, 60 seconds, 65 seconds, 70 seconds, 75 seconds, 80 seconds, 85 seconds, 90 seconds, 95 seconds, 100 seconds, 105 seconds, 110 seconds, 115 seconds, 120 seconds, 125 seconds, 130 seconds, 135 seconds, 140 seconds, 145 seconds, 150 seconds, 155 seconds, 160 seconds, 165 seconds, 170 seconds, 175 seconds, 180 seconds, 185 seconds, 190 seconds, 195 seconds, 200 seconds, 205 seconds, 210 seconds, 215 seconds, 220 seconds, 225 seconds, 230 seconds, 235 seconds, 240 seconds, 245 seconds, 250 seconds, 255 seconds, 260 seconds, 265 seconds, 270 seconds, 275 seconds, 280 seconds, 285 seconds, 290 seconds, 295 seconds, 300 seconds.
Preferably, described first scheduled time is in the scope of 1 minute to 2 minutes.
In the present embodiment, described second scheduled time is in the scope of 1 minute to 20 minutes, and such as, described second scheduled time is 60 seconds, 75 seconds, 90 seconds, 105 seconds, 120 seconds, 135 seconds, 150 seconds, 165 seconds, 180 seconds, 195 seconds, 210 seconds, 225 seconds, 240 seconds, 255 seconds, 270 seconds, 285 seconds, 300 seconds, 315 seconds, 330 seconds, 345 seconds, 360 seconds, 375 seconds, 390 seconds, 405 seconds, 420 seconds, 435 seconds, 450 seconds, 465 seconds, 480 seconds, 495 seconds, 510 seconds, 525 seconds, 540 seconds, 555 seconds, 570 seconds, 585 seconds, 600 seconds, 615 seconds, 630 seconds, 645 seconds, 660 seconds, 675 seconds, 690 seconds, 705 seconds, 720 seconds, 735 seconds, 750 seconds, 765 seconds, 780 seconds, 795 seconds, 810 seconds, 825 seconds, 840 seconds, 855 seconds, 870 seconds, 885 seconds, 900 seconds, 915 seconds, 930 seconds, 945 seconds, 960 seconds, 975 seconds, 990 seconds, 1005 seconds, 1020 seconds, 1035 seconds, 1050 seconds, 1065 seconds, 1080 seconds, 1095 seconds, 1110 seconds, 1125 seconds, 1140 seconds, 1155 seconds, 1170 seconds, 1185 seconds, 1200 seconds.
Preferably, described second scheduled time is in the scope of 10 minutes to 15 minutes.
In the present embodiment, the temperature of the described amorphous silicon layer 103 after described Infrared irradiation is in predetermined temperature range, described predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius, such as, described temperature is 300 degrees Celsius, 305 degrees Celsius, 310 degrees Celsius, 315 degrees Celsius, 320 degrees Celsius, 325 degrees Celsius, 330 degrees Celsius, 335 degrees Celsius, 340 degrees Celsius, 345 degrees Celsius, 350 degrees Celsius, 355 degrees Celsius, 360 degrees Celsius, 365 degrees Celsius, 370 degrees Celsius, 375 degrees Celsius, 380 degrees Celsius, 385 degrees Celsius, 390 degrees Celsius, 395 degrees Celsius, 400 degrees Celsius.
Preferably, described predetermined temperature range is 350 degrees Celsius to 400 degrees Celsius.Being conducive at described thin-film transistor array base-plate is like this flexible thin-film transistor array base-plate (containing polyimide substrate), and when the temperature that the thin-film transistor array base-plate of described flexibility can bear is less than 400 degrees Celsius, prevents the thin-film transistor array base-plate Yin Wendu of described flexibility too high and damage.
In the present embodiment, hydrogen content in described amorphous silicon layer 103 after heating is less than or equal to 1.0%, namely, hydrogen (H) content in described polysilicon layer 401 is less than or equal to 1.0%, such as, described hydrogen content is 0.03%, 0.11%, 0.19%, 0.27%, 0.35%, 0.43%, 0.51%, 0.59%, 0.67%, 0.75%, 0.83%, 0.91%, 1.0%.
By technique scheme, effectively can reduce manufacturing cost and the manufacturing time of described thin-film transistor array base-plate, improve the manufacture efficiency of described thin-film transistor array base-plate.
With reference to the flow chart that figure 7, Fig. 7 is the manufacture method of polycrystalline silicon material of the present invention.
The manufacture method of the polycrystalline silicon material of the present embodiment comprises the following steps:
Step 701, utilize ultraviolet light 201 to irradiate amorphous silicon material, to make silicon-hydrogen (Si-H) bond fission in described amorphous silicon material, irradiation time was first scheduled time.
Step 702, infrared ray 301 is utilized to heat through the postradiation described amorphous silicon material of described ultraviolet light 201, depart from (such as from described amorphous silicon material to make the hydrogen (element) of the amorphous silicon molecule 1 031 in described amorphous silicon material, hydrogen in described amorphous silicon material is overflowed from described amorphous silicon material with the form of hydrogen), heating time was second scheduled time.
Step 703, to through heating after described amorphous silicon material clean.
Step 704, utilize laser by cleaning after described amorphous silicon material carry out annealing crystallization process, to form polycrystalline silicon material.Technology corresponding to this step is ELA (ExcimerLaserAnnealing, quasi-molecule laser annealing) technology.
In the present embodiment, described first scheduled time is in the scope of 20 seconds to 300 seconds (5 minutes), such as, described first scheduled time is 20 seconds, 25 seconds, 30 seconds, 35 seconds, 40 seconds, 45 seconds, 50 seconds, 55 seconds, 60 seconds, 65 seconds, 70 seconds, 75 seconds, 80 seconds, 85 seconds, 90 seconds, 95 seconds, 100 seconds, 105 seconds, 110 seconds, 115 seconds, 120 seconds, 125 seconds, 130 seconds, 135 seconds, 140 seconds, 145 seconds, 150 seconds, 155 seconds, 160 seconds, 165 seconds, 170 seconds, 175 seconds, 180 seconds, 185 seconds, 190 seconds, 195 seconds, 200 seconds, 205 seconds, 210 seconds, 215 seconds, 220 seconds, 225 seconds, 230 seconds, 235 seconds, 240 seconds, 245 seconds, 250 seconds, 255 seconds, 260 seconds, 265 seconds, 270 seconds, 275 seconds, 280 seconds, 285 seconds, 290 seconds, 295 seconds, 300 seconds.
Preferably, described first scheduled time is in the scope of 1 minute to 2 minutes.
In the present embodiment, described second scheduled time is in the scope of 1 minute to 20 minutes, and such as, described second scheduled time is 60 seconds, 75 seconds, 90 seconds, 105 seconds, 120 seconds, 135 seconds, 150 seconds, 165 seconds, 180 seconds, 195 seconds, 210 seconds, 225 seconds, 240 seconds, 255 seconds, 270 seconds, 285 seconds, 300 seconds, 315 seconds, 330 seconds, 345 seconds, 360 seconds, 375 seconds, 390 seconds, 405 seconds, 420 seconds, 435 seconds, 450 seconds, 465 seconds, 480 seconds, 495 seconds, 510 seconds, 525 seconds, 540 seconds, 555 seconds, 570 seconds, 585 seconds, 600 seconds, 615 seconds, 630 seconds, 645 seconds, 660 seconds, 675 seconds, 690 seconds, 705 seconds, 720 seconds, 735 seconds, 750 seconds, 765 seconds, 780 seconds, 795 seconds, 810 seconds, 825 seconds, 840 seconds, 855 seconds, 870 seconds, 885 seconds, 900 seconds, 915 seconds, 930 seconds, 945 seconds, 960 seconds, 975 seconds, 990 seconds, 1005 seconds, 1020 seconds, 1035 seconds, 1050 seconds, 1065 seconds, 1080 seconds, 1095 seconds, 1110 seconds, 1125 seconds, 1140 seconds, 1155 seconds, 1170 seconds, 1185 seconds, 1200 seconds.
Preferably, described second scheduled time is in the scope of 10 minutes to 15 minutes.
In the present embodiment, the temperature of the described amorphous silicon material after described Infrared irradiation is in predetermined temperature range, described predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius, such as, described temperature is 300 degrees Celsius, 305 degrees Celsius, 310 degrees Celsius, 315 degrees Celsius, 320 degrees Celsius, 325 degrees Celsius, 330 degrees Celsius, 335 degrees Celsius, 340 degrees Celsius, 345 degrees Celsius, 350 degrees Celsius, 355 degrees Celsius, 360 degrees Celsius, 365 degrees Celsius, 370 degrees Celsius, 375 degrees Celsius, 380 degrees Celsius, 385 degrees Celsius, 390 degrees Celsius, 395 degrees Celsius, 400 degrees Celsius.
Preferably, described predetermined temperature range is 350 degrees Celsius to 400 degrees Celsius.
In the present embodiment, hydrogen content in described amorphous silicon material after heating is less than or equal to 1.0%, namely, hydrogen (H) content in described polycrystalline silicon material is less than or equal to 1.0%, such as, described hydrogen content is 0.03%, 0.11%, 0.19%, 0.27%, 0.35%, 0.43%, 0.51%, 0.59%, 0.67%, 0.75%, 0.83%, 0.91%, 1.0%.
By technique scheme, effectively can reduce manufacturing cost and the manufacturing time of described polycrystalline silicon material, improve the manufacture efficiency of described polycrystalline silicon material.
Although illustrate and describe the present invention relative to one or more implementation, those skilled in the art are based on to the reading of this specification and accompanying drawing with understand and will expect equivalent variations and amendment.The present invention includes all such amendments and modification, and only limited by the scope of claims.Especially about the various functions performed by said modules, term for describing such assembly is intended to the random component (unless otherwise instructed) corresponding to the appointed function (such as it is functionally of equal value) performing described assembly, even if be not structurally equal to the open structure of the function in the exemplary implementations performing shown in this article specification.In addition, although the special characteristic of this specification relative in some implementations only one be disclosed, this feature can with can be such as expect and other Feature Combinations one or more of other favourable implementations for given or application-specific.And, " comprise " with regard to term, " having ", " containing " or its distortion be used in embodiment or claim with regard to, such term is intended to comprise " to comprise " similar mode to term.
In sum; although the present invention discloses as above with preferred embodiment; but above preferred embodiment is also not used to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; all can do various change and retouching, the scope that therefore protection scope of the present invention defines with claim is as the criterion.
Claims (10)
1. a manufacture method for thin-film transistor array base-plate, is characterized in that, said method comprising the steps of:
A, on substrate, arrange resilient coating and amorphous silicon layer, wherein, described resilient coating is positioned on described substrate, and described amorphous silicon layer is positioned on described resilient coating, and described amorphous silicon layer is the material layer formed by amorphous silicon material;
B, utilize amorphous silicon layer described in UV-irradiation, to make the silicon-hydrogen bond in described amorphous silicon layer rupture, irradiation time was first scheduled time;
C, utilize infrared ray to heat the described amorphous silicon layer after described UV-irradiation, to make the hydrogen in described amorphous silicon layer depart from from described amorphous silicon layer, heating time was second scheduled time;
D, to through heating after described amorphous silicon layer clean;
E, utilize laser by cleaning after described amorphous silicon layer carry out annealing crystallization process, to form polysilicon layer; And
F, on described polysilicon layer and/or on described resilient coating, arrange display device, to form thin-film transistor array base-plate, wherein, described display device at least comprises holding wire, pixel electrode.
2. the manufacture method of thin-film transistor array base-plate according to claim 1, is characterized in that, described first scheduled time is in the scope of 20 seconds to 300 seconds.
3. the manufacture method of thin-film transistor array base-plate according to claim 1, is characterized in that, described second scheduled time is in the scope of 1 minute to 20 minutes.
4. the manufacture method of thin-film transistor array base-plate according to claim 1, it is characterized in that, the temperature of the described amorphous silicon layer after described Infrared irradiation is in predetermined temperature range, and described predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius.
5. the manufacture method of the thin-film transistor array base-plate according to claim 1 or 4, is characterized in that, the hydrogen content in the described amorphous silicon layer after heating is less than or equal to 1.0%.
6. a manufacture method for polycrystalline silicon material, is characterized in that, said method comprising the steps of:
A, utilize UV-irradiation amorphous silicon material, to make the silicon-hydrogen bond in described amorphous silicon material rupture, irradiation time was first scheduled time;
B, utilize infrared ray to heat the described amorphous silicon material after described UV-irradiation, to make the hydrogen in described amorphous silicon material depart from from described amorphous silicon material, heating time was second scheduled time;
C, to through heating after described amorphous silicon material clean; And
D, utilize laser by cleaning after described amorphous silicon material carry out annealing crystallization process, to form polycrystalline silicon material.
7. the manufacture method of polycrystalline silicon material according to claim 6, is characterized in that, described first scheduled time is in the scope of 20 seconds to 300 seconds.
8. the manufacture method of polycrystalline silicon material according to claim 6, is characterized in that, described second scheduled time is in the scope of 1 minute to 20 minutes.
9. the manufacture method of polycrystalline silicon material according to claim 6, is characterized in that, the temperature of the described amorphous silicon layer after described Infrared irradiation is in predetermined temperature range, and described predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius.
10. the manufacture method of the polycrystalline silicon material according to claim 6 or 9, is characterized in that, the hydrogen content in the described amorphous silicon layer after heating is less than or equal to 1.0%.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107275198A (en) * | 2017-05-31 | 2017-10-20 | 昆山国显光电有限公司 | Laser anneal method and laser annealing system |
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| CN116002690A (en) * | 2022-12-30 | 2023-04-25 | 浙大宁波理工学院 | Method and device for removing hydrogen atoms on surface of granular silicon |
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| CN103972050A (en) * | 2014-05-14 | 2014-08-06 | 京东方科技集团股份有限公司 | Preparation method of polycrystalline silicon thin film, polycrystalline silicon thin film transistor and array substrate |
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| CN106087040B (en) * | 2016-07-14 | 2018-07-27 | 京东方科技集团股份有限公司 | Multichip semiconductor crystallization system and the method that polycrystallization is carried out to single crystalline semiconductor substrate |
| CN107275198A (en) * | 2017-05-31 | 2017-10-20 | 昆山国显光电有限公司 | Laser anneal method and laser annealing system |
| CN107275198B (en) * | 2017-05-31 | 2020-03-10 | 昆山国显光电有限公司 | Laser annealing method and laser annealing system |
| CN116002690A (en) * | 2022-12-30 | 2023-04-25 | 浙大宁波理工学院 | Method and device for removing hydrogen atoms on surface of granular silicon |
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| CN105140180B (en) | 2018-03-13 |
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