CN105140180B - The preparation method of thin-film transistor array base-plate and the preparation method of polycrystalline silicon material - Google Patents

The preparation method of thin-film transistor array base-plate and the preparation method of polycrystalline silicon material Download PDF

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CN105140180B
CN105140180B CN201510521942.9A CN201510521942A CN105140180B CN 105140180 B CN105140180 B CN 105140180B CN 201510521942 A CN201510521942 A CN 201510521942A CN 105140180 B CN105140180 B CN 105140180B
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seconds
amorphous silicon
silicon layer
preparation method
thin
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CN105140180A (en
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唐丽娟
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武汉华星光电技术有限公司
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B28/00Production of homogeneous polycrystalline material with defined structure
    • C30B28/02Production of homogeneous polycrystalline material with defined structure directly from the solid state
    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL-GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02Elements
    • C30B29/06Silicon
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
    • H01L27/127Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors

Abstract

The invention discloses a kind of preparation method of thin-film transistor array base-plate and the preparation method of polycrystalline silicon material.The preparation method of the thin-film transistor array base-plate comprises the following steps:Cushion and amorphous silicon layer are set on substrate A,;B, using ultraviolet light amorphous silicon layer, so that the si-h bond fracture in amorphous silicon layer, irradiation time was first scheduled time;C, the amorphous silicon layer after ultraviolet light is heated using infrared ray, so that the hydrogen in amorphous silicon layer departs from from amorphous silicon layer, the heat time was second scheduled time;D, the amorphous silicon layer after heating is cleaned;E, the amorphous silicon layer after cleaning is subjected to annealing crystallization processing using laser, to form polysilicon layer;Display device is set on the polysilicon layer and/or on cushion F,.The present invention can effectively reduce the manufacturing cost and manufacturing time of thin-film transistor array base-plate, improve the manufacture efficiency of thin-film transistor array base-plate.

Description

The preparation method of thin-film transistor array base-plate and the preparation method of polycrystalline silicon material

【Technical field】

The present invention relates to display technology field, the preparation method and polycrystalline of more particularly to a kind of thin-film transistor array base-plate The preparation method of silicon materials.

【Background technology】

Quasi-molecule laser annealing (ELA, Excimer Laser Annealing) is traditional LTPS-TFT-LCD (Low Temperature Poly Silicon Thin FilmTransistor Liquid Crystal Display) in by amorphous Silicon is fabricated to an important procedure of polysilicon.

In general, the hydrogen content in non-crystalline silicon is about 10%.The preferable polysilicon of quality is produced, it is necessary to non- Crystal silicon is heat-treated, to remove the hydrogen in non-crystalline silicon.And require that the content of hydrogen reaches less than 1% in ELA processes, otherwise amorphous The quick-fried phenomenon of hydrogen occurs in silicon thin film, this can cause the surface of polysilicon the defects of serious to be present.

Non-crystalline silicon is heat-treated, generally require and non-crystalline silicon is heated to higher temperature (for example, 490 degrees Celsius To 520 degrees Celsius), the time of heating is more than 20 minutes.This considerably increases manufacturing cost and manufacturing time.

Therefore, it is necessary to a kind of new technical scheme is proposed, to solve above-mentioned technical problem.

【The content of the invention】

It is an object of the invention to provide a kind of preparation method of thin-film transistor array base-plate and the system of polycrystalline silicon material Make method, it can effectively reduce the manufacturing cost and manufacturing time of thin-film transistor array base-plate, improve thin film transistor (TFT) array The manufacture efficiency of substrate.

To solve the above problems, technical scheme is as follows:

A kind of preparation method of thin-film transistor array base-plate, the described method comprises the following steps:A, set on substrate Cushion and amorphous silicon layer, wherein, the cushion is located on the substrate, and the amorphous silicon layer is located on the cushion, The amorphous silicon layer is the material layer formed by amorphous silicon material;B, using amorphous silicon layer described in ultraviolet light, so that described Silicon-hydrogen bond fracture in amorphous silicon layer, irradiation time was first scheduled time;C, using infrared ray to passing through the ultraviolet light The amorphous silicon layer after irradiation is heated, so that the hydrogen in the amorphous silicon layer departs from from the amorphous silicon layer, heating Time was second scheduled time;D, the amorphous silicon layer after heating is cleaned;E, using laser by after cleaning The amorphous silicon layer carries out annealing crystallization processing, to form polysilicon layer;It is and F, on the polysilicon layer and/or described slow Rush and display device be set on layer, to form thin-film transistor array base-plate, wherein, the display device comprise at least signal wire, Pixel electrode;In the range of second scheduled time is in 1 minute to 20 minutes;Institute after infrared ray irradiation The temperature for stating amorphous silicon layer is in predetermined temperature range, and the predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius.

In the preparation method of above-mentioned thin-film transistor array base-plate, first scheduled time is in 20 seconds to 300 seconds In the range of.

In the preparation method of above-mentioned thin-film transistor array base-plate, the hydrogen in the amorphous silicon layer after heating contains Amount is less than or equal to 1.0%.

A kind of preparation method of polycrystalline silicon material, the described method comprises the following steps:A, ultraviolet light non-crystalline silicon is utilized Material, so that the silicon-hydrogen bond fracture in the amorphous silicon material, irradiation time was first scheduled time;B, infrared ray is utilized The amorphous silicon material after the ultraviolet light is heated, so that the hydrogen in the amorphous silicon material is from described Depart from amorphous silicon material, the heat time was second scheduled time;C, the amorphous silicon material after heating is carried out clear Wash;And D, using laser by after cleaning the amorphous silicon material carry out annealing crystallization processing, to form polycrystalline silicon material;Institute Stated for second scheduled time in the range of 1 minute to 20 minutes;The amorphous silicon layer after infrared ray irradiation Temperature be in predetermined temperature range, the predetermined temperature range be 300 degrees Celsius to 400 degrees Celsius.

In the preparation method of above-mentioned polycrystalline silicon material, in the range of first scheduled time is in 20 seconds to 300 seconds.

In the preparation method of above-mentioned polycrystalline silicon material, the hydrogen content in the amorphous silicon layer after heating be less than or Equal to 1.0%.

Compared with the prior art, the present invention effectively reduce thin-film transistor array base-plate or polycrystalline silicon material manufacturing cost and Manufacturing time, improve the manufacture efficiency of the thin-film transistor array base-plate or the polycrystalline silicon material.

For the above of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate institute's accompanying drawings, make Describe in detail as follows.

【Brief description of the drawings】

Fig. 1 to Fig. 5 is the schematic diagram of the preparation method of the thin-film transistor array base-plate of the present invention;

Fig. 6 is the flow chart of the preparation method of the thin-film transistor array base-plate of the present invention;

Fig. 7 is the flow chart of the preparation method of the polycrystalline silicon material of the present invention.

【Embodiment】

Word used in this specification " embodiment " means example, example or illustration.In addition, this specification and appended power Profit require used in article " one " can usually be interpreted " one or more ", unless otherwise or from context It can understand and determine singulative.

Referring to figs. 1 to Fig. 6, Fig. 1 to Fig. 5 is the schematic diagram of the preparation method of the thin-film transistor array base-plate of the present invention, Fig. 6 is the flow chart of the preparation method of the thin-film transistor array base-plate of the present invention.

The preparation method of the thin-film transistor array base-plate of the present embodiment comprises the following steps:

Step 601, cushion 102 and amorphous silicon layer 103 are set on the substrate 101, wherein, the cushion 102 is located at On the substrate 101, the amorphous silicon layer 103 is located on the cushion 102, and the amorphous silicon layer 103 is by non-crystalline silicon material Expect the material layer formed.

Step 602, using ultraviolet light 201 amorphous silicon layer 103 is irradiated, so that silicon-hydrogen in the amorphous silicon layer 103 (Si-H) key is broken, and irradiation time was first scheduled time.

Step 603, using infrared ray 301 to by the ultraviolet light 201 irradiation after the amorphous silicon layer 103 carry out Heating, so that the hydrogen (element) of the non-crystalline silicon molecule 1031 in the amorphous silicon layer 103 departs from from the amorphous silicon layer 103 (for example, the hydrogen in the amorphous silicon layer 103 is escaped in the form of hydrogen from the amorphous silicon layer 103), heat time Two scheduled times.

Step 604, the amorphous silicon layer 103 after heating is cleaned.

Step 605, using laser the amorphous silicon layer 103 after cleaning is subjected to annealing crystallization processing, to form polycrystalline Silicon layer 401.Technology corresponding to this step is ELA (Excimer Laser Annealing, quasi-molecule laser annealing) skill Art.

Step 606, display device 501 is set, to be formed on the polysilicon layer 401 and/or on the cushion 102 Thin-film transistor array base-plate, wherein, the display device 501 comprises at least signal wire, pixel electrode, and the signal wire includes Scan line, data wire.

In the present embodiment, first scheduled time is in the range of 20 seconds to 300 seconds (5 minutes), for example, described First scheduled time be 20 seconds, 25 seconds, 30 seconds, 35 seconds, 40 seconds, 45 seconds, 50 seconds, 55 seconds, 60 seconds, 65 seconds, 70 seconds, 75 seconds, 80 Second, 85 seconds, 90 seconds, 95 seconds, 100 seconds, 105 seconds, 110 seconds, 115 seconds, 120 seconds, 125 seconds, 130 seconds, 135 seconds, 140 seconds, 145 Second, 150 seconds, 155 seconds, 160 seconds, 165 seconds, 170 seconds, 175 seconds, 180 seconds, 185 seconds, 190 seconds, 195 seconds, 200 seconds, 205 seconds, 210 seconds, 215 seconds, 220 seconds, 225 seconds, 230 seconds, 235 seconds, 240 seconds, 245 seconds, 250 seconds, 255 seconds, 260 seconds, 265 seconds, 270 Second, 275 seconds, 280 seconds, 285 seconds, 290 seconds, 295 seconds, 300 seconds.

Preferably, first scheduled time is in the range of 1 minute to 2 minutes.

In the present embodiment, second scheduled time be in 1 minute to 20 minutes in the range of, for example, described second The scheduled time be 60 seconds, 75 seconds, 90 seconds, 105 seconds, 120 seconds, 135 seconds, 150 seconds, 165 seconds, 180 seconds, 195 seconds, 210 seconds, 225 Second, 240 seconds, 255 seconds, 270 seconds, 285 seconds, 300 seconds, 315 seconds, 330 seconds, 345 seconds, 360 seconds, 375 seconds, 390 seconds, 405 seconds, 420 seconds, 435 seconds, 450 seconds, 465 seconds, 480 seconds, 495 seconds, 510 seconds, 525 seconds, 540 seconds, 555 seconds, 570 seconds, 585 seconds, 600 Second, 615 seconds, 630 seconds, 645 seconds, 660 seconds, 675 seconds, 690 seconds, 705 seconds, 720 seconds, 735 seconds, 750 seconds, 765 seconds, 780 seconds, 795 seconds, 810 seconds, 825 seconds, 840 seconds, 855 seconds, 870 seconds, 885 seconds, 900 seconds, 915 seconds, 930 seconds, 945 seconds, 960 seconds, 975 Second, 990 seconds, 1005 seconds, 1020 seconds, 1035 seconds, 1050 seconds, 1065 seconds, 1080 seconds, 1095 seconds, 1110 seconds, 1125 seconds, 1140 Second, 1155 seconds, 1170 seconds, 1185 seconds, 1200 seconds.

Preferably, second scheduled time is in the range of 10 minutes to 15 minutes.

In the present embodiment, the temperature of the amorphous silicon layer 103 after the Infrared irradiation is in predetermined temperature In the range of, the predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius, for example, the temperature is 300 degrees Celsius, 305 take the photograph Family name's degree, 310 degrees Celsius, 315 degrees Celsius, 320 degrees Celsius, 325 degrees Celsius, 330 degrees Celsius, 335 degrees Celsius, 340 degrees Celsius, 345 degrees Celsius, 350 degrees Celsius, 355 degrees Celsius, 360 degrees Celsius, 365 degrees Celsius, 370 degrees Celsius, 375 degrees Celsius, it is 380 Celsius Spend, 385 degrees Celsius, 390 degrees Celsius, 395 degrees Celsius, 400 degrees Celsius.

Preferably, the predetermined temperature range is 350 degrees Celsius to 400 degrees Celsius.So be advantageous to brilliant in the film Body pipe array base palte is flexible thin-film transistor array base-plate (containing polyimide substrate), and the flexible film is brilliant When the temperature that body pipe array base palte can be born is less than 400 degrees Celsius, prevent the flexible thin-film transistor array base-plate because of temperature Spend high and damage.

In the present embodiment, the hydrogen content in the amorphous silicon layer 103 after heating is less than or equal to 1.0%, i.e. Hydrogen (H) content in the polysilicon layer 401 is less than or equal to 1.0%, for example, the hydrogen content is 0.03%, 0.11%, 0.19%th, 0.27%, 0.35%, 0.43%, 0.51%, 0.59%, 0.67%, 0.75%, 0.83%, 0.91%, 1.0%.

Pass through above-mentioned technical proposal, when can effectively reduce manufacturing cost and the manufacture of the thin-film transistor array base-plate Between, improve the manufacture efficiency of the thin-film transistor array base-plate.

With reference to figure 7, Fig. 7 is the flow chart of the preparation method of the polycrystalline silicon material of the present invention.

The preparation method of the polycrystalline silicon material of the present embodiment comprises the following steps:

Step 701, using ultraviolet light 201 irradiate amorphous silicon material so that silicon-hydrogen (Si-H) in the amorphous silicon material Key is broken, and irradiation time was first scheduled time.

Step 702, using infrared ray 301 to by the ultraviolet light 201 irradiation after the amorphous silicon material carry out Heating, so that the hydrogen (element) of the non-crystalline silicon molecule 1031 in the amorphous silicon material departs from (example from the amorphous silicon material Such as, the hydrogen in the amorphous silicon material is escaped in the form of hydrogen from the amorphous silicon material), the heat time is second predetermined Time.

Step 703, the amorphous silicon material after heating is cleaned.

Step 704, using laser by after cleaning the amorphous silicon material carry out annealing crystallization processing, to form polysilicon Material.Technology corresponding to this step is ELA (Excimer Laser Annealing, quasi-molecule laser annealing) technology.

In the present embodiment, first scheduled time is in the range of 20 seconds to 300 seconds (5 minutes), for example, described First scheduled time be 20 seconds, 25 seconds, 30 seconds, 35 seconds, 40 seconds, 45 seconds, 50 seconds, 55 seconds, 60 seconds, 65 seconds, 70 seconds, 75 seconds, 80 Second, 85 seconds, 90 seconds, 95 seconds, 100 seconds, 105 seconds, 110 seconds, 115 seconds, 120 seconds, 125 seconds, 130 seconds, 135 seconds, 140 seconds, 145 Second, 150 seconds, 155 seconds, 160 seconds, 165 seconds, 170 seconds, 175 seconds, 180 seconds, 185 seconds, 190 seconds, 195 seconds, 200 seconds, 205 seconds, 210 seconds, 215 seconds, 220 seconds, 225 seconds, 230 seconds, 235 seconds, 240 seconds, 245 seconds, 250 seconds, 255 seconds, 260 seconds, 265 seconds, 270 Second, 275 seconds, 280 seconds, 285 seconds, 290 seconds, 295 seconds, 300 seconds.

Preferably, first scheduled time is in the range of 1 minute to 2 minutes.

In the present embodiment, second scheduled time be in 1 minute to 20 minutes in the range of, for example, described second The scheduled time be 60 seconds, 75 seconds, 90 seconds, 105 seconds, 120 seconds, 135 seconds, 150 seconds, 165 seconds, 180 seconds, 195 seconds, 210 seconds, 225 Second, 240 seconds, 255 seconds, 270 seconds, 285 seconds, 300 seconds, 315 seconds, 330 seconds, 345 seconds, 360 seconds, 375 seconds, 390 seconds, 405 seconds, 420 seconds, 435 seconds, 450 seconds, 465 seconds, 480 seconds, 495 seconds, 510 seconds, 525 seconds, 540 seconds, 555 seconds, 570 seconds, 585 seconds, 600 Second, 615 seconds, 630 seconds, 645 seconds, 660 seconds, 675 seconds, 690 seconds, 705 seconds, 720 seconds, 735 seconds, 750 seconds, 765 seconds, 780 seconds, 795 seconds, 810 seconds, 825 seconds, 840 seconds, 855 seconds, 870 seconds, 885 seconds, 900 seconds, 915 seconds, 930 seconds, 945 seconds, 960 seconds, 975 Second, 990 seconds, 1005 seconds, 1020 seconds, 1035 seconds, 1050 seconds, 1065 seconds, 1080 seconds, 1095 seconds, 1110 seconds, 1125 seconds, 1140 Second, 1155 seconds, 1170 seconds, 1185 seconds, 1200 seconds.

Preferably, second scheduled time is in the range of 10 minutes to 15 minutes.

In the present embodiment, the temperature of the amorphous silicon material after the Infrared irradiation is in predetermined temperature model In enclosing, the predetermined temperature range is 300 degrees Celsius to 400 degrees Celsius, for example, the temperature is 300 degrees Celsius, 305 Celsius Degree, 310 degrees Celsius, 315 degrees Celsius, 320 degrees Celsius, 325 degrees Celsius, 330 degrees Celsius, 335 degrees Celsius, 340 degrees Celsius, 345 Degree Celsius, 350 degrees Celsius, 355 degrees Celsius, 360 degrees Celsius, 365 degrees Celsius, 370 degrees Celsius, 375 degrees Celsius, 380 degrees Celsius, 385 degrees Celsius, 390 degrees Celsius, 395 degrees Celsius, 400 degrees Celsius.

Preferably, the predetermined temperature range is 350 degrees Celsius to 400 degrees Celsius.

In the present embodiment, the hydrogen content in the amorphous silicon material after heating is less than or equal to 1.0%, i.e. Hydrogen (H) content in the polycrystalline silicon material is less than or equal to 1.0%, for example, the hydrogen content is 0.03%, 0.11%, 0.19%th, 0.27%, 0.35%, 0.43%, 0.51%, 0.59%, 0.67%, 0.75%, 0.83%, 0.91%, 1.0%.

Pass through above-mentioned technical proposal, the manufacturing cost and manufacturing time of the polycrystalline silicon material can be effectively reduced, improved The manufacture efficiency of the polycrystalline silicon material.

Although the present invention, those skilled in the art have shown and described relative to one or more implementations Based on the reading to the specification and drawings and understand it will be appreciated that equivalent variations and modification.The present invention includes all such repair Change and modification, and be limited only by the scope of the following claims.In particular, to the various functions performed by said modules, use Being intended to correspond to the specified function of performing the component in the term of component as description, (such as it is functionally of equal value ) random component (unless otherwise instructed), with performing the exemplary realization of this specification shown in this article in structure The open structure of function in mode is not equivalent.In addition, although the special characteristic of this specification is relative to some realization sides Only one in formula is disclosed, but this feature can with as can be it is expected and favorably for given or application-specific Other one or more combinations of features of other implementations.Moreover, with regard to term " comprising ", " having ", " containing " or its deformation For being used in embodiment or claim, such term is intended to the bag in a manner of similar to term "comprising" Include.

In summary, although the present invention is disclosed above with preferred embodiment, above preferred embodiment simultaneously is not used to limit The system present invention, one of ordinary skill in the art, without departing from the spirit and scope of the present invention, it can make various changes and profit Decorations, therefore protection scope of the present invention is defined by the scope that claim defines.

Claims (6)

1. a kind of preparation method of thin-film transistor array base-plate, it is characterised in that the described method comprises the following steps:
Cushion and amorphous silicon layer are set on substrate A, wherein, the cushion is located on the substrate, the amorphous silicon layer On the cushion, the amorphous silicon layer is the material layer formed by amorphous silicon material;
B, using amorphous silicon layer described in ultraviolet light, so that the silicon-hydrogen bond fracture in the amorphous silicon layer, irradiation time the One scheduled time;
C, the amorphous silicon layer after the ultraviolet light is heated using infrared ray, so that the non-crystalline silicon Hydrogen in layer departs from from the amorphous silicon layer, and the heat time was second scheduled time;
D, the amorphous silicon layer after heating is cleaned;
E, the amorphous silicon layer after cleaning is subjected to annealing crystallization processing using laser, to form polysilicon layer;And
F, display device is set on the polysilicon layer and/or on the cushion, to form thin-film transistor array base-plate, Wherein, the display device comprises at least signal wire, pixel electrode;
In the range of second scheduled time is in 1 minute to 20 minutes;
The temperature of the amorphous silicon layer after infrared ray irradiation is in predetermined temperature range, the predetermined temperature Scope is 300 degrees Celsius to 400 degrees Celsius.
2. the preparation method of thin-film transistor array base-plate according to claim 1, it is characterised in that described first is predetermined In the range of time is in 20 seconds to 300 seconds.
3. the preparation method of thin-film transistor array base-plate according to claim 1, it is characterised in that after heating Hydrogen content in the amorphous silicon layer is less than or equal to 1.0%.
4. a kind of preparation method of polycrystalline silicon material, it is characterised in that the described method comprises the following steps:
A, using ultraviolet light amorphous silicon material, so that the silicon-hydrogen bond fracture in the amorphous silicon material, irradiation time the One scheduled time;
B, the amorphous silicon material after the ultraviolet light is heated using infrared ray, so that the amorphous Hydrogen in silicon materials departs from from the amorphous silicon material, and the heat time was second scheduled time;
C, the amorphous silicon material after heating is cleaned;And
D, the amorphous silicon material after cleaning is subjected to annealing crystallization processing using laser, to form polycrystalline silicon material;
In the range of second scheduled time is in 1 minute to 20 minutes;
The temperature of the amorphous silicon layer after infrared ray irradiation is in predetermined temperature range, the predetermined temperature Scope is 300 degrees Celsius to 400 degrees Celsius.
5. the preparation method of polycrystalline silicon material according to claim 4, it is characterised in that first scheduled time is in In the range of 20 seconds to 300 seconds.
6. the preparation method of polycrystalline silicon material according to claim 4, it is characterised in that the amorphous after heating Hydrogen content in silicon layer is less than or equal to 1.0%.
CN201510521942.9A 2015-08-24 2015-08-24 The preparation method of thin-film transistor array base-plate and the preparation method of polycrystalline silicon material CN105140180B (en)

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CN106087040B (en) * 2016-07-14 2018-07-27 京东方科技集团股份有限公司 Multichip semiconductor crystallization system and the method that polycrystallization is carried out to single crystalline semiconductor substrate
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CN104465371A (en) * 2014-12-31 2015-03-25 深圳市华星光电技术有限公司 Excimer laser annealing pretreatment method, thin film transistor and production method of thin film transistor

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