CN106449732B - Thin film transistor, manufacturing method thereof and display panel - Google Patents

Thin film transistor, manufacturing method thereof and display panel Download PDF

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CN106449732B
CN106449732B CN201610967203.7A CN201610967203A CN106449732B CN 106449732 B CN106449732 B CN 106449732B CN 201610967203 A CN201610967203 A CN 201610967203A CN 106449732 B CN106449732 B CN 106449732B
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insulating layer
thin film
film transistor
active layer
region
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CN106449732A (en
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陆磊
王文
郭海成
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Abstract

A thin film transistor includes a substrate and an active layer made of metal oxide provided on the substrate, the active layer being adjacent to a gate stack; an electrode covers the partial area of the active layer; a first insulating layer is arranged between the electrode and the active layer; the electrode is covered with a second insulating layer; and the active layer forms a source region and a drain region respectively in the region covered by the second insulating layer, and forms a channel region in the region not covered by the second insulating layer. The invention also relates to a manufacturing method of the thin film transistor and a display panel with the thin film transistor. The thin film transistor not only has the small size of the traditional back channel etching structure transistor, but also has better performance than the traditional etching barrier layer structure transistor, including low source-drain parasitic resistance, better on-state and off-state performance and enhanced reliability. The display panel with the thin film transistor has the advantages of high performance, high reliability, low cost and the like, and is more in line with the development trend of display panels.

Description

Thin film transistor, manufacturing method thereof and display panel
Technical Field
The invention relates to a metal oxide thin film transistor structure and a manufacturing method thereof, in particular to a thin film transistor structure used in a display panel.
Background
Conventional metal oxide thin film transistors use metal as electrodes by depositing the metal on an active layer. Schottky barriers are generally formed at the contact interfaces of the electrodes and the active layer, so that the resistance values of the contact interfaces are high, thereby increasing the parasitic contact resistance of the thin film transistor, and meanwhile, the metal oxide semiconductor in an eigenstate is generally high in resistivity, which causes the problem of high-resistivity source-drain resistance. The existing solution is to lower the resistivity of the source and drain regions by doping them, but this usually comes at the expense of process stability and increased manufacturing costs. For example, the source and drain regions may be doped with hydrogen ions by plasma treatment, but the whole process is unstable. Other dopants, such as boron and phosphorus, require extremely expensive ion implantation equipment and additional activation processes. Therefore, there is a need in the thin film transistor manufacturing industry for a method with low cost and simple manufacturing process to reduce the resistivity of the metal oxide source/drain regions.
On the other hand, a back-channel etched BCE (back-channel etched BCE) structure and an etch-stop ES (etch-stop ES) structure are two main structure of the back-gate metal oxide thin film transistor. In the thin film transistor with the traditional back channel etching structure, an exposed upper channel interface can be damaged when an electrode is etched, and the performance of a device is further influenced. Although such damage can be avoided by adding an etching blocking layer on the channel region, this not only increases an additional photolithography process and thus increases the manufacturing cost, but also more importantly, the etching blocking layer device structure needs to extend the channel length and the length of the gate electrode, which enlarges the area of the thin film transistor and thus greatly limits the further improvement of the resolution of the display, and deviates from the high resolution development trend of the display. Summarizing, the device structure of the back channel etching has the advantages of providing a simple process, lower preparation cost and smaller device size, while the device structure of the etching barrier layer provides better device performance and improved device stability, but enlarges the device area and increases the manufacturing cost. Therefore, a new thin film transistor structure is urgently needed in the manufacturing industry of the metal oxide thin film transistor, and the new thin film transistor structure can simultaneously meet multiple requirements of low cost, high performance, small size and the like.
Disclosure of Invention
The present invention is to overcome the above-mentioned deficiencies in the prior art, and to provide a high performance metal oxide thin film transistor structure with low source/drain region resistivity and low manufacturing cost.
The invention provides a thin film transistor, comprising: a substrate and an active layer of metal oxide disposed on the substrate, the active layer being adjacent to a gate stack; an electrode covers the partial area of the active layer; a first insulating layer is further arranged between the electrode and the active layer, and the thickness of the first insulating layer is smaller than the diffusion length of the substance containing oxygen in the first insulating layer; a second insulating layer covers the electrode, and the thickness of the second insulating layer is larger than the diffusion length of the substance containing oxygen in the second insulating layer; the active layer forms a source region and a drain region in the region covered by the second insulating layer respectively, and forms a channel region in the region not covered by the second insulating layer; the source region, the drain region and the channel region are mutually connected and are respectively positioned at two ends of the channel region; the channel region is adjacent to the gate stack; the connection surfaces of the source region, the drain region and the channel region are self-aligned to the vertical plane of the boundary of the second insulating layer in the projection area of the active layer; the resistivity of the source region and the drain region is smaller than that of the channel region.
As a preferable mode of the transistor structure:
the distance between the connecting surfaces of the source region, the drain region and the channel region and the vertical plane of the boundary of the electrode in the projection area of the active layer is less than 100 times of the thickness of the active layer;
the resistivity ratio of the channel region to the source region to the drain region is greater than 1000 times.
The active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum indium tin zinc oxide.
The first insulating layer comprises a combination of one or more of the following materials: silicon oxide and silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. Wherein the first insulating layer has a thickness of 10 to 3000 nm.
The thickness of the second insulating layer is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second insulating layer.
The second insulating layer comprises a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide or hafnium oxide, wherein the proportion of silicon nitride in the silicon oxynitride is more than 20%. Wherein the thickness of the second insulating layer is 10 to 3000 nanometers.
The gate stack may be disposed between the active layer and the substrate; or,
the active layer is disposed between the gate stack and the substrate. Further, the gate stack includes a gate electrode and a gate insulating layer, the gate electrode has a thickness smaller than a diffusion length of the oxygen-containing substance in the gate electrode, and the gate insulating layer has a thickness smaller than the diffusion length of the oxygen-containing substance in the gate insulating layer. The gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide, indium zinc oxide; the gate insulating layer comprises a combination of one or more of the following materials: silicon oxide and silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The thickness of the gate electrode is 10 to 3000 nanometers; the thickness of the gate insulating layer is 10 to 3000 nanometers.
The elemental oxygen-containing species comprises: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and plasmas thereof.
The resistivity of the source region and the drain region is less than 10 ohm cm, and the resistivity of the channel region is greater than 10 ohm cm.
The invention also provides a display panel which comprises a plurality of groups of display modules, wherein the display modules comprise the thin film transistors.
The invention also provides a manufacturing method of the thin film transistor, which comprises the following steps:
preparing a substrate;
providing an active layer and a gate stack adjacent to the active layer over the substrate, the active layer being composed of a metal oxide;
covering an electrode on the active layer part area;
arranging a first insulating layer between the electrode and the active layer, wherein the thickness of the first insulating layer is smaller than the diffusion length of the substance containing oxygen in the first insulating layer;
covering a second insulating layer on the electrode, wherein the thickness of the second insulating layer is larger than the diffusion length of the substance containing oxygen in the second insulating layer;
and annealing, so that a source region and a drain region are respectively formed in the region of the active layer covered by the second insulating layer, a channel region is formed in the region not covered by the second insulating layer, the source region, the drain region and the channel region are mutually connected and are respectively positioned at two ends of the channel region, a connection surface is formed among the source region, the drain region and the channel region by annealing, the connection surface is self-aligned to a vertical plane of a boundary of the electrode in the projection area of the active layer, and the resistivity of the source region and the resistivity of the drain region are smaller than that of the channel region.
As a preferred embodiment of the above-described transistor manufacturing method of the present invention:
and the distance between the connection surface formed by annealing among the source region, the drain region and the channel region and the vertical plane of the boundary of the second insulating layer in the projection area of the active layer is less than 100 times of the thickness of the active layer.
The annealing includes heating with heat, light, laser, microwave.
The annealing is carried out in an oxidizing atmosphere for a time of 10 seconds to 10 hours at a temperature between 100 ℃ and 600 ℃.
The oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide, and plasmas thereof.
According to the method, the invention also provides a display panel which comprises a plurality of groups of display modules, and the display modules comprise the thin film transistors manufactured by the method.
Compared with the traditional thin film transistor structure, the invention has the following advantages: firstly, according to the scheme, the source region and the drain region are formed in the active layer directly through annealing, the size of the device which is the same as that of the back channel etching structure is kept, and the high performance of the device with the etching barrier layer structure is realized. Meanwhile, the advantages of high performance and small size are considered, and the display device well accords with the development trend of the current display, particularly the development and application in the aspects of augmented reality and virtual reality. And secondly, the resistivity of the source-drain region is reduced by annealing, so that the parasitic contact resistance between the electrode and the active layer is reduced, and the on-state performance of the thin film transistor is remarkably improved. Meanwhile, the high resistivity of the channel region is maintained or even improved due to the annealing, so that the off-state current of the thin film transistor is remarkably reduced. More importantly, the annealing can eliminate the defect density in the channel region to a great extent, and the reliability of the device is greatly improved. The first insulating layer above the channel region protects the channel region of the thin film transistor from the external environment, and the environmental reliability of the device is further enhanced. According to the invention, the second insulating layer on the electrode directly covers part of the active layer region, and the resistivity of the source region and the drain region covered by the second insulating layer is reduced through annealing, so that the doping step and the photoetching step in the traditional semiconductor process are omitted, the preparation cost is saved, and the stability of the low resistivity of the source region and the drain region is ensured. Therefore, the invention has the advantages of high performance, small size, high reliability, low cost and the like.
Drawings
Fig. 1 is a sectional view of a back gate thin film transistor with a conventional back channel etching structure.
Fig. 2 is a cross-sectional view of a back gate thin film transistor with a conventional etch barrier structure.
Fig. 3 is a cross-sectional view of a first embodiment of a tft structure of the present invention.
Fig. 4 is a cross-sectional view of a second embodiment of a tft structure of the present invention.
Fig. 5 is a cross-sectional view of a third embodiment of a thin film transistor structure in accordance with the present invention.
FIG. 6 is a diagram of a first display module structure of a display panel according to the present invention.
FIG. 7 is a diagram of a second display module structure of the display panel according to the present invention.
FIG. 8 is a diagram of a third display module structure in a display panel according to the present invention.
Detailed Description
Referring to fig. 1, fig. 1 is a cross-sectional view of a back gate thin film transistor with a conventional back channel etching structure. Wherein, the thin film transistor includes: a substrate 1a, an active layer 2a disposed on the substrate 1 a. A gate stack 3a is further disposed between the active layer 2a and the substrate 1a, the gate stack 3a including a gate electrode 31a and a gate insulating layer 32a disposed between the gate electrode 31a and the active layer 2 a. The active layer 2a is covered with an electrode 4 a. The regions of the active layer 2a in contact with the electrode 4a form source and drain regions 21a and 23a, respectively, and the regions of the active layer 2a in contact with the non-electrode 4a form a channel region 22 a. Wherein the channel region 22a is adjacent to the gate stack 3a, and the source region 21a and the drain region 23a are respectively located at two ends of the channel region 22a and connected to the channel region 22 a. In the working process of the thin film transistor, the resistivity of the channel region can be changed by applying a certain voltage to the gate electrode, so that the current passing through the channel region is controlled, and the switching of the thin film transistor is realized. The off-state current of a thin film transistor depends largely on the resistivity and defect density of the channel region, and higher resistivity and less defect density may lead to lower off-state current and better device performance. The on-state current of the thin film transistor is limited by the resistivity of the source region and the drain region, and the lower resistivity of the source region and the drain region is beneficial to reducing parasitic resistance and improving the on-state current. For the back gate thin film transistor with the back channel etching structure, the channel region 22a of the back gate thin film transistor is damaged in the process of etching the electrode 4a, so that a large amount of defect density is generated, and the performance of the device is greatly reduced. The resulting defect density includes a conductivity type defect density that reduces the resistivity of the channel region 22a, thereby greatly increasing the off-state current of the thin film transistor operating current. Another problem is that the source and drain regions 21a and 23a of intrinsically high resistivity also reduce the on-state current of the thin film transistor.
Referring to fig. 2, fig. 2 is a cross-sectional view of a back gate thin film transistor with a conventional etch barrier structure. Wherein, the thin film transistor includes: a substrate 1b, an active layer 2b disposed on the substrate 1 b. A gate stack 3b is also provided between the active layer 2b and the substrate 1 b. The gate stack 3b includes a gate electrode 31b and a gate insulating layer 32b disposed between the gate electrode 31b and the active layer 2 b. An etch stopper layer 5 is provided on the active layer 2 b. The etch stop layer 5 and the active layer 2b are covered with an electrode 4 b. The regions of the active layer 2b in contact with the electrode 4b form source and drain regions 21b and 23b, respectively, and the regions of the active layer 2b in contact with the non-electrode 4b form a channel region 22 b. Wherein the channel region 22b is adjacent to the gate stack 3b and the source region 21b and the drain region 23b are located at two ends of the channel region 22b and connected to the channel region 22 b. The channel region 22b can be protected from damage caused by the electrode 4b etching process by etching the barrier layer 5, thereby avoiding the introduction of defect density and lowering resistivity in the channel region 22 b. However, due to the introduction of the etch stop layer 5, the channel region 2b2 and the gate electrode 31b are correspondingly elongated to ensure that the channel region 22b can still be connected to the source region 21b, the drain region 23b and the electrode 4 b. Therefore, the area of the thin film transistor is greatly increased, and the trend of miniaturization of the thin film transistor is deviated. Meanwhile, since an additional photolithography step is required to pattern the etching stopper layer 5, the manufacturing cost is also increased. Similarly, the source region 21b and the drain region 23b with intrinsic high resistivity in the thin film transistor with the etching barrier layer structure can reduce the on-state current of the thin film transistor, and the device performance is affected.
The present invention will be described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are non-limiting exemplary embodiments and that the features illustrated in the drawings are not necessarily drawn to scale. The examples given are only intended to facilitate the explanation of the invention and should not be understood as a limitation of the invention.
Referring to fig. 3, fig. 3 is a cross-sectional view of a first embodiment of a thin film transistor structure according to the present invention. The thin film transistor in this embodiment adopts a back gate structure. Wherein, the thin film transistor includes: an active layer 2 disposed on a substrate 1; a gate stack 3 is further disposed between the active layer 2 and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; a first insulating layer 6 covers the active layer 2, through holes reaching the active layer 2 are formed in the first insulating layer 6, conductors are deposited in the through holes, and therefore the electrodes 4 are led out of the through holes, and the electrodes 4 are respectively electrically connected with partial regions of the active layer 2; a second insulating layer 7 is provided over the electrode 4 and the first insulating layer 6.
Referring to fig. 3, the substrate 1 includes, but is not limited to, the following materials: glass, polymer substrates, flexible materials, and the like.
Referring to fig. 3, the active layer 2 includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum indium tin zinc oxide, zinc sulfide, barium titanate, strontium titanate, or lithium niobate.
In the invention, when the thickness of the insulating layer or the conductor layer is less than the diffusion length of the substance containing the oxygen element in the insulating layer or the conductor layer, the substance containing the oxygen element can penetrate through the insulating layer or the conductor layer into the metal oxide active layer in the annealing treatment so as to maintain or even improve the resistivity of the metal oxide, and the insulating layer or the conductor layer is an oxygen permeable layer; when the thickness of one insulating layer or conductor layer is larger than the diffusion length of the substance containing oxygen in the insulating layer, the insulating layer or conductor layer can block the substance containing oxygen, thereby reducing the resistivity of the metal oxide, and the insulating layer or conductor layer is an oxygen-impermeable layer.
The elemental oxygen-containing species comprises: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and plasmas thereof.
Referring to fig. 3, the thickness of the first insulating layer 6 is smaller than the diffusion length of the oxygen-containing substance in the first insulating layer 6, which is able to penetrate the first insulating layer 6 in the annealing treatment, so the first insulating layer 6 is an oxygen permeable layer. The first insulating layer 6 comprises one or a combination of more of the following materials: silicon oxide, silicon oxynitride; wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%. The thickness of the first oxygen permeable layer 6 is 10 to 3000 nm. Preferably, the thickness of the first insulating layer 6 is between 200 nm and 500 nm.
Referring to fig. 3, the thickness of the second insulating layer 7 is greater than the diffusion length of the oxygen-containing substance in the second insulating layer 7, and the second insulating layer 7 can block the oxygen-containing substance, so that the second insulating layer 7 is an oxygen-impermeable layer. Preferably, the thickness of the second insulating layer 7 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second insulating layer 7. The second insulating layer 7 comprises one or a combination of the following materials: silicon nitride, silicon oxynitride, aluminum oxide or hafnium oxide, wherein the proportion of silicon nitride in the silicon oxynitride is more than 20%. The thickness of the second insulating layer 7 is 10 to 3000 nm. Preferably, the thickness of the second insulating layer 7 is between 200 nm and 500 nm.
Referring to fig. 3, in the annealing process, the second insulating layer 7 blocks the oxygen-containing substance, and the resistivity of the region of the active layer 2 covered by the second insulating layer 7 is lowered to form the source region 21 and the drain region 23. The reduced resistivity of the source region 21 and the drain region 23 is beneficial to reducing the contact resistance between the source region 21 and the drain region 23 and the electrode 4, thereby improving the on-state performance of the thin film transistor. Contrary to the properties of the second insulating layer 7, in the annealing treatment, the oxygen-containing substance can enter the active layer 2 through the first insulating layer 6, and thus the resistivity of the region of the active layer 2 not covered by the second insulating layer 7 is maintained or even increased, forming the channel region 22. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, and thus improve the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also protect the channel region 22 from the external environment, thereby improving the stability and reliability of the thin film transistor.
Referring to fig. 3, the resistivity of the source and drain regions 21, 23 is reduced by covering the second insulating layer 7 over a portion of the active layer 2, followed by an annealing process, while maintaining or even increasing the high resistivity of the channel region 22. The source region 21, the drain region 23, and the channel region 22 in the active layer 2 are connected to each other. The connection surface formed by annealing is automatically aligned to the boundary of the second insulating layer 7 covering the active layer 2 without any photoetching alignment process, which is similar to the connection surface of the doped source region, drain region and channel region automatically aligned to the boundary of the gate electrode in the existing silicon-based field effect transistor process. Such self-alignment typically has a range of variation. In the invention, the connection surfaces of the source region, the drain region and the channel region are self-aligned to the vertical plane of the boundary of the second insulating layer in the projection area of the active layer, and the alignment deviation is less than 100 times of the thickness of the active layer.
In the present invention, the projected area is a projected area in a vertical direction shown in the drawings in the specific embodiment.
In the present invention, the annealing treatment includes, but is not limited to, heating using heat, light, laser, microwave. The annealing treatment is carried out in an oxidizing atmosphere for a time of 10 seconds to 10 hours at a temperature of between 100 ℃ and 600 ℃. The oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide, and plasmas thereof.
Compared with the traditional method of doping the source region and the drain region to reduce the resistivity of the source region and the drain region, the method has the advantages that the resistivity of the source region and the drain region obtained by annealing is lower than that obtained by doping, and the resistivity of the source region and the drain region under the protection of the second insulating layer is more stable. Compared with the traditional doping mode, the method has the advantages of simpler process and lower cost. The present invention is not limited to doping, and one or more of the following impurities may be doped in the active layer 2: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminum, or antimony. This does not interfere with the formation of the source, channel and drain regions of the device. Therefore, the scheme is completely compatible with the existing doping process and has high expandability.
Compared with the traditional thin film transistor method, the annealing treatment in the invention also ensures and even improves the high resistivity of the channel region, thereby greatly reducing the off-state current of the thin film transistor, which is far lower than 10 of the current mainstream-13Ampere per micron, even down to a very low 10-18Ampere per micron. More importantly, annealing also largely eliminates defect densities in the channel region, such as oxygen vacancy defect densities, metal interstitial defect densities, and the like, which are widely present in metal oxides and are believed to be important factors in reducing the performance and reliability of thin film transistors, but are difficult to completely eliminate in conventional device structures. Because these defect densities are eliminated, the thin film transistor structure disclosed in the present invention greatly enhances the performance and long-term reliability of the thin film transistor. For example, the current switching ratio of the metal oxide thin film transistor is greatly improved and even higher than 1011(ii) a The threshold voltage drift caused by common hysteresis effect is suppressed to be within 0.15V; the drift degradation of the threshold voltage generated when a constant voltage is applied to the gate electrode is eliminated to about 0V. And secondly, the first insulating layer covered above the channel region can completely protect the channel region from being damaged by electrode etching like an etching barrier layer, and can well protect the thin film transistor from being influenced by the external environment and enhance the environmental stability of the thin film transistor. For example, the performance degradation such as threshold voltage shift caused by storage at 80 degrees centigrade and 80% relative humidity for 10 hours can be greatly improved by the thin film transistor structure of the present invention.
In summary, the present invention has a number of advantages over conventional thin film transistor structures, including: the method has the advantages of simpler manufacturing process, lower preparation cost, higher process expansibility, better device performance, reliability and environmental stability.
Referring to fig. 4, fig. 4 is a cross-sectional view of a second embodiment of a tft structure of the present invention. In this embodiment, the thin film transistor has a top gate structure. Also, the thin film transistor includes: a substrate 1; an active layer 2 disposed on a substrate 1; an oxygen-permeable gate electrode 311 and an oxygen-permeable gate insulating layer 321 arranged between the oxygen-permeable gate electrode 311 and the active layer 2 are arranged on the active layer 2; the active layer 2, the oxygen permeable gate insulating layer 321 and the oxygen permeable gate electrode 311 are covered with a first insulating layer 6, a through hole reaching the active layer 2 is formed in the first insulating layer 6, a conductor is deposited in the through hole, so that the electrode 4 is led out from the through hole, and the electrode 4 is respectively and electrically connected with partial regions of the active layer 2. A second insulating layer 7 is also provided over the electrode 4 and the first insulating layer 6.
Referring to fig. 4, the thickness of the oxygen-permeable gate electrode 311 is smaller than the diffusion length of the oxygen-containing substance in the gate electrode 31, the oxygen-containing substance being able to permeate through the oxygen-permeable gate electrode 311 in the annealing treatment, so that the oxygen-permeable gate electrode 311 is an oxygen-permeable layer; the oxygen permeable gate electrode 311 comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide, or indium zinc oxide; the oxygen permeable gate electrode 311 has a thickness of 10 to 3000 nanometers. Preferably, the oxygen permeable gate electrode 311 is between 200 nanometers and 500 nanometers thick.
Referring to fig. 4, the thickness of the oxygen-permeable gate insulating layer 321 is less than the diffusion length of the oxygen-containing substance in the oxygen-permeable gate insulating layer 321; the oxygen-containing substance is able to permeate through the oxygen-permeable gate insulating layer 321 during the annealing treatment, so the oxygen-permeable gate insulating layer 321 is an oxygen-permeable layer; the oxygen permeable gate insulating layer 321 comprises a combination of one or more of the following materials: silicon oxide and silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20 percent; the oxygen permeable gate insulating layer 321 has a thickness of 10 to 3000 nanometers. Preferably, the oxygen permeable gate insulating layer 321 has a thickness between 200 nanometers and 500 nanometers.
Referring to fig. 4, in the annealing process, the second insulating layer 7 blocks the oxygen-containing substance, and the resistivity of the region of the active layer 2 covered by the second insulating layer 7 is lowered to form the source region 21 and the drain region 23. The reduced resistivity of the source region 21 and the drain region 23 is beneficial to reducing the contact resistance between the source region 21 and the drain region 23 and the electrode 4, thereby improving the on-state performance of the thin film transistor. Contrary to the properties of the second insulating layer 7, the first insulating layer 6, the oxygen permeable gate electrode 311 and the oxygen permeable gate insulating layer 321 are oxygen permeable layers. In the annealing process, the oxygen-containing substance can enter the active layer 2 through the first insulating layer 6, the oxygen-permeable gate electrode 311 and the oxygen-permeable gate insulating layer 321, so that the resistivity of the region of the active layer 2 not covered by the second insulating layer 7 is maintained or even increased, and the channel region 22 is formed. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, and thus improve the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also protect the channel region 22 from the external environment, thereby improving the stability and reliability of the thin film transistor.
Referring to fig. 5, fig. 5 is a cross-sectional view of a third embodiment of a thin film transistor structure according to the present invention. The thin film transistor in this embodiment adopts a back gate structure. Wherein, the thin film transistor includes: a substrate 1; an active layer 2 disposed on a substrate 1; a gate stack 3 is further disposed between the active layer 2 and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer 2; a first insulating layer 6 covers the active layer 2, a through hole reaching the active layer 2 is formed in the first insulating layer 6, a conductor is deposited in the through hole, and therefore the electrode 4 is led out of the through hole, and the electrode 4 is respectively and electrically connected with partial areas of the active layer 2; a second insulating layer 7 is provided over the electrode 4 and the first insulating layer 6. In the present embodiment, the projected area of the second insulating layer 7 completely overlaps the projected area of the electrode 4.
Referring to fig. 5, in the annealing process, the electrode 4 and the second insulating layer 7 block the oxygen-containing substance together, the resistivity of the region of the active layer 2 under the coverage of the electrode 4 and the second insulating layer 7 together is lowered, and the source region 21 and the drain region 23 are formed. The reduced resistivity of the source region 21 and the drain region 23 is beneficial to reducing the contact resistance between the source region 21 and the drain region 23 and the electrode 4, thereby improving the on-state performance of the thin film transistor. Contrary to the properties of the second insulating layer 7, in the annealing process, the oxygen-containing substance is able to penetrate through the first insulating layer 6 into the active layer 2, and thus the resistivity of the region of the active layer 2 under the common coverage of the non-electrode 4 and the second insulating layer 7 is maintained or even increased, forming the channel region 22. The first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, and thus improve the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also protect the channel region 22 from the external environment, thereby improving the stability and reliability of the thin film transistor.
Referring to fig. 6, fig. 6 is a schematic diagram of a first display module structure in a display panel according to the present invention, wherein the display panel is composed of a plurality of display modules. The display module comprises a thin film transistor, an intermediate insulating layer 8, a pixel electrode 9, an electro-optic material 10 and a common electrode 11. The pixel electrode 9 is electrically connected to the electrode 4 of the thin film transistor through a via hole in the intermediate insulating layer 8. Photovoltaic material 10 includes, but is not limited to: liquid crystal, light emitting diode, organic light emitting diode, quantum dot light emitting diode. In the display panel of this embodiment, the thin film transistor is the thin film transistor shown in fig. 3. Such a thin film transistor can also be used to constitute a circuit such as a driver circuit in a display panel.
Referring to fig. 7, fig. 7 is a schematic diagram of a second display module structure in a display panel according to the present invention, wherein the display panel is composed of a plurality of display modules. The display module comprises a thin film transistor, an intermediate insulating layer 8, a pixel electrode 9, an electro-optic material 10 and a common electrode 11. The pixel electrode 9 is electrically connected to the electrode 4 of the thin film transistor through a via hole in the intermediate insulating layer 8. In the display panel of this embodiment, the thin film transistor is the thin film transistor shown in fig. 5. Such a thin film transistor can also be used to constitute a circuit such as a driver circuit in a display panel.
Referring to fig. 8, fig. 8 is a schematic diagram of a third structure of a display module in a display panel according to the present invention, wherein the display panel is composed of a plurality of display modules. The display module includes a thin film transistor, a pixel electrode 9, a photoelectric material 10, and a common electrode 11. The pixel electrode 9 is electrically connected with the electrode 4 of the thin film transistor through a through hole on the second insulating layer 7, and the second insulating layer 7 also has the function of an intermediate insulating layer, so that a special intermediate insulating layer is not required to be arranged. In the display panel of this embodiment, the thin film transistor is the thin film transistor shown in fig. 3.
It should be understood that the above-mentioned embodiments are merely preferred embodiments of the present invention, and not restrictive, and that any modifications, equivalents or improvements made within the spirit and principle of the present invention should be understood by those skilled in the art to be included in the scope of the present invention.

Claims (23)

1. A thin film transistor, comprising: a substrate and an active layer of metal oxide disposed on the substrate, the active layer being adjacent to a gate stack; an electrode covers the partial area of the active layer; a first insulating layer is further arranged between the electrode and the active layer, the thickness of the first insulating layer is smaller than the diffusion length of the substance containing oxygen in the first insulating layer, a through hole reaching the active layer is formed in the first insulating layer, a conductor is deposited in the through hole, and therefore the electrode is led out from the through hole and is respectively electrically connected with partial regions of the active layer; the electrode is covered with a second insulating layer, the second insulating layer is positioned above the electrode and the first insulating layer and is an oxygen-impermeable layer, and the thickness of the second insulating layer is greater than the diffusion length of the substance containing oxygen in the second insulating layer so as to block the substance containing oxygen; after annealing treatment, the resistivity of the area of the active layer covered by the second insulating layer is reduced, a source area and a drain area are respectively formed, and a channel area is formed in the area not covered by the second insulating layer; the source region, the drain region and the channel region are mutually connected and respectively positioned at two ends of the channel region; the connection surface formed by annealing the source region, the drain region and the channel region is self-aligned to the vertical surface of the boundary of the second insulating layer in the projection area of the active layer; the resistivity of the source region and the drain region is smaller than that of the channel region.
2. The thin film transistor of claim 1, wherein the junction faces of the source, drain and channel regions and the vertical plane of the boundary of the electrode within the projected area of the active layer have a spacing of less than 100 times the thickness of the active layer.
3. The thin film transistor of claim 1, wherein a ratio of a resistivity of the channel region to the source region and the drain region is greater than 1000 times.
4. The thin film transistor of claim 1, wherein the active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, bismuth oxide, indium zinc oxide, zinc tin oxide, aluminum tin oxide, indium gallium zinc oxide, indium tin zinc oxide, aluminum indium tin zinc oxide.
5. The thin film transistor of claim 1, wherein the first insulating layer comprises a combination of one or more of the following materials: silicon oxide and silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
6. The thin film transistor according to claim 5, wherein a thickness of the first insulating layer is 10 to 3000 nm.
7. The thin film transistor according to claim 1, wherein a thickness of the second insulating layer is between 2 and 100 times a diffusion length of the oxygen-containing substance in the second insulating layer.
8. The thin film transistor of claim 1, wherein the second insulating layer comprises a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, or hafnium oxide; wherein the proportion of silicon nitride in the silicon oxynitride is more than 20%.
9. The thin film transistor according to claim 8, wherein a thickness of the second insulating layer is 10 to 3000 nm.
10. The thin film transistor of claim 1, wherein the gate stack is disposed between the active layer and the substrate.
11. The thin film transistor of claim 1, wherein the active layer is disposed between the gate stack and the substrate.
12. The thin film transistor of claim 11, wherein the gate stack comprises a gate electrode and a gate insulating layer, wherein the gate electrode has a thickness less than a diffusion length of the oxygen-containing species in the gate electrode, and wherein the gate insulating layer has a thickness less than the diffusion length of the oxygen-containing species in the gate insulating layer.
13. The thin film transistor of claim 12, wherein the gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide, or indium zinc oxide; the gate insulating layer comprises a combination of one or more of the following materials: silicon oxide and silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
14. The thin film transistor of claim 13, wherein the gate electrode has a thickness of 10 to 3000 nm; the thickness of the gate insulating layer is 10 to 3000 nanometers.
15. The thin film transistor according to claim 1, wherein the oxygen-containing substance comprises: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and plasmas thereof.
16. The thin film transistor of claim 1, wherein the source and drain regions have a resistivity of less than 10 ohm cm and the channel region has a resistivity of greater than 10 ohm cm.
17. A display panel comprising a plurality of groups of display modules, wherein the display modules comprise the thin film transistors of any one of claims 1 to 16.
18. A method of manufacturing a thin film transistor, comprising:
preparing a substrate;
providing an active layer and a gate stack adjacent to the active layer over the substrate, the active layer being composed of a metal oxide;
covering an electrode on the active layer part area;
arranging a first insulating layer between the electrode and the active layer, wherein the thickness of the first insulating layer is smaller than the diffusion length of the substance containing oxygen in the first insulating layer;
covering a second insulating layer on the electrode, wherein the thickness of the second insulating layer is larger than the diffusion length of the substance containing oxygen in the second insulating layer; a through hole reaching the active layer is formed on the first insulating layer, a conductor is deposited in the through hole, so that electrodes are led out from the through hole and are respectively and electrically connected with partial regions of the active layer;
and annealing to reduce the resistivity of the active layer in the region covered by the second insulating layer to form a source region and a drain region respectively, forming a channel region in the region not covered by the second insulating layer, wherein the source region, the drain region and the channel region are connected with each other and are positioned at two ends of the channel region respectively, and annealing to form a connection surface among the source region, the drain region and the channel region, the connection surface is self-aligned to a vertical plane of a boundary of the electrode in the projection area of the active layer, the resistivity of the source region and the resistivity of the drain region are reduced by annealing, and the resistivity of the source region and the resistivity of the drain region are smaller than the resistivity of the channel region.
19. The method for manufacturing a thin film transistor according to claim 18, wherein a pitch of vertical planes of boundaries of the connection faces between the source region, the drain region, and the channel region formed by annealing and the second insulating layer within a projected area of the active layer is less than 100 times a thickness of the active layer.
20. The method for manufacturing a thin film transistor according to claim 18, wherein the annealing treatment includes heating by heat, light, laser, or microwave.
21. The method for manufacturing a thin film transistor according to claim 18, wherein the annealing treatment is performed in an oxidizing atmosphere at a temperature between 100 ℃ and 600 ℃ for 10 seconds to 10 hours.
22. The method for manufacturing a thin film transistor according to claim 21, wherein the oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide, and plasmas thereof.
23. A display panel comprising a plurality of groups of display modules, wherein the display modules comprise thin film transistors fabricated by the method of any one of claims 18 to 22.
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