WO2017071658A1 - Structure de circuit constituée de transistors à couche mince et son procédé de fabrication, et panneau d'affichage - Google Patents

Structure de circuit constituée de transistors à couche mince et son procédé de fabrication, et panneau d'affichage Download PDF

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Publication number
WO2017071658A1
WO2017071658A1 PCT/CN2016/103831 CN2016103831W WO2017071658A1 WO 2017071658 A1 WO2017071658 A1 WO 2017071658A1 CN 2016103831 W CN2016103831 W CN 2016103831W WO 2017071658 A1 WO2017071658 A1 WO 2017071658A1
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channel region
layer
thin film
region
film transistor
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PCT/CN2016/103831
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Chinese (zh)
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陆磊
王文
郭海成
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陆磊
王文
郭海成
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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Definitions

  • the present invention relates to a circuit structure and a manufacturing method composed of a metal oxide thin film transistor, particularly a circuit used in a module of a display panel.
  • the performance of a thin film transistor directly affects the performance of the display.
  • thin film transistors composed of metal oxide active layers have many advantages, such as low temperature process, high transparency, high mobility, low leakage, etc., which are considered to be silicon-based devices in display panels. The most promising replacement.
  • conventional metal oxide thin film transistors have significant deficiencies in manufacturing processes, device structures, and circuit applications.
  • a conventional metal oxide thin film transistor is used as an electrode by depositing a metal on an active layer.
  • a Schottky barrier is usually formed at the contact interface between the electrode and the active layer, resulting in a high contact resistance between the oxide and the metal interface, and the eigenstate metal oxide semiconductor is usually high resistivity, which is carried
  • the problem of high source-drain parasitic resistance is to reduce the resistivity of the source and drain regions by making the source and drain regions cumbersome, but this is usually at the expense of process stability and increased manufacturing costs.
  • the source and drain regions can be mischarged into the source and drain regions by plasma treatment, but the effects are not stable.
  • Other filths, such as boron and phosphorus require extremely expensive ion implantation equipment and additional activation processes. For this reason, there is an urgent need in the thin film transistor manufacturing industry for a low cost, simple manufacturing process to reduce the resistivity of the metal oxide source and drain regions, thereby improving device performance.
  • the back channel etch structure and the etch barrier structure are two main structures of the back gate metal oxide thin film transistor.
  • the exposed interface on the channel is damaged at the time of etching the electrode, thereby affecting the performance of the device.
  • the etch barrier device structure needs to be extended. The length of the channel and the length of the gate electrode, which enlarges the area of the thin film transistor, thereby greatly limiting the display
  • the further increase in resolution deviates from the high resolution trend of the display.
  • the advantages of the back-channel etched device structure are that it provides a simple process, lower fabrication cost, and smaller device size, while the device structure of the etch barrier provides better device performance and Improved device stability, but increases the area of the device and increases manufacturing costs. For this reason, the metal oxide thin film transistor manufacturing industry urgently needs a novel thin film transistor structure, which can meet the multiple requirements of low cost, high performance, small size, and the like.
  • metal oxide thin film transistors also have a significant defect density compared to conventional silicon-based thin film transistors. Although the performance of metal oxide thin film transistors has been significantly improved over the years, the thin film transistor process and structure of the present invention can be further improved. However, current mainstream metal oxide thin film transistors are also n-type thin film transistors, and p-type metal oxide thin film transistors with excellent performance are still difficult to implement. Further improvements in power consumption and other performance parameters of the circuit can no longer rely solely on the performance improvement of the thin film transistor itself, but also require an active "pull-up" device.
  • this active "pull-up” device is a p-type thin film transistor, but for metal oxide thin film transistors the situation is completely different. Since circuits composed of metal oxide thin film transistors can only be based on n-type devices, it is difficult to prepare high-performance circuits in a complementary manner to n-type and p-type thin film transistors like silicon-based devices. In order to achieve a relatively good performance circuit, a widely used alternative is to use a depletion type n-type metal oxide thin film transistor as an active "pull-up" device, and an enhanced n-type thin film transistor as an active "pull-down". Device. Wherein, the threshold voltage of the depletion thin film transistor is lower than the threshold voltage of the enhancement type thin film transistor.
  • the method for realizing the monolithic integration of the depletion mode and the enhancement type thin film transistor mainly includes: adjusting the material composition of the metal oxide active layer, adjusting the thickness of the active layer, using an active layer of a multilayer structure, or the like.
  • the above method is very limited in adjusting the threshold voltage of the thin film transistor, and the process is complicated, and the device performance is severely limited by the preparation process.
  • Another way to adjust the threshold voltage to form depletion mode and enhancement thin film transistors is by introducing an additional gate stack to form a double gate structure.
  • the additional gate stack is specifically responsible for adjusting the threshold voltage of the thin film transistor, so the adjustment range is larger.
  • this additional gate stack requires additional control circuitry, which greatly increases the complexity and cost of the fabrication circuitry, and is not compatible with existing device architectures, deviating from the current high resolution trends in display panels.
  • display panel manufacturing urgently needs a new The method of adjusting the threshold voltage of the metal oxide thin film transistor can increase the modulation range of the threshold voltage of the device under the premise of ensuring the high performance index of the thin film transistor, and maintain the simple and easy-to-cost manufacturing process.
  • the technical problem to be solved by the present invention is to overcome the above-mentioned deficiencies of the prior art, and provide a circuit structure for effectively adjusting a threshold voltage of a metal oxide thin film transistor, an integrated enhancement thin film transistor and a depletion thin film transistor, Increasing the modulation range of the threshold voltage of the thin film transistor also maintains the high performance of the thin film transistor, simplifies the existing manufacturing process, and reduces the manufacturing cost, and can be effectively applied to an integrated circuit, particularly a circuit in a display panel. .
  • the present invention provides a thin film transistor circuit structure, the structure of the thin film transistor includes: a substrate and an active layer made of a metal oxide on the substrate; the active layer and the gate a portion of the active layer is covered with a first conditioning layer, the first conditioning layer having a thickness greater than a diffusion length of the oxygen-containing material in the first conditioning layer; Forming a source region and a drain region in a region covered by the first adjustment layer, and forming a channel region in a region not covered by the first adjustment layer; the source region, the drain region, and the The channel regions are connected to each other and are respectively located at two ends of the channel region, the channel region is adjacent to the gate stack; the source region, the drain region and the channel region
  • the connection surface is self-aligned with a vertical surface of a boundary of the first adjustment layer within a projected area of the active layer; the resistivity of the source region and the drain region is smaller than a resistivity of the channel region a second adjustment layer is disposed over the entire channel region of the partial thin film
  • a depletion mode channel region under the cover of the second adjustment layer Forming a depletion mode channel region under the cover of the second adjustment layer, forming an enhancement channel region under the cover of the second adjustment layer, the depletion mode channel region having a resistivity less than a resistivity of the enhanced channel region; a thickness of the second conditioning layer being greater than a diffusion length of the oxygen-containing material in the second conditioning layer; and a thin film transistor having the depletion channel region
  • a depletion thin film transistor, the thin film transistor having the enhanced channel region is an enhancement thin film transistor; and the depletion thin film transistor and the enhancement thin film transistor are electrically connected to each other to constitute a circuit.
  • a preferred method as the above circuit structure [0010] a distance between a connection surface of the source region, the drain region and the channel region, and a vertical plane of a boundary of the first adjustment layer within a projected area of the active layer is smaller than the 100 times the thickness of the source layer.
  • a ratio of resistivity of the channel region to the source region and the drain region is greater than 1000 times; a resistivity of the enhanced channel region is 2 of a resistivity of the depletion channel region Up to 100 times.
  • the active layer comprises a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide
  • the thickness of the first adjustment layer is between 2 and 100 times the diffusion length of the oxygen-containing substance in the first adjustment layer
  • the thickness of the second adjustment layer is the The substance of the oxygen element is between 2 and 100 times the diffusion length in the second conditioning layer.
  • the first conditioning layer and the second conditioning layer comprise a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, silicon, gallium arsenide, titanium , molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy; wherein, the nitridation in the silicon oxynitride The silicon ratio is greater than 20%.
  • the first conditioning layer has a thickness of 10 to 3000 nm
  • the second conditioning layer has a thickness of 10 to 3000 nm.
  • the gate stack may be disposed between the active layer and the substrate;
  • the active layer is disposed between the gate stack and the substrate.
  • the gate stack includes a gate electrode and a gate insulating layer, the gate electrode has a thickness smaller than a diffusion length of the oxygen-containing material in the gate electrode, and the gate insulating layer The thickness of the layer is less than the diffusion length of the oxygen-containing material in the gate insulating layer.
  • the gate electrode comprises a combination of one or more of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium aluminum oxide or indium zinc oxide; the gate insulating layer comprises one of the following materials Or a combination of a plurality of: silicon oxide, silicon oxynitride, wherein the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the gate electrode has a thickness of 10 to 3000 nm; and the gate insulating layer has a thickness of 10 to 3000 nm.
  • the oxygen element-containing substance includes: plasma of oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and the like.
  • the present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the circuit structure described above.
  • the present invention further provides another display panel, including a plurality of sets of display modules, the display module includes: a thin film transistor, an intermediate insulating layer, and a pixel electrode; the thin film transistor is electrically connected to the pixel electrode, The intermediate insulating layer is located between the thin film transistor and the pixel electrode, the projected area of the second adjusting layer and the projected area of the intermediate insulating layer completely overlap, and the thin film transistors are electrically connected to each other to form a pixel circuit and display
  • the driving circuit, the structure of the pixel circuit and the display driving circuit include the circuit structure described above.
  • the present invention further provides a display panel, comprising a plurality of sets of display modules, wherein the display module includes
  • the thin film transistor is electrically connected to the pixel electrode, the thin film transistors are electrically connected to each other to form a pixel circuit and a display driving circuit, and the structure of the pixel circuit and the display driving circuit includes the above The circuit structure described.
  • the present invention also provides a method for fabricating a thin film transistor circuit, comprising:
  • an active layer and a gate stack adjacent to the active layer are disposed over the substrate, the active layer being composed of a metal oxide;
  • a first annealing process forms a channel region, the channel region is adjacent to the gate stack, the source region, the drain region and the channel region are connected to each other, and are respectively located in the channel region
  • the connecting surface formed by the first annealing process between the source region, the drain region and the channel region is self-aligned with the projected area of the active layer in the active layer a vertical plane of a boundary within the boundary, wherein a resistivity of the source region and the drain region is less than a resistivity of the channel region;
  • a second adjustment layer is disposed over a portion of the entire channel region of the thin film transistor, such that a thickness of the second adjustment layer is greater than a diffusion length of the oxygen-containing material in the adjustment layer;
  • Performing a second annealing process to form a depletion channel region by a second annealing process in the channel region covered by the conditioning layer, and a second region annealing in a channel region not covered by the second conditioning layer Processing to form an enhanced channel region, wherein the depletion mode channel region formed by the second annealing process has a resistivity less than the second annealing treatment a resistivity of the enhanced channel region formed;
  • the thin film transistor having the depletion channel region is a depletion thin film transistor, and the thin film transistor having the enhancement channel region is an enhancement thin film transistor; electrically connecting the depletion thin film transistor and the The enhanced thin film transistor constitutes a circuit.
  • the first annealing process and the second annealing process include heating the circuit structure with heat, light, laser, or microwave.
  • the first annealing treatment is performed under an oxidizing atmosphere for 10 seconds to 10 hours, and the temperature is between 100 ° C and 600 ° C; the second annealing treatment is continued under the oxidizing atmosphere 5 seconds to 5 hours, temperature between 100 ° C and 400 ° C.
  • the oxidizing atmosphere includes: oxygen, ozone, nitrous oxide, water, carbon dioxide, and a plasma of the above substances.
  • the present invention also provides a display panel comprising a plurality of sets of display modules, the display module comprising the circuit manufactured by the circuit manufacturing method described above.
  • the thin film transistor of the present invention has the following advantages: First, the present scheme directly forms a source region and a drain region in the active layer by annealing treatment, which is both maintained and backed.
  • the device size of the channel etch structure achieves high performance of the etch barrier structure device.
  • the advantages of high performance and small size are taken into account, which is in line with the current development trend of displays, especially in the development of augmented reality and virtual reality.
  • the annealing treatment reduces the resistivity of the source and drain regions, thereby reducing the parasitic contact resistance between the electrode and the active layer, and significantly improving the germanium performance of the thin film transistor.
  • the annealing treatment maintains or even increases the high resistivity of the channel region, the off-state current of the thin film transistor is remarkably lowered. More importantly, the annealing process will largely eliminate the defect density in the channel region and greatly improve the reliability of the device.
  • Second insulation above the channel region The channel region of the layer protection thin film transistor is protected from the external environment, and the environmental reliability of the device can be further enhanced.
  • the invention directly covers part of the active layer region with an electrode, and reduces the resistivity of the source region and the drain region under the electrode coverage by annealing treatment, and omits the complicated steps and the photolithography step in the conventional semiconductor process, thereby saving the preparation cost.
  • the same kind ensures the low resistivity stability of the source and drain regions. Therefore, the invention has the advantages of high performance, small size, high reliability, low cost, and the like.
  • a depletion type and enhancement type metal oxide thin film type thin film transistor is formed, and a method of forming an integrated circuit is based on using a specific adjustment layer metal oxide channel region, and an annealing treatment is used to adjust the resistivity of the channel region.
  • the threshold voltage of the thin film transistor is further adjusted. Since the adjustment layer is disposed only above the channel region of a portion of the thin film transistor, the device structure itself does not change much, and the method not only greatly simplifies the process, greatly reduces the cost, but also prepares with the existing metal oxide thin film transistor. The process is fully compatible, and the same can maximize the use of existing research results, and more importantly, to maintain the high performance of the device to the greatest extent, and to improve the performance of the constructed circuit.
  • the adjustment of the resistivity of the channel region is not only large in range but also high in precision, which is advantageous for accurately modulating the threshold voltage to further optimize the circuit performance in a targeted manner.
  • the overlying conditioning layer also enhances the protection of the channel region, further protecting it from the environment and enhancing device stability.
  • the intermediate insulating layer inherent in the display panel can be directly used as an adjustment layer covering the channel region or the intermediate insulating layer and the adjustment layer are patterned together to avoid additional lithography steps. Optimize the preparation process of the circuit. Brief description of the drawing
  • FIG. 1 is a cross-sectional view showing a first embodiment of a circuit structure in the present invention.
  • FIG. 2 is a cross-sectional view showing a second embodiment of the circuit structure of the present invention.
  • FIG 3 is a cross-sectional view showing a third embodiment of the circuit structure in the present invention.
  • FIG. 4 is a cross-sectional view showing a fourth embodiment of the circuit structure of the present invention.
  • FIG. 5 is a cross-sectional view showing a fifth embodiment of the circuit structure of the present invention.
  • FIG. 6 is a cross-sectional view showing a first embodiment of a display panel structure in accordance with the present invention.
  • FIG. 7 is a cross-sectional view showing a second embodiment of the structure of the display panel of the present invention.
  • FIG. 8 is a cross-sectional view showing a third embodiment of the structure of the display panel of the present invention.
  • FIG. 1 is a cross-sectional view showing a first embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting the electrode 4, the electrode 4 and the portion of the active layer from the through hole The regions are electrically connected; a third insulating layer 8 is disposed on the electrode 4. The projection area of the third insulating layer 8 and the projected area of the electrode 4 completely overlap.
  • the projected area is the projection area in the vertical direction shown in the drawings in the specific embodiment.
  • the substance containing oxygen when the thickness of the insulating layer or the conductor layer is smaller than the diffusion length of the substance containing oxygen in the insulating layer or the conductor layer, the substance containing oxygen can pass through the insulating layer in the annealing process or The conductor layer enters the active layer of the metal oxide to maintain, or even increase, the resistivity of the metal oxide.
  • the insulating layer or the conductor layer is an oxygen permeable layer; when an insulating layer or a conductor layer is thicker than the substance containing oxygen
  • the diffusion length ⁇ in the insulating layer, the insulating layer or the conductor layer can block the oxygen-containing material, thereby reducing the electrical resistivity of the metal oxide, and the insulating layer or the conductor layer is an oxygen-impermeable layer.
  • the oxygen element-containing substance includes: oxygen, ozone, nitrous oxide, water, hydrogen peroxide, carbon dioxide, and a plasma of the above.
  • the substrate 1 includes, but is not limited to, the following materials: glass, polymer substrate, flexible material, and the like.
  • the active layer includes a combination of one or more of the following materials: zinc oxide, zinc oxynitride, tin oxide, indium oxide, gallium oxide, copper oxide, cerium oxide, indium zinc oxide , zinc tin oxide, aluminum oxide tin, indium tin oxide, indium gallium zinc oxide, indium tin zinc zinc, aluminum oxide indium tin zinc, zinc sulfide, barium titanate, barium titanate or lithium niobate.
  • the second insulating layer 7, the electrode 4, and the third insulating layer 8 collectively constitute the first conditioning layer 5.
  • the thickness of the first conditioning layer 5 is greater than the diffusion length of the oxygen-containing element in the first conditioning layer 5, and the first conditioning layer 5 is capable of blocking the oxygen-containing material, and thus the first conditioning layer 5 is Impervious to the oxygen layer.
  • the thickness of the first conditioning layer 5 is 2 to 100 times the diffusion length of the oxygen-containing substance in the first conditioning layer 5.
  • the thickness of the first insulating layer 6 is smaller than the diffusion length of the substance containing the oxygen element in the first insulating layer 6, and the substance containing the oxygen element can pass through the first annealing process.
  • An insulating layer 6 enters the channel region 22, and thus the first insulating layer 6 is an oxygen permeable layer.
  • the first insulating layer 6 comprises one or more of the following materials: silicon oxide, silicon oxynitride; further, the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the first insulating layer 6 has a thickness of 10 to 3000 nm. Preferably, the thickness of the first insulating layer 6 is between 200 nm and 50 nm.
  • the resistivity of the active layer under the coverage of the first adjustment layer 5 is lowered by the first annealing treatment to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing material can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in a region not covered by the first conditioning layer 5 The rate is maintained or even increased to form the channel region 22.
  • the resistivity of the channel region can be changed, thereby controlling the current passing through the channel region, thereby achieving the switching of the thin film transistor device.
  • the off-state current of a thin film transistor is highly dependent on the resistivity and defect density of the channel region. Higher resistivity and less defect density result in lower off-state current and better device performance.
  • the zeta current of the thin film transistor is limited by the resistivity of the source and drain regions, and the lower resistivity of the source and drain regions is beneficial to reduce parasitic resistance and increase the zeta current.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the first annealing treatment reduces the resistivity of the source region 21 and the drain region 23 while maintaining or even increasing the high resistivity of the channel region 22.
  • the source region 21, the drain region 23, and the channel region 22 in the active layer are connected to each other.
  • the connection surface between the source region 21, the drain region 23, and the channel region 22 formed by the first annealing process is automatically aligned with the first adjustment layer 5 covering the active layer without any photolithography alignment process. Border This is similar to the existing silicon-based FET process, in which the connection regions of the source region, the drain region and the channel region are automatically aligned to the gate electrode boundary. This self-alignment usually has a certain range of deviation.
  • connection faces of the source region, the drain region and the channel region are self-aligned with the vertical plane of the boundary of the first adjustment layer within the projected area of the active layer, and the alignment deviation is smaller than the thickness of the active layer. 100 times.
  • the first annealing treatment includes heating using heat, light, laser, or microwave.
  • the first annealing treatment is carried out under an oxidizing atmosphere for 10 seconds to 10 hours and at a temperature greater than 100 °C.
  • the temperature of the first annealing treatment is between 100 ° C and 600 ° C.
  • the temperature of the first annealing treatment is between 100 ° C and 500 ° C.
  • the oxidizing atmosphere comprises: oxygen, ozone, nitrous oxide, water, carbon dioxide and a plasma of the above substances.
  • the resistivity ratio of the source region and the drain region obtained by the first annealing treatment in the present invention is complicated.
  • the resulting resistivity is lower, and the low resistivity of the source and drain regions under electrode protection is more stable.
  • the process of the present invention is simpler and less expensive than conventionally cumbersome methods.
  • the present invention is not limited to the cumbersome one or more of the following impurities in the active layer: hydrogen, nitrogen, fluorine, boron, phosphorus, arsenic, silicon, indium, aluminum or antimony. This does not prevent the formation of source, channel and drain regions of the device. Therefore, the present invention is fully compatible with the existing complicated processes and has high scalability.
  • the annealing process in the present invention maintains and even improves the high resistivity of the channel region, thereby greatly reducing the off-state current of the thin film transistor, which is far lower than the current mainstream 10- 1 3 amps per micron, even down to very low 10-18 amps per micron. More importantly, annealing also largely eliminates the defect density in the channel region, such as oxygen vacancy defect density, metal interstitial defect density, etc. These defect densities are widely present in metal oxides and are considered It is an important factor in reducing the performance and reliability of thin film transistors, but it is difficult to completely eliminate them in the conventional device structure.
  • the thin film transistor structure disclosed in the present invention greatly enhances the performance and long-term reliability of the thin film transistor.
  • the current-to-voltage ratio of metal oxide thin film transistors is greatly increased, even higher than 1011; the threshold voltage drift caused by the common hysteresis effect is suppressed to within 0.15 V; a certain voltage is applied to the gate electrode.
  • the drift of the threshold voltage is degraded to around 0 V.
  • the first insulating layer covering the upper portion of the channel region can not only completely protect the channel region from the damage caused by the electrode etching like the etch barrier layer, but also protect the thin film transistor from the external environment.
  • Increase Environmental stability of strong thin film transistors for example, the problem of performance degradation such as threshold voltage drift caused by storing 10 small turns at 80 degrees Celsius and 80% relative humidity can be greatly improved by the structure of the thin film transistor of the present invention.
  • the novel thin film transistor of the present invention has many advantages over the conventional thin film transistor structure, including: a simpler manufacturing process, lower fabrication cost, higher process scalability, and better device performance. , reliability and environmental stability.
  • a circuit structure includes a substrate 1 and a plurality of thin film transistors formed of a metal oxide on the substrate 1 and constituting the active layer.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91.
  • the oxygen-containing material can enter the channel region 22 through the first insulating layer 6.
  • the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel.
  • the enhancement channel region 222 has a resistivity of 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is an enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement type thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • the thickness of the second insulation adjusting layer 91 is greater than the diffusion length of the oxygen-containing material in the second insulating adjustment layer 91, which can block the oxygen-containing substance, and thus the second insulation
  • the adjustment layer 91 is an oxygen-impermeable layer; preferably, the thickness of the second insulation adjustment layer 91 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second insulation adjustment layer 91.
  • the second insulation adjusting layer 91 includes a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is greater than 20% .
  • the second insulating adjustment layer 91 has a thickness of 10 to 3000 nm.
  • the second insulating adjustment layer 91 has a thickness of between 200 nm and 500 nm.
  • the second annealing treatment includes heating using heat, light, laser, or microwave.
  • the second annealing treatment is performed under the oxidizing atmosphere for between 5 seconds and 5 hours, and between 100 ° C and 500 ° C.
  • the temperature of the second annealing treatment is at 100 ° C and 400 Between °C.
  • the metal oxide material constituting the active layer of the depletion thin film transistor has a lower resistivity than the material constituting the active layer of the enhancement type thin film transistor.
  • the metal oxide constituting the active layer of the depletion thin film transistor has more conductive impurities such as indium or aluminum than the metal oxide constituting the active layer of the enhancement type thin film transistor.
  • the thickness of the metal oxide constituting the active layer of the thin film transistor is larger than the thickness of the metal oxide constituting the active layer of the enhancement type thin film transistor.
  • the active layer of the thin film transistor is composed of a laminate of a plurality of metal oxides, and the metal oxide of the stacked structure close to the gate insulating layer has a specific thin film transistor in the depletion thin film transistor.
  • these methods require separate adjustments of the active layers of the two modes of thin film transistors, and the material adjustment and process adjustment involved are relatively complicated. More importantly, all adjustments to the material, composition, thickness and stack of the active layer not only adjust the threshold voltage of the device, but also seriously affect other performance specifications of the device, so it is difficult to guarantee the same A high performance depletion thin film transistor and an enhancement thin film transistor are prepared. What's more, the adjustment of the material, composition, thickness and lamination of the active layer is bound to be limited without severely degrading the performance of the device. It is difficult to achieve a precise and wide range adjustment of the threshold voltage. .
  • the method of the present embodiment is based on controlling the structure of the cap layer on the channel region of the metal oxide, and adjusting the resistivity of the channel region by annealing treatment, thereby adjusting the threshold voltage of the thin film transistor. Since only the adjustment layer is disposed above part of the channel region, the device structure itself is completely unchanged, which not only greatly simplifies the process, greatly reduces the cost, but also is fully compatible with the existing metal oxide thin film transistor structure, and can maximize the use of existing The research results, more importantly, the high performance of the device is guaranteed to the greatest extent.
  • the adjustment of the resistivity of the channel region is not only large in scope but also high in precision, which is advantageous for accurately adjusting the threshold voltage to specifically optimize circuit performance.
  • the adjustment layer can also enhance the protection of the channel region, further protecting it from the environment and enhancing the stability of the device.
  • FIG. 2 is a cross-sectional view showing a second embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; above different regions of the active layer
  • the first insulating layer 6 and the oxygen-impermeable second insulating layer 71 are respectively covered; the second insulating layer 71 is formed with a through hole deep into the active layer, and a conductor is deposited in the through hole. Thereby extracting the electrode 4 from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer;
  • the thickness of the oxygen-impermeable second insulating layer 71 is greater than the diffusion length of the oxygen-containing element in the oxygen-impermeable second insulating layer 71, which can block the oxygen-containing substance
  • the oxygen impermeable second insulating layer 71 is an oxygen-impermeable layer; preferably, the thickness of the oxygen-impermeable second insulating layer 71 is 2 to the diffusion length of the oxygen-containing substance in the oxygen-impermeable second insulating layer 71 Between 100 times.
  • the oxygen impermeable second insulating layer 71 may be made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is more than 20%.
  • the oxygen impermeable second insulating layer 71 has a thickness of 10 to 3000 nm. Preferably, the thickness of the oxygen impermeable second insulating layer 71 is between 200 nm and 500 nm.
  • the resistivity of the active layer under the coverage of the oxygen-impermeable second insulating layer 71 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing element can enter the active layer through the first insulating layer 6, and thus the active layer is in the non-oxygen-free second insulating layer 71.
  • the resistivity of the area underlying is maintained even increased, forming channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of thin film transistors formed of a metal oxide on the substrate 1 over the substrate 1.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91.
  • the oxygen-containing material can enter the channel region 22 through the first insulating layer 6.
  • the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel.
  • the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221.
  • Thin film crystal having depletion channel region 221 The transistor is a depletion thin film transistor 121, and the thin film transistor having the enhancement type channel region 222 is an enhancement type thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • FIG. 3 is a cross-sectional view showing a third embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting the electrode 4, the electrode 4 and the portion of the active layer from the through hole The regions are electrically connected; the third insulating layer 8 is disposed on the electrode 4, the first insulating layer 6, and the second insulating layer 7; the projected area of the third insulating layer 8 completely overlaps the projected area of the second insulating layer 7.
  • the thickness of the third insulating layer 8 is greater than the diffusion length of the oxygen-containing material in the third insulating layer 8, which can block the oxygen-containing material, and the third insulating layer 8 is Oxygen-impermeable layer; Preferably, the thickness of the third insulating layer 8 is between 2 and 100 times the diffusion length of the oxygen-containing material in the third insulating layer 8.
  • the third insulating layer 8 may be made of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide; further, the proportion of silicon nitride in the silicon oxynitride is more than 20%.
  • the third insulating layer 8 has a thickness of 10 to 3000 nm. Preferably, the thickness of the third insulating layer 8 is between 200 nm and 500 nm.
  • the resistivity of the active layer under the coverage of the third insulating layer 8 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in a region covered by the non-third insulating layer 8 The rate is maintained or even increased to form the channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of thin film transistors on the substrate 1 which are composed of a metal oxide.
  • the entire channel region of a portion of the thin film transistor It is completely covered by the second adjustment layer 9. Performing a second annealing process on the thin film transistor structure.
  • the oxygen-containing material can pass through the first insulating layer 6 into the channel region 22, and further The resistivity of the channel region 22 is maintained, or even increased, to form the enhanced channel region 222; conversely, the second conditioning layer 9 can block the oxygen-containing species for the channel region 22, thereby reducing the channel region 22
  • the resistivity is such that a depletion channel region 221 is formed, and the resistivity of the depletion channel region 221 is smaller than that of the enhancement channel region 222.
  • the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is the enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • the thickness of the second conditioning layer 9 is greater than the diffusion length of the oxygen-containing material in the second conditioning layer 9, which blocks the oxygen-containing material, and the second conditioning layer 9 is Oxygen-impermeable layer; Preferably, the thickness of the second conditioning layer 9 is between 2 and 100 times the diffusion length of the oxygen-containing substance in the second conditioning layer 9.
  • the second conditioning layer 9 comprises a combination of one or more of the following materials: silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, silicon, gallium arsenide, titanium, molybdenum, aluminum, copper, silver, gold, Nickel, tungsten, chromium, ruthenium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, molybdenum copper alloy or copper aluminum alloy, wherein the proportion of silicon nitride in the silicon oxynitride is greater than 20%.
  • the second conditioning layer 9 has a thickness of 10 to 3000 nm. Preferably, the thickness of the second conditioning layer 9 is between 200 nm and 500 nm.
  • FIG. 4 is a cross-sectional view showing a fourth embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; a gate stack 3 disposed between the active layer and the substrate 1, and the gate stack 3 includes a gate electrode 31 and a gate insulating layer 32 disposed between the gate electrode 31 and the active layer; different regions of the active layer are respectively covered with a first insulating layer 6 and a second insulating layer 7; A through hole deep to the active layer is formed on the second insulating layer 7, and a conductor is deposited in the through hole, thereby extracting an oxygen-impermeable electrode 41 from the through hole, and the oxygen-impermeable electrode 41 and the Portions of the active layer are electrically connected; the projected area of the oxygen-impermeable electrode 41 completely overlaps with the projected area of the second insulating layer 7.
  • the thickness of the oxygen-impermeable electrode 41 is greater than the diffusion length of the oxygen-containing element in the oxygen-impermeable electrode 41, and the oxygen-impermeable electrode 41 can block the substance containing the oxygen element, and thus Oxygen permeable electrode 41 is not Oxygen permeable layer.
  • the thickness of the oxygen-impermeable electrode 41 is between 2 and 100 times the diffusion length of the oxygen-containing element in the oxygen-impermeable electrode 41.
  • the oxygen-impermeable electrode 41 comprises a combination of one or more of the following materials: titanium, molybdenum, aluminum, copper, silver, gold, nickel, tungsten, chromium, niobium, platinum, iron, titanium tungsten alloy, molybdenum aluminum alloy, Molybdenum copper alloy or copper aluminum alloy.
  • the oxygen-impermeable electrode 41 has a thickness of 10 to 3000 nm. Preferably, the thickness of the oxygen-impermeable electrode 41 is between 200 nm and 500 nm.
  • the resistivity of the active layer under the area covered by the oxygen-impermeable electrode 41 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer through the first insulating layer 6, and thus the resistance of the active layer in the region covered by the non-oxygen-impermeable electrode 41 The rate is maintained or even increased to form the channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of thin film transistors on the substrate 1 which are composed of a metal oxide to form the active layer.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second insulating adjustment layer 91.
  • the oxygen-containing material can enter the channel region 22 through the first insulating layer 6.
  • the resistivity of the channel region 22 is maintained, or even increased, to form the enhancement channel region 222; conversely, the second insulation adjustment layer 91 can block the oxygen-containing material for the channel region 22, thereby reducing the channel.
  • the enhancement channel region 222 has a resistivity of 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is an enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement type thin film transistor 122 are electrically connected to each other through a wire, a power source electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form an electric circuit.
  • FIG. 5 is a cross-sectional view showing a fifth embodiment of a circuit composed of a metal oxide thin film transistor in the present invention.
  • the thin film transistor includes: a substrate 1; an active layer disposed on the substrate 1; An oxygen permeable gate electrode 311 and an oxygen permeable gate insulating layer 321 disposed between the oxygen permeable gate electrode 311 and the active layer are disposed between the active layers; the active layer is different A first insulating layer 6 and a second insulating layer 7 are respectively covered on the upper portion of the region; a through hole deep to the active layer is formed on the second insulating layer 7 and the oxygen permeable gate insulating layer 321 A conductor is accumulated so that the electrode 4 is drawn from the through hole, and the electrode 4 is electrically connected to a partial region of the active layer.
  • the third insulating layer 8 is also covered on the electrode 4; the projected area of the third insulating layer 8 and the projected area of the second insulating layer 7 completely overlap.
  • the thickness of the oxygen permeable gate electrode 311 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate electrode 31 1 , and the oxygen-containing substance can be in the first annealing process.
  • the oxygen permeable gate electrode 311 enters the channel region 22, and thus the oxygen permeable gate electrode 311 is an oxygen permeable layer.
  • the oxygen permeable gate electrode 311 comprises one or more combinations of the following materials: zinc oxide, indium tin oxide, aluminum zinc oxide, indium zinc oxide.
  • the oxygen permeable gate electrode 311 has a thickness of 10 to 3000 nm.
  • the oxygen permeable gate electrode 311 has a thickness between 200 nm and 500 nm.
  • the thickness of the oxygen permeable gate insulating layer 321 is smaller than the diffusion length of the oxygen-containing element in the oxygen permeable gate insulating layer 321, and the oxygen-containing substance is in the first annealing process.
  • the channel region 22 can be accessed through the oxygen permeable gate insulating layer 321, so that the oxygen permeable gate insulating layer 321 is an oxygen permeable layer.
  • the oxygen permeable gate insulating layer 321 includes one or more combinations of the following materials: silicon oxide, silicon oxynitride; and the proportion of silicon nitride in the silicon oxynitride is less than 20%.
  • the oxygen permeable gate insulating layer 321 has a thickness of 10 to 3000 nm.
  • the oxygen permeable gate insulating layer 321 has a thickness of between 200 nm and 500 nm.
  • the resistivity of the active layer under the coverage of the third insulating layer 8 is lowered to form the source region 21 and the drain region 23.
  • the reduced source region 21 and the resistivity of the drain region 23 are advantageous for reducing the contact resistance between the source region 21, the drain region 23 and the electrode 4, thereby improving the germanium performance of the thin film transistor.
  • the oxygen-containing substance can enter the active layer through the first insulating layer 6, the oxygen-permeable gate insulating layer 321, and the oxygen-permeable gate electrode 311, so The resistivity of the region of the source layer covered by the non-third insulating layer 8 is maintained or even increased to form the channel region 22.
  • the first insulating layer 6 over the channel region 22 can also increase the resistivity of the channel region 22, reduce the defect density of the channel region 22, thereby improving the off-state characteristics of the thin film transistor, and the first insulating layer 6 can also be protected.
  • the channel region 22 is protected from the external environment, improving the stability and reliability of the thin film transistor.
  • the circuit structure includes a substrate 1 and a plurality of the metal oxide oxides on the substrate 1 Thin film transistor of the active layer.
  • the entire channel region of a portion of the thin film transistor is completely covered by the second adjustment layer 9. Performing a second annealing process on the thin film transistor structure.
  • the oxygen-containing material can pass through the first insulating layer 6 into the channel region 22, and further The resistivity of the channel region 22 is maintained, or even increased, to form the enhanced channel region 222; conversely, the second conditioning layer 9 can block the oxygen-containing species for the channel region 22, thereby reducing the channel region 22
  • the resistivity is such that a depletion channel region 221 is formed, and the resistivity of the depletion channel region 221 is smaller than that of the enhancement channel region 222.
  • the resistivity of the enhancement channel region 222 is 2 to 100 times the resistivity of the depletion channel region 221.
  • the thin film transistor having the depletion channel region 221 is a depletion thin film transistor 121
  • the thin film transistor having the enhancement channel region 222 is the enhancement thin film transistor 122.
  • the depletion thin film transistor 121 and the enhancement thin film transistor 122 are electrically connected to each other through a wire, a power supply electrode 111, a ground electrode 112, an input electrode 113, and an output electrode 114 to form a circuit.
  • FIG. 6 is a cross-sectional view showing a first embodiment of a display panel structure in accordance with the present invention.
  • the display panel is composed of a plurality of display modules, and the display module includes: a thin film transistor disposed on the substrate 1; an intermediate insulating layer 13 disposed on the thin film transistor; a second insulating adjustment layer 91 and an intermediate insulating layer 13 a through hole deep in the electrode 4 is formed, and a conductor is deposited in the through hole, thereby extracting the pixel electrode 14 from the through hole, and the pixel electrode 14 is electrically connected to the thin film transistor; the intermediate insulating layer 13 and A photovoltaic material 15 and a common electrode 16 are disposed over the pixel electrode 14.
  • the photoelectric material 15 includes, but is not limited to, a liquid crystal, a light emitting diode, an organic light emitting diode, and a quantum dot light emitting diode.
  • the circuit structure shown in FIG. 2 is used to form the pixel circuit and the driving circuit.
  • FIG. 7 is a cross-sectional view showing a second embodiment of the structure of the display panel of the present invention.
  • the display panel is composed of a plurality of display modules, and the display module includes: a thin film transistor disposed on the substrate 1; an intermediate insulating layer 13 disposed on the thin film transistor; a second insulating adjustment layer 91 and an intermediate insulating layer 13 a through hole deep in the electrode 4 is formed, and a conductor is deposited in the through hole, thereby extracting the pixel electrode 14 from the through hole, and the pixel electrode 14 is electrically connected to the thin film transistor; the intermediate insulating layer 13 and A photovoltaic material 15 and a common electrode 16 are disposed over the pixel electrode 14.
  • the display panel in this embodiment is similar to the circuit structure shown in FIG. 2 to form a pixel circuit and a driving circuit.
  • the difference between this embodiment and the embodiment shown in FIG. 6 is that the portion of the second insulating adjustment layer 91 on the enhancement type channel region 222 does not need to be removed by a separate photolithography step, but the light of the intermediate insulating layer 13 Engraved together.
  • this embodiment section A lithography step is saved, which greatly simplifies the process and reduces costs.
  • the projected area of the second insulating adjustment layer 91 completely overlaps with the projected area of the intermediate insulating layer 13.
  • FIG. 8 is a cross-sectional view showing a third embodiment of the display panel structure of the present invention.
  • the display module of this embodiment is similar to the display module shown in FIG. The difference is that the display module of the present embodiment has no intermediate insulating layer 13, and the function of the intermediate insulating layer 13 is taken care of by the second insulating regulating layer 91.
  • this embodiment also saves a lithography step, greatly simplifying the process and reducing the cost.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)

Abstract

L'invention concerne une structure de circuit comprenant plusieurs transistors à couche mince (TFT), la structure desdits TFT comprenant : un substrat (1) et une couche active constituée d'oxyde de métal sur ledit substrat (1) ; la couche active est jointe à un empilement de grille (3), et des zones de la couche active sont recouvertes par une première couche d'ajustement (5) ; les zones de la couche active recouvertes par la première couche d'ajustement (5) sont formées en une zone de source (21) et en une zone de drain (23) respectivement, et des zones non recouvertes par la première couche d'ajustement (5) forment une zone de canal (22) ; la zone de source (21) et la zone de drain (23) sont connectées à la zone de canal (22), étant positionnées de part et d'autre de cette dernière, et la zone de canal (22) est jointe à l'empilement de grille (3) ; une deuxième couche d'ajustement (91) est disposée au-dessus de la totalité de la zone de canal (22) de certains TFT, la zone située sous la deuxième couche d'ajustement formant une zone de canal d'appauvrissement (221) et la zone non recouverte par la deuxième couche d'ajustement (91) formant une zone de canal de renforcement ; les TFT comportant ladite zone de canal d'appauvrissement sont des TFT en mode d'appauvrissement (121), et les TFT comportant lesdites zones de canal de renforcement sont des TFT en mode de renforcement ; les TFT en mode d'appauvrissement (121) et les TFT en mode de renforcement (122) sont électriquement connectés entre eux pour former le circuit.
PCT/CN2016/103831 2015-10-29 2016-10-28 Structure de circuit constituée de transistors à couche mince et son procédé de fabrication, et panneau d'affichage WO2017071658A1 (fr)

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PCT/CN2016/103835 WO2017071661A1 (fr) 2015-10-29 2016-10-28 Transistor à couche mince, son procédé de fabrication, et panneau d'affichage
PCT/CN2016/103831 WO2017071658A1 (fr) 2015-10-29 2016-10-28 Structure de circuit constituée de transistors à couche mince et son procédé de fabrication, et panneau d'affichage
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WO2017071662A1 (fr) 2017-05-04
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CN106449763B (zh) 2019-06-25
CN106486499A (zh) 2017-03-08
CN106409841B (zh) 2019-06-25
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CN106409841A (zh) 2017-02-15
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CN106486499B (zh) 2019-08-06
CN106449732A (zh) 2017-02-22

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