CN106409841A - 一种电路结构及制作方法和显示器面板 - Google Patents

一种电路结构及制作方法和显示器面板 Download PDF

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CN106409841A
CN106409841A CN201610964428.7A CN201610964428A CN106409841A CN 106409841 A CN106409841 A CN 106409841A CN 201610964428 A CN201610964428 A CN 201610964428A CN 106409841 A CN106409841 A CN 106409841A
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film transistor
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陆磊
王文
郭海成
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Abstract

一种电路结构,包括:衬底和多个位于衬底之上的由金属氧化物构成有源层的薄膜晶体管,所述有源层包含有与栅极叠层相毗邻的沟道区,部分薄膜晶体管的整个沟道区上方设有调节层,在所述调节层覆盖下的形成耗尽型沟道区,在非调节层覆盖下的形成增强型沟道区;具有耗尽型沟道区的薄膜晶体管形成耗尽型薄膜晶体管,具有增强型沟道区的薄膜晶体管形成增强型薄膜晶体管;所述耗尽型薄膜晶体管和增强型薄膜晶体管相互电连接构成电路结构。本发明还涉及上述电路结构的制作方法和具有上述电路结构的显示器面板,可在增加薄膜晶体管阈值电压的调制范围的同时保持薄膜晶体管的高性能,制造工艺简化,成本低,可用于集成电路,特别是显示器面板中的电路。

Description

一种电路结构及制作方法和显示器面板
技术领域
本发明涉及一种由金属氧化物薄膜晶体管构成的电路结构及制造方法,尤其是用于显示器模块中的电路结构。
背景技术
作为构成显示器面板中电路不可或缺的有源器件,薄膜晶体管的性能直接影响显示器的性能。相比于传统的硅基薄膜晶体管,由金属氧化物构成有源层的薄膜晶体管具有诸多优势,比如低温工艺、高透明度、高迁移率和低漏电等,其被认为是显示器面板中硅基器件的最有希望替代者。但是现阶段,金属氧化物薄膜晶体管在电路应用中相比于传统硅基薄膜晶体管,还存在一个明显的缺陷密度。由于难以实现性能优良的p型金属氧化物薄膜晶体管,因此很难像硅基器件一样形成n型和p型薄膜晶体管互补的高性能电路。所以,由金属氧化物薄膜晶体管构成的电路目前只能基于n型器件。
伴随着金属氧化物薄膜晶体管性能的快速提升,其在显示器面板的电路中取代传统硅基晶体管的趋势已经越来越明显。而对电路的功耗和其它性能参数的进一步改良,不再能够单独依赖于薄膜晶体管自身性能的提升,而且还需要一种有源“上拉”器件。对于传统的硅基薄膜晶体管,这种有源“上拉”器件就是p型薄膜晶体管,但是对于金属氧化物薄膜晶体管来说情况完全不同。
拥有良好性能的金属氧化物薄膜晶体管目前还只局限于n型器件,比如受到广泛关注的氧化铟镓锌薄膜晶体管。在缺乏高性能p型金属氧化物薄膜晶体管前提下,为了实现性能相对良好的电路,广泛采用的替代方法是利用耗尽型的n型金属氧化物薄膜晶体管作为有源“上拉”器件,而用增强型的n型薄膜晶体管作为有源“下拉”器件。其中,耗尽型薄膜晶体管的阈值电压应比增强型薄膜晶体管的阈值电压低。
采用这种方式制备的反向器电路已有很多报道。实现耗尽型的和增强型的薄膜晶体管的单片集成的方法主要包括:调整金属氧化物有源层的材料成分、调节有源层的厚度和采用多层结构的有源层等。然而上述方法对薄膜晶体管阈值电压的调节十分受限,并且其工艺复杂,器件性能严重受限于制备过程。另外一类调节阈值电压形成耗尽型和增强型薄膜晶体管的方式是通过引入一个额外的栅极叠层,从而形成双栅结构。额外的栅极叠层专门负责调节薄膜晶体管的阈值电压,因此调节范围更大。但是,这额外的栅极叠层需要配置额外的控制电路,极大地增加了制备电路的复杂度和成本,与现有的器件结构也不兼容,背离了目前显示器面板高分辨率的发展趋势。
调节金属氧化物薄膜晶体管的阈值电压常常通过调整有源层沟道区的金属氧化物的一系列参数来实现,如调节金属氧化物的厚度、材料成分或采用多层金属氧化物结构。这些调整手段通常需要比较复杂的制备工艺和高昂的成本,而且更重要的是其对阈值电压的调节范围十分有限,还可能会损害到薄膜晶体管的器件性能。
发明内容
本发明所要解决的技术问题在于克服上述现有技术之不足,可在增加薄膜晶体管阈值电压的调制范围的同时保持薄膜晶体管的高性能,简化了现有的制造工艺,降低了制造成本,其可以有效地应用于集成电路,特别是显示器面板中的电路。
本发明提供的一种电路结构,所述电路的结构包括:衬底和多个位于所述衬底之上的由金属氧化物构成有源层的薄膜晶体管,所述有源层包含有与栅极叠层相毗邻的沟道区,部分所述薄膜晶体管的整个沟道区上方设置有调节层,在所述调节层覆盖下的形成耗尽型沟道区,在非所述调节层覆盖下的形成增强型沟道区,所述耗尽型沟道区的电阻率小于所述增强型沟道区的电阻率;所述调节层的厚度大于含氧元素的物质在所述调节层中的扩散长度;具有所述耗尽型沟道区的薄膜晶体管形成耗尽型薄膜晶体管,具有所述增强型沟道区的薄膜晶体管形成增强型薄膜晶体管;所述耗尽型薄膜晶体管和所述增强型薄膜晶体管相互电连接构成电路结构。
作为上述电路结构优选的方式:
所述增强型沟道区的电阻率为所述耗尽型沟道区的电阻率的2至100倍。
所述有源层包括以下材料中的一种或多种的组合:氧化锌、氮氧化锌、氧化锡、氧化铟、氧化镓、氧化铜、氧化铋、氧化铟锌、氧化锌锡、氧化铝锡、氧化铟锡、氧化铟镓锌、氧化铟锡锌、氧化铝铟锡锌、硫化锌、钛酸钡、钛酸锶或铌酸锂。
所述调节层的厚度为所述含氧元素的物质在所述调节层中的扩散长度的2至100倍之间。
所述调节层包括以下材料中的一种或多种的组合:氮化硅、氮氧化硅、氧化铝、氧化铪、硅、砷化镓,钛、钼、铝、铜、银、金、镍、钨、铬、铪、铂、铁、钛钨合金、钼铝合金、钼铜合金或铜铝合金;进一步地,所述氮氧化硅中的氮化硅比例大于20%。所述调节层的厚度为10至3000纳米。
所述含氧元素的物质包括:氧气、臭氧、一氧化二氮、水、双氧水、二氧化碳和上述物质的等离子体。
本发明还提供了一种显示器面板,包括多组显示模块,所述显示模块包含上述所述的电路结构。
本发明还提供了一种薄膜晶体管电路制造方法,包含:
准备一个衬底;
在所述衬底之上设置薄膜晶体管,所述薄膜晶体管的有源层由金属氧化物构成,所述有源层包含有与栅极叠层相毗邻的沟道区;
在部分薄膜晶体管的整个沟道区之上设置调节层,使所述调节层的厚度大于含氧元素的物质在所述调节层中的扩散长度;
退火处理中,使所述调节层覆盖下的沟道区为耗尽型沟道区;使在非所述调节层覆盖下的沟道区为增强型沟道区;所述退火处理形成的所述耗尽型沟道区的电阻率小于退火处理形成的所述增强型沟道区的电阻率;
具有所述耗尽型沟道区的薄膜晶体管形成耗尽型薄膜晶体管,具有所述增强型沟道区的薄膜晶体管形成增强型薄膜晶体管;电连接所述耗尽型薄膜晶体管和所述增强型薄膜晶体管,即构成所述电路结构。
作为本发明上述所述的电路制作方法的优选方式:
所述退火处理包括利用热、光、激光、微波加热。
所述退火处理是在氧化气氛下,持续5秒至5小时,温度在100℃和400℃之间。
所述氧化气氛包括:氧气、臭氧、一氧化二氮、水、二氧化碳和上述物质的等离子体。
根据上述方法,本发明还提供了一种显示器面板,包括多组显示模块,所述显示模块包含上述所述的电路制造方法所制造的电路。
本发明中形成耗尽型和增强型金属氧化物薄膜晶体管,构成集成电路的结构是基于使用特定调节层金属氧化物沟道区,利用退火处理调节沟道区的电阻率,进而调节薄膜晶体管的阈值电压。因为只在部分薄膜晶体管沟道区上方设置调节层,器件结构本身不会有太大调整改变,此种结构不仅工艺大大简化、成本极大降低,而且与现有金属氧化物薄膜晶体管的制备工艺完全兼容、能够最大化地利用既有的研究成果,更重要的是在最大程度地保持器件的高性能,有利于提高构成的电路的性能。同时,沟道区的电阻率的调节不仅范围大、而且精度高,有利于精确调制阈值电压以进一步针对性地优化电路性能。覆盖的调节层还可以增强对沟道区保护,使其进一步免受环境的影响,增强了器件的稳定性。更进一步,在显示器面板电路中,可以利用显示器面板中固有的中间绝缘层直接作为覆盖沟道区上的调节层或者中间绝缘层和调节层一起图形化的方式免去额外的光刻步骤,大大优化电路的制备工艺。
附图说明
图1为本发明中电路结构的第一种实施例的剖视图。
图2为本发明中电路结构的第二种实施例的剖视图。
图3为本发明中电路结构的第三种实施例的剖视图。
图4为本发明中电路结构的第四种实施例的剖视图。
图5为本发明中电路结构的第五种实施例的剖视图。
图6为本发明中电路结构的第六种实施例的剖视图。
图7为本发明中显示面板结构的第一种实施例的剖视图。
图8为本发明中显示面板结构的第二种实施例的剖视图。
图9为本发明中显示面板结构的第三种实施例的剖视图。
图10为本发明中显示面板结构的第三种实施例的剖视图。
具体实施方式
下面结合附图及实施例详细描述本发明。应当理解,此处所描述的具体实施例为非限制性示例实施例,且附图示出的特征不是必须按比例绘制。所给出的示例仅旨在有利于解释本发明,不应被理解为对本发明的限定。
参照图1,图1为本发明中电路结构的第一种实施例的剖视图。本实施例中,电路由耗尽型和增强型的背栅刻蚀阻挡层结构的金属氧化物薄膜晶体管相互电连接构成。其中,薄膜晶体管包括:衬底1,设置在衬底1上的有源层,所述有源层与衬底1之间还设置有栅极叠3,栅极叠层3则包括栅极电极31和设置在栅极电极31和所述有源层之间的栅极绝缘层32;在所述有源层上设置有第一绝缘层6;第一绝缘层6和所述有源层之上覆盖有电极4;在第一绝缘层6和电极4之上设置有第二绝缘层7,第二绝缘层7部分区域上设置有调节层5。其中,所述有源层与电极4相接触的区域分别形成源区21和漏区23,所述有源层与非电极4接触的区域形成沟道区22。其中,沟道区22与栅极叠层3相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接。其中,第一绝缘层6起到刻蚀阻挡层作用,保护沟道区22免受电极4刻蚀过程的损害,避免器件性能的退化。
本发明中,当绝缘层或导体层的厚度小于含氧元素的物质在该绝缘层或导体层中的扩散长度时,含氧元素的物质能在退火处理中透过该绝缘层或导体层进入金属氧化物有源层,从而保持、甚至提高金属氧化物的电阻率,此时该绝缘层或导体层是透氧层;当一个绝缘层或导体层的厚度大于含氧元素的物质在该绝缘层中的扩散长度时,该绝缘层或导体层能阻挡含氧元素的物质,从而降低金属氧化物的电阻率,此时该绝缘层或导体层是不透氧层。
所述含氧元素的物质包括:氧气、臭氧、一氧化二氮、水、双氧水、二氧化碳和上述物质的等离子体。
参照图1,衬底1包括但不限于以下材料:玻璃、聚合物衬底、柔性材料等。
参照图1,所述有源层包括以下材料中的一种或多种的组合:氧化锌、氮氧化锌、氧化锡、氧化铟、氧化镓、氧化铜、氧化铋、氧化铟锌、氧化锌锡、氧化铝锡、氧化铟锡、氧化铟镓锌、氧化铟锡锌、氧化铝铟锡锌、硫化锌、钛酸钡、钛酸锶或铌酸锂。
参照图1,第一绝缘层6的厚度小于所述含氧元素的物质在第一绝缘层6中的扩散长度,所述含氧元素的物质在退火处理中能够透过第一绝缘层6,因此在本实施例中第一绝缘层6是透氧层。第一绝缘层6包含以下材料的一种或多种组合:氧化硅、氮氧化硅;进一步地,所述氮氧化硅中氮化硅的比例小于20%。第一绝缘层6的厚度为10至3000纳米。优选地,第一绝缘层6的厚度在200纳米到400纳米之间。
参照图1,第二绝缘层7的厚度小于所述含氧元素的物质在第二绝缘层7中的扩散长度,所述含氧元素的物质在退火处理中能够透过第二绝缘层7,因此在本实施例中第二绝缘层7是透氧层。第二绝缘层7包含以下材料的一种或多种组合:氧化硅、氮氧化硅;进一步地,所述氮氧化硅中氮化硅的比例小于20%。第二绝缘层7的厚度为10至3000纳米。优选地,第二绝缘层7的厚度在200纳米到400纳米之间。
参照图1,调节层5的厚度大于所述含氧元素的物质在调节层5中的扩散长度,其能阻挡所述含氧元素的物质,因此在本实施例中调节层5是不透氧层。优选地,调节层5的厚度是所述含氧元素的物质在调节层5中扩散长度的2至100倍。调节层5包含以下材料的一种或多种组合:氮化硅、氮氧化硅、氧化铝、氧化铪、硅、砷化镓、钛、钼、铝、铜、银、金、镍、钨、铬、铪、铂、铁、钛钨合金、钼铝合金、钼铜合金或铜铝合金;进一步地,所述氮氧化硅中氮化硅的比例大于20%。调节层5的厚度为10至3000纳米。优选地,调节层5的厚度在200纳米到400纳米之间。
参照图1,电路结构包含衬底1和多个位于衬底1之上的由金属氧化物构成所述有源层的薄膜晶体管。所述薄膜晶体管结构中,部分所述薄膜晶体管的整个沟道区22被调节层5完全覆盖。对所述薄膜晶体管结构进行退火处理,当沟道区22在非调节层5覆盖下时,所述含氧元素的物质能够透过第一绝缘层6和第二绝缘层7进入沟道区22,进而保持、甚至提高沟道区22的电阻率,从而形成增强型沟道区222;相反地,调节层5能够阻挡所述含氧元素的物质,进而降低沟道区22的电阻率,从而形成耗尽型沟道区221,耗尽型沟道区221的电阻率小于增强型沟道区222的电阻率。优选地,增强型沟道区222的电阻率为耗尽型沟道区221的电阻率的2至100倍。具有耗尽型沟道区221的薄膜晶体管为耗尽型薄膜晶体管111,具有增强型沟道区222的薄膜晶体管为增强型薄膜晶体管112。耗尽型薄膜晶体管111和增强型薄膜晶体管112相互通过导线、电源电极101、接地电极102、输入电极103以及输出电极104电连接形成电路。
参照图1,所述退火处理包括利用热、光、激光、微波进行加热。所述退火处理是在氧化气氛下进行,持续时间5秒至5小时之间,温度在100℃和400℃之间。优选地,温度在100℃和400℃之间。所述氧化气氛包括:氧气、臭氧、一氧化二氮、水、二氧化碳和以上物质的等离子体。
本发明公开了在薄膜晶体管沟道区之上覆盖调节层,然后进行退火处理来改变沟道区的电阻率,进而调节薄膜晶体管的阈值电压的方法。此方法简单易行,成本低廉,不仅增加了薄膜晶体管阈值电压的调制范围,且保持了薄膜晶体管的高性能。
相比于传统的方法,本发明中形成耗尽型和增强型金属氧化物薄膜晶体管,构成集成电路的方法是基于使用特定调节层金属氧化物沟道区,利用退火处理调节沟道区的电阻率,进而调节薄膜晶体管的阈值电压。因为只在部分薄膜晶体管沟道区上方设置调节层,器件结构本身不会有太大的改变,此方法不仅大大简化了工艺、极大降低了成本,而且与现有金属氧化物薄膜晶体管的制备工艺完全兼容,同时能够最大化地利用既有的研究成果,更重要的是在最大程度地保持器件的高性能,有利于提高构成的电路的性能。同时,通过此方法,沟道区的电阻率的调节不仅范围大、而且精度高,有利于精确调制阈值电压以进一步针对性地优化电路性能。覆盖的调节层还可以增强对沟道区保护,使其进一步免受环境的影响,增强了器件的稳定性。更进一步,在显示器面板电路中,可以利用显示器面板中固有的中间绝缘层直接作为覆盖沟道区上的调节层或者中间绝缘层和调节层一起图形化的方式免去额外的光刻步骤,大大优化电路的制备工艺。本发明在传统的显示器面板的制备过程中,通过在部分薄膜晶体管的沟道区上选择性地覆盖调节层,继而退火处理可以实现集成于同一基底上的增强型和耗尽型的金属氧化物薄膜晶体管,进而制备高性能的像素电路和驱动电路。
参照图2,图2为本发明中电路结构的第二种实施例的剖视图。在本实施例中,电路由耗尽型和增强型的背栅刻蚀阻挡层结构的金属氧化物薄膜晶体管相互电连接构成。其中,薄膜晶体管包括:衬底1,设置在衬底1上的有源层;所述有源层与衬底1之间还设置有栅极叠层3,栅极叠层3则包括栅极电极31和设置在栅极电极31和所述有源层之间的栅极绝缘层32;在所述有源层上设置有第一绝缘层6,在第一绝缘层6部分区域之上设置有绝缘调节层51;第一绝缘层6、绝缘调节层51和所述有源层之上覆盖有电极4。其中,所述有源层与电极4相接触的区域分别形成源区21和漏区23,所述有源层与非电极4接触的区域形成沟道区22。其中,沟道区22与栅极叠层3相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接。其中,第一绝缘层6起到刻蚀阻挡层作用,保护沟道区22免受电极4刻蚀过程的损害,避免器件性能的退化。
参照图2,绝缘调节层51的厚度大于所述含氧元素的物质在绝缘调节层51中的扩散长度,其能阻挡所述含氧元素的物质,因此在本实施例中绝缘调节层51是不透氧层。优选地,绝缘调节层51的厚度是所述含氧元素的物质在绝缘调节层51中扩散长度的2至100倍。绝缘调节层51包含以下材料的一种或多种组合:氮化硅、氮氧化硅、氧化铝或氧化铪;进一步地,所述氮氧化硅中氮化硅的比例大于20%。绝缘调节层51的厚度为10至3000纳米。优选地,绝缘调节层51的厚度在200纳米到400纳米之间。
参照图2,电路结构包含衬底1和多个位于衬底1之上的由金属氧化物构成所述有源层的薄膜晶体管。所述薄膜晶体管结构中,部分所述薄膜晶体管的整个沟道区22被绝缘调节层51完全覆盖。对所述薄膜晶体管结构进行退火处理,当沟道区22在非绝缘调节层51覆盖下时,所述含氧元素的物质能够透过第一绝缘层6进入沟道区22,进而保持、甚至提高沟道区22的电阻率,从而形成增强型沟道区222;相反地,绝缘调节层51能够阻挡所述含氧元素的物质,进而降低沟道区22的电阻率,从而形成耗尽型沟道区221,耗尽型沟道区221的电阻率小于增强型沟道区222的电阻率。优选地,增强型沟道区222的电阻率为耗尽型沟道区221的电阻率的2至100倍。具有耗尽型沟道区221的薄膜晶体管为耗尽型薄膜晶体管111,具有增强型沟道区222的薄膜晶体管为增强型薄膜晶体管112。耗尽型薄膜晶体管111和增强型薄膜晶体管112相互通过导线、电源电极101、接地电极102、输入电极103以及输出电极104电连接形成电路。
参照图3,图3为本发明中电路结构的第三种实施例的剖视图。在本实施例中,电路由耗尽型和增强型的背栅背沟道刻蚀结构金属氧化物薄膜晶体管相互电连接构成。其中,薄膜晶体管包括:衬底1,设置在衬底1上的有源层;所述有源层与衬底1之间还设置有栅极叠层3,栅极叠层3则包括栅极电极31和设置在栅极电极31和所述有源层之间的栅极绝缘层32;所述有源层之上覆盖有电极4;在所述有源层和电极4之上设置有绝缘调节层51。其中,所述有源层与电极4相接触的区域分别形成源区21和漏区23,所述有源层与非电极4接触的区域形成沟道区22。其中,沟道区22与栅极叠层3相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接。其中,沟道区22在电极4的刻蚀过程中会受到伤害,降低器件性能。绝缘调节层51能够保护沟道区22免受外界环境影响,增强了器件的稳定性。
参照图3,电路结构包含衬底1和多个位于衬底1之上的由金属氧化物构成所述有源层的薄膜晶体管。所述薄膜晶体管结构中,部分所述薄膜晶体管的整个沟道区22被绝缘调节层51完全覆盖。对所述薄膜晶体管结构进行退火处理,当沟道区22在非绝缘调节层51覆盖下时,所述含氧元素的物质能够进入沟道区22,进而保持、甚至提高沟道区22的电阻率,从而形成增强型沟道区222;相反地,绝缘调节层51能够阻挡所述含氧元素的物质,进而降低沟道区22的电阻率,从而形成耗尽型沟道区221,耗尽型沟道区221的电阻率小于增强型沟道区222的电阻率。优选地,增强型沟道区222的电阻率为耗尽型沟道区221的电阻率的2至100倍。具有耗尽型沟道区221的薄膜晶体管为耗尽型薄膜晶体管111,具有增强型沟道区222的薄膜晶体管为增强型薄膜晶体管112。耗尽型薄膜晶体管111和增强型薄膜晶体管112相互通过导线、电源电极101、接地电极102、输入电极103以及输出电极104电连接形成电路。
参照图4,图4为本发明中电路结构的第四种实施例的剖视图。在本实施例中,电路由耗尽型和增强型的顶栅金属氧化物薄膜晶体管相互电连接构成。其中,薄膜晶体管包括:衬底1,设置在衬底1上的有源层;所述有源层之上设置透氧栅极电极311和设置在透氧栅极电极311和所述有源层之间的透氧栅极绝缘层321;所述有源层上、透氧栅极电极311和透氧栅极绝缘层321之上设置有第一绝缘层6、第一绝缘层6的部分区域上设置有绝缘调节层51。其中,所述有源层自对准于透氧栅极电极311掺杂形成源区21、漏区23和沟道区22,所述有源层在透氧栅极电极311投影面积之内的区域为沟道区22,所述有源层在透氧栅极电极311投影面积之外的区域分别为源区21和漏区23。其中,沟道区22与透氧栅极绝缘层321相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接。透氧栅极绝缘层321、第一绝缘层6和绝缘调节层51上形成有深至源区21和漏区23的通孔,所述通孔内淀积有导体,从而由所述通孔中引出电极4,电极4分别与源区21和漏区23相电连接。
在本发明中,所述的投影面积为具体实施例中的附图所示的垂直方向的投影面积。
参照图4,透氧栅极电极311的厚度小于所述含氧元素的物质在透氧栅极电极311中的扩散长度,所述含氧元素的物质在退火处理中能够透过透氧栅极电极311进入沟道区22,因此透氧栅极电极311是透氧层。透氧栅极电极311包含以下材料的一种或多种组合:氧化锌、氧化铟锡、氧化铝锌、氧化铟锌。透氧栅极电极311的厚度为10至3000纳米。优选地,透氧栅极电极311的厚度在200纳米到400纳米之间。
参照图4,透氧栅极绝缘层321的厚度小于所述含氧元素的物质在透氧栅极绝缘层321中的扩散长度,所述含氧元素的物质在退火处理中能够透过透氧栅极绝缘层321进入沟道区22,因此透氧栅极绝缘层321是透氧层。透氧栅极绝缘层321包含以下材料的一种或多种组合:氧化硅、氮氧化硅;进一步地,所述氮氧化硅中氮化硅的比例小于20%。透氧栅极绝缘层321的厚度为10至3000纳米。优选地,透氧栅极绝缘层321的厚度在200纳米到400纳米之间。
参照图4,电路结构包含衬底1和多个位于衬底1之上的由金属氧化物构成所述有源层的薄膜晶体管。所述薄膜晶体管结构中,部分所述薄膜晶体管的整个沟道区22被绝缘调节层51完全覆盖。对所述薄膜晶体管结构进行退火处理,当沟道区22在非绝缘调节层51覆盖下时,所述含氧元素的物质能够透过第一绝缘层6、透氧栅极电极311和透氧栅极绝缘层321进入沟道区22,进而保持、甚至提高沟道区22的电阻率,从而形成增强型沟道区222;相反地,绝缘调节层51能够阻挡所述含氧元素的物质,进而降低沟道区22的电阻率,从而形成耗尽型沟道区221,耗尽型沟道区221的电阻率小于增强型沟道区222的电阻率。优选地,增强型沟道区222的电阻率为耗尽型沟道区221的电阻率的2至100倍。具有耗尽型沟道区221的薄膜晶体管为耗尽型薄膜晶体管111,具有增强型沟道区222的薄膜晶体管为增强型薄膜晶体管112。耗尽型薄膜晶体管111和增强型薄膜晶体管112相互通过导线、电源电极101、接地电极102、输入电极103以及输出电极104电连接形成电路。
参照图5,图5为本发明中电路结构的第五种实施例的剖视图。在本实施例中,电路由耗尽型和增强型的顶栅金属氧化物薄膜晶体管相互电连接构成。其中,薄膜晶体管包括:衬底1,设置在衬底1上的有源层;所述有源层之上设置有透氧栅极电极311和设置在透氧栅极电极311和所述有源层之间的透氧栅极绝缘层321;部分透氧栅极绝缘层321和透氧栅极电极311之间还设置有绝缘调节层51;所述有源层、透氧栅极电极311、透氧栅极绝缘层321和绝缘调节层51之上设置有第一绝缘层6。其中,所述有源层自对准于透氧栅极电极311掺杂形成源区21、漏区23和沟道区22,所述有源层在透氧栅极电极311投影面积之内的区域为沟道区22,所述有源层在透氧栅极电极311投影面积之外的区域分别为源区21和漏区23。其中,沟道区22与透氧栅极绝缘层321相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接。透氧栅极绝缘层321、第一绝缘层6和绝缘调节层51上形成有深至源区21和漏区23的通孔,所述通孔内淀积有导体,从而由所述通孔中引出电极4,电极4分别与源区21和漏区23相电连接。
参照图5,电路结构包含衬底1和多个位于衬底1之上的由金属氧化物构成所述有源层的薄膜晶体管。所述薄膜晶体管结构中,部分所述薄膜晶体管的整个沟道区22被绝缘调节层51完全覆盖。对所述薄膜晶体管结构进行退火处理,当沟道区22在非绝缘调节层51覆盖下时,所述含氧元素的物质能够透过第一绝缘层6、透氧栅极电极311和透氧栅极绝缘层321进入沟道区22,进而保持、甚至提高沟道区22的电阻率,从而形成增强型沟道区222;相反地,绝缘调节层51能够阻挡所述含氧元素的物质,进而降低沟道区22的电阻率,从而形成耗尽型沟道区221,耗尽型沟道区221的电阻率小于增强型沟道区222的电阻率。优选地,增强型沟道区222的电阻率为耗尽型沟道区221的电阻率的2至100倍。具有耗尽型沟道区221的薄膜晶体管为耗尽型薄膜晶体管111,具有增强型沟道区222的薄膜晶体管为增强型薄膜晶体管112。耗尽型薄膜晶体管111和增强型薄膜晶体管112相互通过导线、电源电极101、接地电极102、输入电极103以及输出电极104电连接形成电路。
参照图6,图6为本发明中电路结构的第六种实施例的剖视图。在本实施例中,电路由耗尽型和增强型的顶栅金属氧化物薄膜晶体管相互电连接构成。其中,薄膜晶体管包括:衬底1,设置在衬底1上的有源层;所述有源层之上设置有透氧栅极电极311和设置在透氧栅极电极311和所述有源层之间的透氧栅极绝缘层321;部分透氧栅极电极311之上还设置有调节层5;所述有源层、透氧栅极绝缘层321、透氧栅极电极311和调节层5之上设置有第一绝缘层6。其中,所述有源层自对准于透氧栅极电极311掺杂形成源区21、漏区23和沟道区22,所述有源层在透氧栅极电极311投影面积之内的区域为沟道区22,所述有源层在透氧栅极电极311投影面积之外的区域分别为源区21和漏区23。其中,沟道区22与透氧栅极绝缘层321相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接。透氧栅极绝缘层321、第一绝缘层6和调节层5上形成有深至源区21和漏区23的通孔,所述通孔内淀积有导体,从而由所述通孔中引出电极4,电极4分别与源区21和漏区23相电连接。
参照图6,电路结构包含衬底1和多个位于衬底1之上的由金属氧化物构成所述有源层的薄膜晶体管。所述薄膜晶体管结构中,部分所述薄膜晶体管的整个沟道区22被调节层5完全覆盖。对所述薄膜晶体管结构进行退火处理,当沟道区22在非调节层5覆盖下时,所述含氧元素的物质能够透过第一绝缘层6、透氧栅极电极311和透氧栅极绝缘层321进入沟道区22,进而保持、甚至提高沟道区22的电阻率,从而形成增强型沟道区222;相反地,调节层5能够阻挡所述含氧元素的物质,进而降低沟道区22的电阻率,从而形成耗尽型沟道区221,耗尽型沟道区221的电阻率小于增强型沟道区222的电阻率。优选地,增强型沟道区222的电阻率为耗尽型沟道区221的电阻率的2至100倍。具有耗尽型沟道区221的薄膜晶体管为耗尽型薄膜晶体管111,具有增强型沟道区222的薄膜晶体管为增强型薄膜晶体管112。耗尽型薄膜晶体管111和增强型薄膜晶体管112相互通过导线电源电极101、接地电极102、输入电极103以及输出电极104电连接形成电路。
参照图7,图7为本发明中显示面板结构的第一种实施例的剖视图。显示器面板由多个显示模块组成,显示模块中包括:设置于衬底之上的薄膜晶体管,采用图3所述薄膜晶体管结构;设置于所述薄膜晶体管之上的中间绝缘层13;绝缘调节层51和中间绝缘层13上形成有深至电极4的通孔,所述通孔内淀积有导体,从而由所述通孔中引出像素电极14,像素电极14与所述薄膜晶体管相电连接;中间绝缘层13和像素电极14之上设置光电材料15和公共电极16。其中,光电材料14包括但不限于:液晶、发光二极管、有机发光二极管、量子点发光二极管。对于现实面板结构,形成耗尽型薄膜晶体管和增强型薄膜晶体管的退火处理在显示面板结构制备到中间结构之后进行。在本实施例中,设置绝缘调节层51之后形成第一中间结构121,此时进行所述退火处理,形成耗尽型薄膜晶体管和增强型薄膜晶体管。
参照图8,图8为本发明中显示面板结构的第二种实施例的剖视图。显示器面板由多个显示模块组成,显示模块中包括:设置于衬底之上的薄膜晶体管,采用图3所述薄膜晶体管结构;设置于所述薄膜晶体管之上的透氧中间绝缘层131;绝缘调节层51和透氧中间绝缘层131上形成有深至电极4的通孔,所述通孔内淀积有导体,从而由所述通孔中引出像素电极14,像素电极14与所述薄膜晶体管相电连接;透氧中间绝缘层131和像素电极14之上设置光电材料15和公共电极16。对于现实面板结构,形成耗尽型薄膜晶体管和增强型薄膜晶体管的退火处理在显示面板结构制备到中间结构之后进行。在本实施例中,设置调节层5之后形成第二中间结构122,此时进行所述退火处理,形成耗尽型薄膜晶体管和增强型薄膜晶体管。
参照图8,透氧中间绝缘层131的厚度小于所述含氧元素的物质在透氧中间绝缘层131中的扩散长度,所述含氧元素的物质在退火处理中能够透过透氧中间绝缘层131进入沟道区22,因此透氧中间绝缘层131是透氧层。透氧中间绝缘层131包含以下材料的一种或多种组合:氧化硅、氮氧化硅;进一步地,所述氮氧化硅中氮化硅的比例小于20%。透氧中间绝缘层131的厚度为10至3000纳米。优选地,透氧中间绝缘层131的厚度在200纳米到400纳米之间。
参照图9,图9为本发明中显示面板结构的第三种实施例的剖视图。显示器面板由多个显示模块组成,显示模块中包括薄膜晶体管、中间绝缘层13、像素电极14、光电材料15以及公共电极16。像素电极14与所述薄膜晶体管相电连接。
参照图9,本实施例中薄膜晶体管采用背栅背沟道刻蚀结构。所述薄膜晶体管包含:衬底1;设置在衬底1上的有源层;所述有源层与衬底1之间还设置有栅极叠层3,栅极叠层3则包括栅极电极31和设置在栅极电极31和所述有源层之间的栅极绝缘层32;所述有源层之上覆盖有电极4,所述有源层与电极4相接触的区域分别形成源区21和漏区23,所述有源层非与电极4接触的区域形成沟道区22,沟道区22与栅极叠层3相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接;所述有源层和电极4之上设置有的第二绝缘层7和绝缘调节层51;第二绝缘层7和绝缘调节层51上形成有深至电极4的通孔,所述通孔内淀积有导体,从而由所述通孔中引出第二电极8,第二电极8与电极4相电连接。薄膜晶体管之上设置有中间绝缘层13,中间绝缘层13和绝缘调节层51上形成有深至第二电极8的通孔,所述通孔内淀积有导体,从而由所述通孔中引出像素电极14,进而使像素电极14与所述薄膜晶体管相电连接。其中,在刻蚀中间绝缘层13上的所述通孔的同时,部分沟道区22上方的绝缘调节层51也被完全刻蚀移除,无需借助额外光刻步骤,因而中间绝缘层13的投影面积和绝缘调节层51的投影面积完全重叠。对于现实面板结构,形成耗尽型薄膜晶体管和增强型薄膜晶体管的退火处理在显示面板结构制备到中间结构之后进行。在本实施例中,设置中间绝缘层13之后形成的第三中间结构123,此时进行所述退火处理,形成耗尽型薄膜晶体管和增强型薄膜晶体管。
参照图10,图10为本发明中显示面板结构的第四种实施例的剖视图。显示器面板由多个显示模块组成,显示模块中包括薄膜晶体管、像素电极14、光电材料15以及公共电极16。像素电极14与所述薄膜晶体管相电连接。
参照图10,本实施例中薄膜晶体管采用背栅背沟道刻蚀结构。薄膜晶体管包含:衬底1;设置在衬底1上的有源层。所述有源层与衬底1之间还设置有栅极叠层3,栅极叠层3则包括栅极电极31和设置在栅极电极31和所述有源层之间的栅极绝缘层32;所述有源层之上覆盖有电极4,所述有源层与电极4相接触的区域分别形成源区21和漏区23,所述有源层与非电极4接触的区域形成沟道区22;其中,沟道区22与栅极叠层3相毗邻,而源区21和漏区23分别位于沟道区22的两端,并与沟道区22相连接;所述有源层和电极4之上设置有第二绝缘层7和绝缘调节层51;第二绝缘层7和绝缘调节层51上形成有深至电极4的通孔,所述通孔内淀积有导体,从而由所述通孔中引出第二电极8,第二电极8与电极4相电连接。绝缘调节层51上形成有深至第二电极8的通孔,所述通孔内淀积有导体,从而由所述通孔中引出像素电极14,进而使像素电极14与所述薄膜晶体管相电连接。在本实施例中,绝缘调节层51同时也起到中间绝缘层的作用。对于现实面板结构,形成耗尽型薄膜晶体管和增强型薄膜晶体管的退火处理在显示面板结构制备到中间结构之后进行。在本实施例中,设置中间绝缘层13之后形成的第四中间结构124,此时进行所述退火处理,形成耗尽型薄膜晶体管和增强型薄膜晶体管。
最后应当说明的是,以上实施例仅为本发明的较佳实施例而已,而非对本发明保护范围的限制,本领域的普通技术人员应当理解,凡在本发明的精神和原则之内所作的任何修改、等同替换或改进等,均应包含在本发明的保护范围之内。

Claims (13)

1.一种电路结构,其特征在于,包括:衬底和多个位于所述衬底之上的由金属氧化物构成有源层的薄膜晶体管,所述有源层包含有与栅极叠层相毗邻的沟道区,部分所述薄膜晶体管的整个沟道区上方设置有调节层,在所述调节层覆盖下的形成耗尽型沟道区,在非所述调节层覆盖下的形成增强型沟道区,所述耗尽型沟道区的电阻率小于所述增强型沟道区的电阻率;所述调节层的厚度大于含氧元素的物质在所述调节层中的扩散长度;具有所述耗尽型沟道区的薄膜晶体管形成耗尽型薄膜晶体管,具有所述增强型沟道区的薄膜晶体管形成增强型薄膜晶体管;所述耗尽型薄膜晶体管和所述增强型薄膜晶体管相互电连接构成电路结构。
2.根据权利要求1所述的电路结构,其特征在于,所述增强型沟道区的电阻率为所述耗尽型沟道区的电阻率的2至100倍。
3.根据权利要求1所述的电路结构,其特征在于,所述有源层包括以下材料中的一种或多种的组合:氧化锌、氮氧化锌、氧化锡、氧化铟、氧化镓、氧化铜、氧化铋、氧化铟锌、氧化锌锡、氧化铝锡、氧化铟锡、氧化铟镓锌、氧化铟锡锌、氧化铝铟锡锌、硫化锌、钛酸钡、钛酸锶或铌酸锂。
4.根据权利要求1所述的电路结构,其特征在于,所述调节层的厚度为所述含氧元素的物质在所述调节层中的扩散长度的2至100倍之间。
5.根据权利要求1所述的电路结构,其特征在于,所述调节层包括以下材料中的一种或多种的组合:氮化硅、氮氧化硅、氧化铝、氧化铪、硅、砷化镓,钛、钼、铝、铜、银、金、镍、钨、铬、铪、铂、铁,以及钛钨合金、钼铝合金、钼铜合金或铜铝合金;进一步得,所述氮氧化硅中的氮化硅比例大于20%。
6.根据权利要求5所述的电路结构,其特征在于,所述调节层的厚度为10至3000纳米。
7.根据权利要求1所述的电路结构,其特征在于,所述含氧元素的物质包括:氧气、臭氧、一氧化二氮、水、双氧水、二氧化碳和上述物质的等离子体。
8.一种显示器面板,其特征在于,包括多组显示模块,所述显示模块包含权利要求1至7任一项所述的电路结构。
9.一种电路结构的制造方法,其特征在于,包含:
准备一个衬底;
在所述衬底之上设置薄膜晶体管,所述薄膜晶体管的有源层由金属氧化物构成,所述有源层包含有与栅极叠层相毗邻的沟道区;
在部分薄膜晶体管的整个沟道区之上设置调节层,使所述调节层的厚度大于含氧元素的物质在所述调节层中的扩散长度;
退火处理中,使在所述调节层覆盖下的沟道区为耗尽型沟道区;使在非所述调节层覆盖下的沟道区为增强型沟道区;所述退火处理形成的所述耗尽型沟道区的电阻率小于退火处理形成的所述增强型沟道区的电阻率;
具有所述耗尽型沟道区的薄膜晶体管形成耗尽型薄膜晶体管,具有所述增强型沟道区的薄膜晶体管形成增强型薄膜晶体管;电连接所述耗尽型薄膜晶体管和所述增强型薄膜晶体管,即构成所述电路结构。
10.根据权利要求9所述的方法,其特征在于,所述退火处理包括利用热、光、激光、微波加热。
11.根据权利要求9所述的方法,其特征在于,所述退火处理是在氧化气氛下,持续5秒至5小时,温度在100℃和400℃之间。
12.根据权利要求11所述的方法中,其特征在于,所述氧化气氛包括:氧气、臭氧、一氧化二氮、水、二氧化碳和上述物质的等离子体。
13.一种显示器面板,其特征在于,包括多组显示模块,所述显示模块包含权利要求9至12任一项所述的电路制造方法所制造的电路结构。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273352A (zh) * 2018-10-25 2019-01-25 山东大学 一种高性能多元非晶金属氧化物薄膜晶体管的制备方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
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CN107425049A (zh) * 2017-05-23 2017-12-01 华南理工大学 一种类岛状电子传输的薄膜晶体管及制备方法
CN107546259A (zh) * 2017-09-06 2018-01-05 深圳市华星光电技术有限公司 Igzo薄膜晶体管及其制作方法
CN109817723B (zh) * 2019-01-24 2022-07-05 北京京东方技术开发有限公司 一种薄膜晶体管及其制备方法、阵列基板和显示装置
CN110161761A (zh) * 2019-05-10 2019-08-23 香港科技大学 液晶显示面板及其制作方法以及显示设备
CN112802904A (zh) * 2020-12-29 2021-05-14 重庆先进光电显示技术研究院 薄膜晶体管器件的制作方法、薄膜晶体管器件及显示装置
CN113707724B (zh) * 2021-07-14 2024-03-26 山东师范大学 一种氧化物薄膜晶体管及其制备方法与应用
CN113745156A (zh) * 2021-08-23 2021-12-03 Tcl华星光电技术有限公司 显示面板及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100187523A1 (en) * 2009-01-23 2010-07-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110062992A1 (en) * 2009-09-16 2011-03-17 Semiconductor Energy Laboratory Co., Ltd. Logic circuit, light emitting device, semiconductor device, and electronic device
US20110230021A1 (en) * 2009-04-17 2011-09-22 Huaxiang Yin Inverter, method of manufacturing the same, and logic circuit including the inverter
CN102646683A (zh) * 2012-02-02 2012-08-22 京东方科技集团股份有限公司 一种阵列基板及其制造方法

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1155095A (zh) * 1989-11-29 1997-07-23 纳幕尔杜邦公司 电-光调制器
JP2000311992A (ja) * 1999-04-26 2000-11-07 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US6531365B2 (en) * 2001-06-22 2003-03-11 International Business Machines Corporation Anti-spacer structure for self-aligned independent gate implantation
KR100845557B1 (ko) * 2002-02-20 2008-07-10 삼성전자주식회사 액티브 매트릭스형 유기전계발광 표시장치 및 그 제조방법
KR100659759B1 (ko) * 2004-10-06 2006-12-19 삼성에스디아이 주식회사 바텀 게이트형 박막트랜지스터, 그를 구비하는평판표시장치 및 박막트랜지스터의 제조방법
US8222646B2 (en) * 2005-07-08 2012-07-17 The Hong Kong University Of Science And Technology Thin-film transistors with metal source and drain and methods of fabrication
KR101236427B1 (ko) * 2006-05-10 2013-02-22 삼성디스플레이 주식회사 박막 트랜지스터용 게이트 절연막의 제조방법 및 이를이용한 박막 트랜지스터의 제조방법
JP5127183B2 (ja) * 2006-08-23 2013-01-23 キヤノン株式会社 アモルファス酸化物半導体膜を用いた薄膜トランジスタの製造方法
CN101217112A (zh) * 2007-01-04 2008-07-09 中国科学院微电子研究所 一种纳米尺度W/TiN复合难熔金属栅制备方法
JP5213422B2 (ja) * 2007-12-04 2013-06-19 キヤノン株式会社 絶縁層を有する酸化物半導体素子およびそれを用いた表示装置
KR101490112B1 (ko) * 2008-03-28 2015-02-05 삼성전자주식회사 인버터 및 그를 포함하는 논리회로
JP5331382B2 (ja) * 2008-05-30 2013-10-30 富士フイルム株式会社 半導体素子の製造方法
KR100958006B1 (ko) * 2008-06-18 2010-05-17 삼성모바일디스플레이주식회사 박막 트랜지스터, 그의 제조 방법 및 박막 트랜지스터를구비하는 평판 표시 장치
CN101478005B (zh) * 2009-02-13 2010-06-09 北京大学深圳研究生院 一种金属氧化物薄膜晶体管及其制作方法
JPWO2011039853A1 (ja) * 2009-09-30 2013-02-21 キヤノン株式会社 薄膜トランジスタ
KR20110093113A (ko) * 2010-02-11 2011-08-18 삼성전자주식회사 박막 트랜지스터 기판 및 이의 제조 방법
US9093539B2 (en) * 2011-05-13 2015-07-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102683423A (zh) * 2012-05-08 2012-09-19 东莞彩显有机发光科技有限公司 一种顶栅结构金属氧化物薄膜晶体管及其制作方法
CN104934481B (zh) * 2014-03-21 2017-10-13 北京大学深圳研究生院 一种薄膜晶体管及其制备方法
CN104157699B (zh) * 2014-08-06 2019-02-01 北京大学深圳研究生院 一种背沟道刻蚀型薄膜晶体管及其制备方法
CN104851809A (zh) * 2015-04-09 2015-08-19 信利(惠州)智能显示有限公司 薄膜晶体管及其制作方法、以及阵列基板与显示装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100187523A1 (en) * 2009-01-23 2010-07-29 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US20110230021A1 (en) * 2009-04-17 2011-09-22 Huaxiang Yin Inverter, method of manufacturing the same, and logic circuit including the inverter
US20110062992A1 (en) * 2009-09-16 2011-03-17 Semiconductor Energy Laboratory Co., Ltd. Logic circuit, light emitting device, semiconductor device, and electronic device
CN102646683A (zh) * 2012-02-02 2012-08-22 京东方科技集团股份有限公司 一种阵列基板及其制造方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
LEI LU: "A Bottom-Gate Indium-Gallium-Zinc Oxide Thin-Film Transistor With an Inherent Etch-Stop and Annealing-Induced Source and Drain Regions", 《IEEE TRANSACTIONS ON ELECTRON DEVICES》 *
XIN HE: "Implementation of Multi-threshold Voltage a-IGZO TFTs with Oxygen Plasma Treatment", 《INTERNATIONAL CONFERENCE ON SOLID STATE DEVICES AND MATERIALS》 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109273352A (zh) * 2018-10-25 2019-01-25 山东大学 一种高性能多元非晶金属氧化物薄膜晶体管的制备方法

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