CN104576399A - 一种薄膜晶体管及其制造方法 - Google Patents

一种薄膜晶体管及其制造方法 Download PDF

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CN104576399A
CN104576399A CN201410832468.7A CN201410832468A CN104576399A CN 104576399 A CN104576399 A CN 104576399A CN 201410832468 A CN201410832468 A CN 201410832468A CN 104576399 A CN104576399 A CN 104576399A
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film transistor
amorphous silicon
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CN104576399B (zh
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王迪
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Kunshan Govisionox Optoelectronics Co Ltd
Kunshan Guoxian Photoelectric Co Ltd
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Abstract

本发明公开了一种薄膜晶体管及其制造方法，包括：在基板上制作缓冲层；在缓冲层上制作经离子掺杂的多晶硅层，经离子掺杂的多晶硅层掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布；刻蚀多晶硅层，形成凹字形硅岛，凹字形硅岛的下陷部分为沟道区，凸起部分为源漏区；在凹字形硅岛上依次形成栅极绝缘层、栅极层、层间绝缘层和源漏极。本发明的优点是：采用离子注入工艺或者在PECVD工艺中控制掺杂浓度，以实现掺杂离子浓度的纵向梯度，省去或减少离子注入次数；同时，可减少薄膜晶体管的工艺光掩模数目，并降低工艺复杂性；而且，纵向的浓度梯度会形成LDD结构，降低TFT漏电流。

Description

一种薄膜晶体管及其制造方法
技术领域
本发明涉及半导体领域，特别设计一种薄膜晶体管及其制造方法。
背景技术
薄膜晶体管作为应用在液晶显示器中的驱动元件被广泛地应用在日常生活中，一般来说，薄膜晶体管至少具有栅极、源极、漏极以及沟道等构件，其中可通过控制栅极的电压来改变沟道的导电性，以使源极与漏极之间形成导通（开）或绝缘（关）的状态，此外，通常还会在沟道上形成一具有N型掺杂或P型掺杂的欧姆接触层，以减少沟道与源极、或沟道与漏极间的接触电阻。
低温多晶硅薄膜晶体管（Low Temperature Poly-silicon Thin Filmtransistor, LTPS TFT）具有低功率消耗和低电磁干扰的特点，在元件缩小化，面板开口率，画面品质与解析度上具有很大优势，因此，其工艺的发展与改良得到了更加广泛的重视。但是，现有的制造LTPS-TFT的工艺中，对于未掺杂的p-Si，载流子浓度低，导致迁移率低，不能满足AMOLED对TFT开态电流要求。此外，也有采用离子注入进行重掺杂，在源/漏极与p-Si间形成欧姆接触，或者采用轻掺杂漏区（Lightly Doped Drain，LDD）结构但是，这些方法需要进行至少三次不同剂量的掺杂，且增加至少一道掩膜工序，由此增加了制造工艺的复杂性。
发明内容
有鉴于此，本发明的主要目的在于提供一种薄膜晶体管及其制造方法，其能够减少离子注入次数，降低工艺复杂性，同时，形成垂直方向的LDD结构，减小TFT漏电流。
为达到上述目的，本发明提供一种薄膜晶体管的制备方法，包括如下步骤：
步骤一，在基板上制作缓冲层；
步骤二，在所述缓冲层上制作经离子掺杂的多晶硅层，所述经离子掺杂的多晶硅层掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布；
步骤三，刻蚀所述多晶硅层，形成凹字形硅岛，所述凹槽的下陷部分为沟道区，所述凹槽的突出部分为源漏区；
步骤四，在所述凹字形硅岛上依次形成栅极绝缘层、栅极层、层间绝缘层和源漏极。
其中一个实施例中，所述步骤二包括如下步骤：
在所述缓冲层上制作第一非晶硅层；
晶化所述第一非晶硅层，所述第一非晶硅层转变为多晶硅层；
在所述多晶硅层上沉积阻挡层；
对所述多晶硅层进行离子掺杂，使得掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布。
其中一个实施例中，在所述多晶硅层上沉积阻挡层步骤之前，在所述多晶硅层上先沉积第二非晶硅层。
其中一个实施例中，所述第一非晶硅层转变为多晶硅层的晶化方法为准分子激光晶化、固相晶化、金属诱导晶化中的一种。
其中一个实施例中，所述离子掺杂方法为离子注入，控制注入离子剂量使得掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布。
其中一个实施例中，在所述步骤三之前先刻蚀掉所述阻挡层。
其中一个实施例中，所述步骤二包括如下步骤：
在所述缓冲层上沉积非晶硅层，在沉积所述非晶硅层的同时通入掺杂元素气体，对所述非晶硅层进行离子掺杂，控制通入掺杂元素气体浓度使得掺杂离子浓度自非晶硅层的上表面至下表面由高到低呈梯度分布；
晶化所述非晶硅层，完成由非晶硅层到多晶硅层的转变，得到掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层。
本发明还提供一种采用上述方法制造的薄膜晶体管。
本发明相对于现有技术具有以下实质性特点和进步：
采用离子注入工艺或者在PECVD沉积工艺中控制掺杂浓度，以实现掺杂离子浓度的纵向梯度，并通过刻蚀形成带有凹槽的硅岛，凹槽中间凹陷部分的掺杂浓度低，作为沟道区，凹槽两边凸起部分的掺杂浓度高，作为源/漏极，形成垂直方向的LDD结构，改善了薄膜晶体管特性，并省去了离子注入次数，减少了工艺光掩模数目，降低了工艺步骤及复杂性；或直接在沉积非晶硅时进行掺杂，工艺集成到PECVD中，工艺兼容性好。
附图说明
图1A至图1E为本发明第一实施例的薄膜晶体管的制造流程示意图；
图2A至图2E为本发明第二实施例的薄膜晶体管的制造流程示意图；
图3A至图3E为本发明第三实施例的薄膜晶体管的制造流程示意图。
具体实施方式
本发明的保护核心为：形成掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层，并将该多晶硅层刻蚀成凹字形硅岛，凹槽的下陷部分为低掺杂的沟道区，凹槽的突出部分为高掺杂的源漏区，并在源漏区的垂直方向形成LDD结构，简化工艺，改善TFT特性。
第一实施例
图1A至图1E为本发明第一实施例的薄膜晶体管的制造流程示意图。
参照图1A所示，在基板1上依次沉积缓冲层2和3。基板1的材质可为玻璃、石英、有机聚合物、或是不透光/反射材料。缓冲层2和3的形成可采用低压化学气相淀积工艺或离子增长型化学气相淀积工艺，缓冲层可阻挡基板所含的杂质进入多晶硅层41中。在具体的实施例中，缓冲层可以是单层氧化硅或氧化硅/氮化硅的双层结构。然后在缓冲层2和3上沉积非晶硅层，对非晶硅层进行晶化，晶化方法可选自准分子激光晶化、固相晶化、金属诱导晶化中的任一种，或其他能将非晶硅转变为多晶硅的晶化方法。非晶硅层经晶化后转变为多晶硅层4，多晶硅层4的厚度为1~1000 ?。在多晶硅层4上覆盖阻挡层4’。阻挡层4’的材料包含氧化硅、氮化硅、氮氧化硅，或其它可适用的材料，优选地，阻挡层4’为SiO2，厚度为 1~10000?，而较佳的厚度例如是介于1~500?。阻挡层4’的作用为在后续的离子掺杂过程中，离子在阻挡层4’和多晶硅层4中的分布具有一峰值层。然后对多晶硅层4进行离子掺杂。此实施例中，离子掺杂采用离子注入方式。具体地，注入P型掺杂物，掺杂物可以是B离子，或者注入N型沟道，掺杂物可以是P离子或As离子，注入剂量随非晶硅层的沉积由小到大。。优选地，离子注入条件为：P型沟道，B离子注入；剂量：1010~1016cm-3；能量：1~100 keV，均匀性：＜10%;或者N型沟道，P离子、As离子注入，剂量：1010~1016cm-3；能量：1~100 keV，均匀性：＜10%。经离子注入后，去掉阻挡层4’，前述离子分布的峰值层正好位于多晶硅层4的上表面，得到掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层4。
参照图1B所示，采用半曝光方法刻蚀所述掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层4，得到凹字形硅岛4，中间凹陷部分B浓度低，作为沟道区，凹槽两边凸起部分B浓度高，可作为源/漏极，源漏极在垂直方向上掺杂离子浓度自上而下由高到低呈梯度分布，形成LDD结构。
参照图1C所示，在硅岛4上依次沉积栅极绝缘层5和栅极金属层，并采用光刻形成栅极6，其中栅极6或完全覆盖硅岛4的凹槽区域。
优选地，形成栅极金属层的方法例如是先沉积一层导电材料，之后通过微影以及蚀刻程序图案化所述导电材料以形成栅极金属层，基于导电性的考虑，栅极一般是使用金属材料，根据其它实施例，栅极也可以是使用其它导电材料，例如合金、金属材料额氮化物、金属材料的氧化物、金属材料的氮氧化物、或是金属材料与其它导电材料的堆栈层。
参照图1D所示，沉积层间绝缘层7并采用光刻形成接触孔7’，且接触孔底部部分或完全暴露出硅岛4两端源漏区。
参照图1E所示，在层间绝缘层7上级接触孔7’中形成源漏极8，源漏极8与硅岛4的源漏区电连接，继续进行后续制程形成平坦化层9及阳极10，阳极10与源漏极8电连接，以及像素限定层11，形成完整的像素结构。
本实施例减少了离子注入次数，因此减少了光掩膜的使用数量以简化工艺，降低生产成本；此外，本发明形成垂直方向的LDD结构，可降低漏电流。
第二实施例
图2A至图2E为本发明第二实施例的薄膜晶体管的制造流程示意图。
参照图2A所示，在基板1上依次沉积缓冲层2和3。然后在缓冲层2和3上沉积第一非晶硅层，对第一非晶硅层进行晶化。第一非晶硅层经晶化后转变为多晶硅层41。第二实施例与第一实施例的区别在于，在多晶硅层41上沉积阻挡层4’之前先沉积第二非晶硅层42，优选地，第二非晶硅层42的厚度为1~5000 ?，多晶硅层的厚度为1~5000 ?。因为在晶化过程中，如果多晶硅层41太厚则不利于生成均一性良好的多晶硅，但如果多晶硅层41够薄，虽然能形成均一性良好的多晶硅，但后续离子掺杂的步骤中，由于多晶硅层41太薄不利于形成掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层41，因此，在沉积阻挡层4’之前先沉积第二非晶硅层42，然后进行离子掺杂，并去除阻挡层4’，即可得到掺杂离子浓度自第二非晶硅层42上表面至多晶硅层41下表面由高到低呈梯度分布的半导体结构。
参照图2B-2E所示，所示工艺与第一实施例相同，在此不再赘述。
第三实施例
图3A至图3E为本发明第三实施例的薄膜晶体管的制造流程示意图。
本实施例与前述两个实施例的区别在于，形成掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层的方法不同。参照图3A所示，在基板1上依次沉积缓冲层2和3 。然后采用离子增长型化学气相淀积工艺（Plasma Enhanced Chemical Vapor Deposition, PECVD）在缓冲层上沉积非晶硅层，在沉积非晶硅层4的同时，通入掺杂气体，对于p型沟道可以通入含B气体，对于N型掺杂可以通入含P或As等气体，并且控制掺杂气体浓度逐渐增加，最终形成掺杂离子浓度自上表面至下表面由高到低呈梯度分布的非晶硅层，然后对非晶硅层进行晶化，形成多晶硅层4。多晶硅层4中掺杂离子浓度自上表面至下表面由高到低呈梯度分布。参照图3B-3E所示，所示工艺与第一实施例相同，在此不再赘述。
由于本实施例是利用直接在沉积非晶硅层时进行离子掺杂，不仅省略了离子注入工艺，且将工艺集成到PECVD中，具有工艺兼容性好的优点。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。

Claims (8)

1.一种薄膜晶体管的制造方法，其特征在于，包括如下步骤：
步骤一，在基板上制作缓冲层；
步骤二，在所述缓冲层上制作经离子掺杂的多晶硅层，所述经离子掺杂的多晶硅层掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布；
步骤三，刻蚀所述多晶硅层，形成凹字形硅岛，所述凹字形硅岛的下陷部分为沟道区，凸起部分为源漏区；
步骤四，在所述凹字形硅岛上依次形成栅极绝缘层、栅极层、层间绝缘层和源漏极。
2.如权利要求1所述的薄膜晶体管的制造方法，其特征在于，所述步骤二包括如下步骤： 
在所述缓冲层上制作第一非晶硅层；
晶化所述第一非晶硅层，所述第一非晶硅层转变为多晶硅层；
在所述多晶硅层上沉积阻挡层；
对所述多晶硅层进行离子掺杂，掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布。
3.如权利要求2所述的薄膜晶体管的制造方法，其特征在于：在所述多晶硅层上沉积阻挡层步骤之前，在所述多晶硅层上先沉积第二非晶硅层。
4.如权利要求2或3所述的薄膜晶体管的制造方法，其特征在于，所述第一非晶硅层转变为多晶硅层的晶化方法为准分子激光晶化、固相晶化、金属诱导晶化中的一种。
5.如权利要求2或3所述的薄膜晶体管的制造方法，其特征在于，所述离子掺杂方法为离子注入，控制注入离子剂量使得掺杂离子浓度自多晶硅层的上表面至下表面由高到低呈梯度分布。
6.如权利要求2或3所述的薄膜晶体管的制造方法，其特征在于，在所述步骤三之前先刻蚀掉所述阻挡层。
7.如权利要求1所述的薄膜晶体管的制造方法，其特征在于，所述步骤二包括如下步骤：
在所述缓冲层上沉积非晶硅层，在沉积所述非晶硅层的同时通入掺杂元素气体，对所述非晶硅层进行离子掺杂，控制通入掺杂元素气体浓度使得掺杂离子浓度自非晶硅层的上表面至下表面由高到低呈梯度分布；
晶化所述非晶硅层，完成由非晶硅层到多晶硅层的转变，得到掺杂离子浓度自上表面至下表面由高到低呈梯度分布的多晶硅层。
8.一种采用如权利要求1-7任一项所述的方法制造的薄膜晶体管。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105070724A (zh) * 2015-07-16 2015-11-18 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
CN106328586A (zh) * 2016-08-24 2017-01-11 武汉华星光电技术有限公司 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
WO2017020358A1 (zh) * 2015-08-04 2017-02-09 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN110993618A (zh) * 2019-12-04 2020-04-10 武汉华星光电半导体显示技术有限公司 一种tft阵列基板及其制备方法、显示面板
CN113948579A (zh) * 2020-07-17 2022-01-18 京东方科技集团股份有限公司 薄膜晶体管及其制备方法和显示装置
US20220077261A1 (en) * 2020-09-08 2022-03-10 Samsung Display Co., Ltd. Display device and manufacturing method thereof
WO2023050238A1 (zh) * 2021-09-29 2023-04-06 京东方科技集团股份有限公司 非晶硅薄膜晶体管及其制备方法、显示面板

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719081A (en) * 1995-11-03 1998-02-17 Motorola, Inc. Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
KR100304123B1 (ko) * 1999-10-22 2001-11-02 이계철 트렌치 구조 및 덮개층을 이용한 박막 트랜지스터 제조방법
CN101232047A (zh) * 2007-01-26 2008-07-30 株式会社半导体能源研究所 发光器件及其制造方法
US20140134808A1 (en) * 2011-06-13 2014-05-15 International Business Machines Corporation Recessed gate field effect transistor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719081A (en) * 1995-11-03 1998-02-17 Motorola, Inc. Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
KR100304123B1 (ko) * 1999-10-22 2001-11-02 이계철 트렌치 구조 및 덮개층을 이용한 박막 트랜지스터 제조방법
CN101232047A (zh) * 2007-01-26 2008-07-30 株式会社半导体能源研究所 发光器件及其制造方法
US20140134808A1 (en) * 2011-06-13 2014-05-15 International Business Machines Corporation Recessed gate field effect transistor

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105070724A (zh) * 2015-07-16 2015-11-18 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
WO2017008368A1 (zh) * 2015-07-16 2017-01-19 深圳市华星光电技术有限公司 Tft基板的制作方法及制得的tft基板
WO2017020358A1 (zh) * 2015-08-04 2017-02-09 深圳市华星光电技术有限公司 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管
CN106328586A (zh) * 2016-08-24 2017-01-11 武汉华星光电技术有限公司 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
WO2018035902A1 (zh) * 2016-08-24 2018-03-01 武汉华星光电技术有限公司 低温多晶硅阵列基板的制备方法、阵列基板以及显示面板
US10020382B1 (en) 2016-08-24 2018-07-10 Wuhan China Star Optoelectronics Technology Co., Ltd Method of manufacturing low temperature poly-silicon array substrate, array substrate, and display panel
CN110993618A (zh) * 2019-12-04 2020-04-10 武汉华星光电半导体显示技术有限公司 一种tft阵列基板及其制备方法、显示面板
CN110993618B (zh) * 2019-12-04 2022-10-04 武汉华星光电半导体显示技术有限公司 一种tft阵列基板及其制备方法、显示面板
CN113948579A (zh) * 2020-07-17 2022-01-18 京东方科技集团股份有限公司 薄膜晶体管及其制备方法和显示装置
CN113948579B (zh) * 2020-07-17 2023-06-23 京东方科技集团股份有限公司 薄膜晶体管及其制备方法和显示装置
US20220077261A1 (en) * 2020-09-08 2022-03-10 Samsung Display Co., Ltd. Display device and manufacturing method thereof
US11715739B2 (en) * 2020-09-08 2023-08-01 Samsung Display Co., Ltd. Display device and manufacturing method thereof
WO2023050238A1 (zh) * 2021-09-29 2023-04-06 京东方科技集团股份有限公司 非晶硅薄膜晶体管及其制备方法、显示面板

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