CN107393830A - 薄膜晶体管的制备方法 - Google Patents
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Abstract
本发明提供一种薄膜晶体管的制备方法,属于显示技术领域。本发明的薄膜晶体管的制备方法,包括在基底上通过构图工艺形成有源层的图形;对有源层的沟道区进行离子掺杂;形成栅极绝缘层;通过构图工艺,形成包括栅极的图形;对有源层的源极接触区和漏极接触区进行离子掺杂;形成层间绝缘层;对形成层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。由于在本发明的薄膜晶体管的制备方法中,对有源层中所掺杂的离子的结晶和活化是一次工艺完成,不仅可以降低工艺成本,提高工艺效率。
Description
技术领域
本发明属于显示技术领域,具体涉及一种薄膜晶体管的制备方法。
背景技术
随着显示技术的发展,人们对显示画质的需求日益增长,高画质、高分辨率的平板显示装置的需求越来越普遍,也越来越得到显示面板厂家的重视。
薄膜晶体管(Thin Film Transistor,简称TFT)是平板显示面板的主要驱动器件,直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构,制备相应结构的薄膜晶体管的材料也具有多种,例如:非晶硅和多晶硅都是目前常用的薄膜晶体管制备材料。然而,非晶硅本身存在很多无法避免的缺点,比如:低迁移率、低稳定性等;与此相比,低温多晶硅(Low Temperature Poly-Silicon,简称LTPS)具有较高的迁移率及稳定性,其迁移率可达非晶硅的几十甚至几百倍。因此,采用低温多晶硅材料形成薄膜晶体管的技术得到了迅速发展,由LTPS衍生的新一代液晶显示装置(Liquid Crystal Display:简称LCD)或有机电致发光显示装置(Organic Light-Emitting Diode:简称OLED)成为重要的显示技术,尤其是OLED显示装置,由于OLED具有超薄、低功耗、同时自身发光等特点,备受用户的青睐。
虽然低温多晶硅薄膜晶体管具有上述优点,但是,在低温多晶硅薄膜晶体管(LTPSTFT)的制备工艺中,通常在对a-Si沉积完成后进行去氢处理,之后便进行激光退火(ELA)过程,此时a-Si结晶后会在产生较大的晶界凸起,因此将会影响薄膜晶体管的性能。而且,在对薄膜晶体管的有源层的沟道区、源极接触区、漏极接触区进行离子掺杂之后还需要活化的过程以激活所掺杂的离子,此时不仅增加了工艺成本,而且工艺效率低。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一,提供一种工艺简单、成本较低的薄膜晶体管的制备方法。
解决本发明技术问题所采用的技术方案是一种薄膜晶体管的制备方法,包括:
在基底上,通过构图工艺形成有源层的图形;
对所述有源层的沟道区进行离子掺杂;
形成栅极绝缘层;
通过构图工艺,形成包括栅极的图形;
对所述有源层的源极接触区和漏极接触区进行离子掺杂;
形成层间绝缘层;
对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
优选的是,所述对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化的步骤,具体包括:
对所述基底背离所述有源层的一侧进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
进一步优选的是,在所述对所述基底背离所述有源层的一侧进行激光退火的步骤之前还包括:
在所述层间绝缘层上形成表面保护层的步骤。
优选的是,所述对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化的步骤,具体包括:
在所述层间绝缘层上形成光刻胶层,并通过掩模板对所述有源层进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
优选的是,所述激光退火的扫描能量为350-450mJ/cm2。
优选的是,对所述有源层的沟道区进行离子掺杂的掺杂电压为12-15KeV;剂量为1E12-2E12n/cm2;气体源为BF3;对所述有源层的源极接触区和漏极接触区进行离子掺杂的掺杂电压为25-30KeV;剂量为4E14-5E14n/cm2;气体源为BF3。
优选的是,所述有源层的材料在经过激光退火结晶后形成P-Si。
优选的是,所述在基底上,通过构图工艺形成有源层的图形的步骤,具体包括:
在基底上形成半导体材料层;
对完成上述步骤的基底进行去氢处理;
通过构图工艺形成有源层的图形。
优选的是,所述去氢处理的温度为400-450℃;时间为60-90min。
优选的是,在所述在基底上,通过构图工艺形成有源层的图形的步骤之前,还包括:
在所述基底上形成缓冲层的步骤。
优选的是,在所述对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子结晶并活化的步骤之后,还包括:
在所述栅极绝缘层和层间绝缘层中刻蚀过孔,所述过孔的位置与所述有源层的源极接触区、漏极接触区位置对应;
通过构图工艺形成包括源极和漏极的步骤;其中,所述源极通过与所述源极接触区对应的过孔与所述有源层连接,所述漏极通过与所述漏极接触区对应的过孔与所述有源层连接。
本发明具有如下有益效果:
由于在本发明的薄膜晶体管的制备方法中,在形成层间绝缘层之后对基底进行激光退火,以使有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子结晶并活化,也即对有源层中所掺杂的离子的结晶和活化是一次工艺完成,此时不仅可以降低工艺成本,提高工艺效率,而且在形成层间绝缘层之后对基底进行激光退火,可以有效的改善有源层与栅极绝缘层之间的接触界面,以提高薄膜晶体管的特性(改善漏电流),同时可以避免a-Si结晶后会在产生较大的晶界凸起的问题。
附图说明
图1为本发明的实施例1的薄膜晶体管的制备方法的流程图;
图2为本发明的实施例1的薄膜晶体管的制备方法中步骤一的示意图;
图3为本发明的实施例1的薄膜晶体管的制备方法中步骤二的示意图;
图4为本发明的实施例1的薄膜晶体管的制备方法中步骤三的示意图;
图5为本发明的实施例1的薄膜晶体管的制备方法中步骤四的示意图;
图6为本发明的实施例1的薄膜晶体管的制备方法中步骤五的示意图;
图7为本发明的实施例1的薄膜晶体管的制备方法中步骤六的示意图;
图8为本发明的实施例1的薄膜晶体管的制备方法中步骤七的示意图;
图9为本发明的实施例1的薄膜晶体管的制备方法中步骤八的示意图。
其中附图标记为:10、基底;1、缓冲层;2、有源层;3、栅极绝缘层;4、栅极;5、层间绝缘层;51、52、过孔;61、源极;62、漏极。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案,下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1:
如图1所示,本实施例提供一种低温多晶硅薄膜晶体管的制备方法,其包括以下步骤:在基底10上,通过构图工艺形成有源层2的图形;对有源层2的沟道区进行离子掺杂;形成栅极绝缘层3;通过构图工艺,形成包括栅极4的图形;对有源层2的源极接触区和漏极接触区进行离子掺杂;形成层间绝缘层5;对形成层间绝缘层5的基底10,进行激光退火,以使有源层2的材料结晶的同时,使得有源层2的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
由于在本实施例的薄膜晶体管的制备方法中,在形成层间绝缘层5之后对基底10进行激光退火,以使有源层2的材料结晶的同时,使得有源层2的沟道区、源极接触区、漏极接触区中所掺杂的离子活化,也即对有源层2中所掺杂的离子的结晶和活化是一次工艺完成,此时不仅可以降低工艺成本,提高工艺效率,而且在形成层间绝缘层5之后对基底10进行激光退火,可以有效的改善有源层2与栅极绝缘层3之间的接触界面,以提高薄膜晶体管的特性(改善漏电流),同时可以避免a-Si结晶后会在产生较大的晶界凸起的问题。
在此需要说明的是,在本实施例中,构图工艺,可只包括光刻工艺,或,包括光刻工艺以及刻蚀步骤,同时还可以包括打印、喷墨等其他用于形成预定图形的工艺;光刻工艺,是指包括成膜、曝光、显影等工艺过程的利用光刻胶、掩模板、曝光机等形成图形的工艺。可根据本实施例中所形成的结构选择相应的构图工艺。
以下结合具体实现方式,对本申请中薄膜晶体管的制备方法进行说明。
步骤一、在基底10上依次沉积缓冲层1和半导体材料层(a-Si膜层),通过构图工艺形成包括有源层2的图形,如图2所示。
在该步骤中,基底10采用玻璃等透明材料制成、且经过预先清洗。具体的,在基底10上采用溅射方式、热蒸发方式、等离子体增强化学气相沉积(Plasma Enhanced VaporDeposition:简称PECVD)方式、低压化学气相沉积(Low Pressure Chemical VaporDeposition:简称LPCVD)方式、大气压化学气相沉积(Atmospheric Pressure ChemicalVapor Deposition:简称APCVD)方式或电子回旋谐振化学气相沉积(Electron CyclotronResonance Chemical Vapor Deposition:简称ECR-CVD)方式形成缓冲层1和半导体材料层,之后通过构图工艺(成膜、曝光、显影、湿法刻蚀或干法刻蚀)形成有源层2的图形,最后对有源层2进行去氢处理,以使有源层2中的氢含量<2%。
其中,缓冲层1的可以采用氮化硅和氧化硅两层结构,氮化硅的厚度为氧化硅的厚度为半导体材料层的厚度为对有源层2去氢温度为400-450℃,时间为60-90min。
步骤二、对有源层2的沟道区进行离子掺杂,如图3所示。其中,对有源层2的沟道区进行离子掺杂的掺杂电压为12-15KeV;剂量为1E12-2E12n/cm2;气体源为BF3。
步骤三、形成栅极绝缘层3和栅极4金属薄膜,并通过构图工艺形成包括栅极4的图形,如图4所示。
具体的,在该步骤中,首先,采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式在有源层2的上方形成栅绝缘层;接着,采用溅射方式、热蒸发方式、等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式形成栅金属薄膜,最后采用构图工艺形成包括栅极4的图形。
其中,栅极绝缘层3包括沿背离基底10上依次设置的二氧化硅层和氮化硅层,二氧化硅层的厚度为氮化硅层的厚度为栅极4的材料采用Mo,厚度为2200-2400。
步骤四、如图5所示,以栅极4图形作为掩模板,采用离子注入的方式,对有源层2的源极接触区和漏极接触区进行离子掺杂,以增强有源层2与源极和漏极的欧姆接触,保证P-Si与源极、漏极形成良好的欧姆接触。其中,对所述有源层2的源极接触区和漏极接触区进行离子掺杂的掺杂电压为25-30KeV;剂量为4E14-5E14n/cm2;气体源为BF3。
其中,离子注入方式包括具有质量分析仪的离子注入方式、不具有质量分析仪的离子云式注入方式、等离子注入方式或固态扩散式注入方式。
步骤五、采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式或溅射方式在栅极4上方形成层间绝缘层5,如图6所示。其中,层间绝缘层5包括沿背离基底10上依次设置的二氧化硅层和氮化硅层,二氧化硅层的厚度为氮化硅层的厚度为
步骤六、将完成上述步骤的基底10翻转,对着基底10侧进行激光退火,以使有源层2材料从a-Si到P-Si的转化的同时,以使有源层2沟道区、源极接触区、漏极接触区中所掺杂的离子的活化,如图7所示。
步骤七、在栅极绝缘层3和层间绝缘层5中刻蚀过孔51、52,所述过孔的位置与所述有源层2的源极接触区、漏极接触区位置对应,如图8所示。
步骤八、在层间绝缘层5上方,通过构图工艺形成包括源极61和漏极62的图形,如图9所示。
具体的,采用等离子体增强化学气相沉积方式、低压化学气相沉积方式、大气压化学气相沉积方式或电子回旋谐振化学气相沉积方式源漏金属薄膜,之后同构构图工艺形成包括源极和漏极的图形。
至此完成薄膜晶体管的制备。
在上述薄膜晶体管的制备方法中在形成层间绝缘层5之后对基底10进行激光退火,以使有源层2的材料结晶的同时,使得有源层2的沟道区、源极接触区、漏极接触区中所掺杂的离子活化,也即对有源层2中所掺杂的离子的结晶和活化是一次工艺完成,此时不仅可以降低工艺成本,提高工艺效率,而且在形成层间绝缘层5之后对基底10进行激光退火,可以有效的改善有源层2与栅极绝缘层3之间的接触界面,以提高薄膜晶体管的特性(改善漏电流),同时可以避免a-Si结晶后会在产生较大的晶界凸起的问题。
在此需要说明的是,步骤六也不局限于上述一种方式,还可以在层间绝缘层5上形成光刻胶层,在光刻胶层上方通过掩模板对所述有源层2进行激光退火,以使所述有源层2的沟道区、源极接触区、漏极接触区中所掺杂的离子结晶并活化。或者,在层间绝缘层5上形成表面保护层之后再对基底10背离有源层2侧进行激光退火工艺。
可以理解的是,以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式,然而本发明并不局限于此。对于本领域内的普通技术人员而言,在不脱离本发明的精神和实质的情况下,可以做出各种变型和改进,这些变型和改进也视为本发明的保护范围。
Claims (11)
1.一种薄膜晶体管的制备方法,其特征在于,包括:
在基底上,通过构图工艺形成有源层的图形;
对所述有源层的沟道区进行离子掺杂;
形成栅极绝缘层;
通过构图工艺,形成包括栅极的图形;
对所述有源层的源极接触区和漏极接触区进行离子掺杂;
形成层间绝缘层;
对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
2.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化的步骤,具体包括:
对所述基底背离所述有源层的一侧进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
3.根据权利要求2所述的薄膜晶体管的制备方法,其特征在于,在所述对所述基底背离所述有源层的一侧进行激光退火的步骤之前还包括:
在所述层间绝缘层上形成表面保护层的步骤。
4.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化的步骤,具体包括:
在所述层间绝缘层上形成光刻胶层,并通过掩模板对所述有源层进行激光退火,以使所述有源层的材料结晶的同时,使得所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子活化。
5.根据权利要求1-4中任一项所述的薄膜晶体管的制备方法,其特征在于,所述激光退火的扫描能量为350-450mJ/cm2。
6.根据权利要求1-4中任一项所述的薄膜晶体管的制备方法,其特征在于,对所述有源层的沟道区进行离子掺杂的掺杂电压为12-15KeV;剂量为1E12-2E12n/cm2;气体源为BF3;对所述有源层的源极接触区和漏极接触区进行离子掺杂的掺杂电压为25-30KeV;剂量为4E14-5E14n/cm2;气体源为BF3。
7.根据权利要求1-4中任一项所述的薄膜晶体管的制备方法,其特征在于,所述有源层的材料在经过激光退火结晶后形成P-Si。
8.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,所述在基底上,通过构图工艺形成有源层的图形的步骤,具体包括:
在基底上形成半导体材料层;
对完成上述步骤的基底进行去氢处理;
通过构图工艺形成有源层的图形。
9.根据权利要求8所述的薄膜晶体管的制备方法,其特征在于,所述去氢处理的温度为400-450℃;时间为60-90min。
10.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,在所述在基底上,通过构图工艺形成有源层的图形的步骤之前,还包括:
在所述基底上形成缓冲层的步骤。
11.根据权利要求1所述的薄膜晶体管的制备方法,其特征在于,在所述对形成所述层间绝缘层的基底,进行激光退火,以使所述有源层的沟道区、源极接触区、漏极接触区中所掺杂的离子结晶并活化的步骤之后,还包括:
在所述栅极绝缘层和层间绝缘层中刻蚀过孔,所述过孔的位置与所述有源层的源极接触区、漏极接触区位置对应;
通过构图工艺形成包括源极和漏极的步骤;其中,所述源极通过与所述源极接触区对应的过孔与所述有源层连接,所述漏极通过与所述漏极接触区对应的过孔与所述有源层连接。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321033A (ja) * | 1994-05-26 | 1995-12-08 | Semiconductor Energy Lab Co Ltd | 半導体装置作製方法及び電気光学装置の作製方法 |
JP2003332351A (ja) * | 2003-04-24 | 2003-11-21 | Semiconductor Energy Lab Co Ltd | 絶縁ゲイト型半導体装置の作製方法 |
CN1682259A (zh) * | 2002-09-20 | 2005-10-12 | 株式会社半导体能源研究所 | 显示器件及其制造方法 |
CN101335212A (zh) * | 2005-09-29 | 2008-12-31 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
CN103700706A (zh) * | 2013-12-16 | 2014-04-02 | 京东方科技集团股份有限公司 | 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置 |
CN103839825A (zh) * | 2014-02-24 | 2014-06-04 | 京东方科技集团股份有限公司 | 一种低温多晶硅薄膜晶体管、阵列基板及其制作方法 |
CN104900491A (zh) * | 2015-05-05 | 2015-09-09 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、显示装置 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002231628A (ja) * | 2001-02-01 | 2002-08-16 | Sony Corp | 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置 |
KR20070003784A (ko) * | 2003-12-15 | 2007-01-05 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 광센서를 가지는 능동 매트릭스 픽셀 디바이스 |
TW200743154A (en) * | 2006-05-10 | 2007-11-16 | Toppoly Optoelectronics Corp | System for displaying image and laser annealing method for LTPS |
US20180350685A1 (en) * | 2011-06-28 | 2018-12-06 | Monolithic 3D Inc. | 3d semiconductor device and system |
JP6471379B2 (ja) * | 2014-11-25 | 2019-02-20 | 株式会社ブイ・テクノロジー | 薄膜トランジスタ、薄膜トランジスタの製造方法及びレーザアニール装置 |
US10355034B2 (en) * | 2017-08-21 | 2019-07-16 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Low-temperature polycrystalline silicon array substrate and manufacturing method, display panel |
-
2017
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07321033A (ja) * | 1994-05-26 | 1995-12-08 | Semiconductor Energy Lab Co Ltd | 半導体装置作製方法及び電気光学装置の作製方法 |
CN1682259A (zh) * | 2002-09-20 | 2005-10-12 | 株式会社半导体能源研究所 | 显示器件及其制造方法 |
JP2003332351A (ja) * | 2003-04-24 | 2003-11-21 | Semiconductor Energy Lab Co Ltd | 絶縁ゲイト型半導体装置の作製方法 |
CN101335212A (zh) * | 2005-09-29 | 2008-12-31 | 株式会社半导体能源研究所 | 半导体器件及其制造方法 |
CN103700706A (zh) * | 2013-12-16 | 2014-04-02 | 京东方科技集团股份有限公司 | 薄膜晶体管和阵列基板及其各自制备方法、以及显示装置 |
CN103839825A (zh) * | 2014-02-24 | 2014-06-04 | 京东方科技集团股份有限公司 | 一种低温多晶硅薄膜晶体管、阵列基板及其制作方法 |
CN104900491A (zh) * | 2015-05-05 | 2015-09-09 | 京东方科技集团股份有限公司 | 薄膜晶体管及其制作方法、显示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112038405A (zh) * | 2020-08-19 | 2020-12-04 | 深圳市紫光同创电子有限公司 | 场效应晶体管及其制备方法、静态随机存储器、集成电路 |
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