WO2016173322A1 - 一种阵列基板及其制作方法、及显示装置 - Google Patents

一种阵列基板及其制作方法、及显示装置 Download PDF

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Publication number
WO2016173322A1
WO2016173322A1 PCT/CN2016/075754 CN2016075754W WO2016173322A1 WO 2016173322 A1 WO2016173322 A1 WO 2016173322A1 CN 2016075754 W CN2016075754 W CN 2016075754W WO 2016173322 A1 WO2016173322 A1 WO 2016173322A1
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Prior art keywords
substrate
gate
orthographic projection
insulating pattern
pattern
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PCT/CN2016/075754
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English (en)
French (fr)
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刘政
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京东方科技集团股份有限公司
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Priority to US15/309,499 priority Critical patent/US9880439B2/en
Publication of WO2016173322A1 publication Critical patent/WO2016173322A1/zh

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    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L2029/7863—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD

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  • the realization of LCD is generally to add an ion implantation process on the existing basis. That is, after the gate metal etching, the gate is used for light doping, and then, based on the addition of a mask, the reverse doping (PR) is used as a mask for heavy doping.
  • PR reverse doping
  • Step 2 As shown in FIG. 3B, on the base substrate 1 on which the semiconductor pattern 2 is formed, the first An insulating layer 3.
  • the first insulating layer 3 may be a single layer of silicon oxide, silicon nitride or a combination of the two, and has a thickness of 500 angstroms to 2000 angstroms, preferably a thickness of 600 angstroms to 1500 angstroms (depending on the specific design requirements). thickness of).

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Abstract

一种阵列基板的制作方法包括如下步骤：在衬底基板（1）上依次形成不同层的半导体图形（2）、栅极（4）和第一绝缘图形（5）；半导体图形在衬底基板上的正投影覆盖第一绝缘图形在衬底基板上的正投影，第一绝缘图形在衬底基板上的正投影覆盖栅极在衬底基板上的正投影；以第一绝缘图形和栅极为掩膜，通过一次离子注入工艺对半导体图形进行处理，形成有源层（2C）、重掺杂源极区（2A）、轻掺杂源极区（2B）、重掺杂漏极区（2D）和轻掺杂漏极区（2E）。只通过一次离子注入工艺即可形成具有轻掺杂、重掺杂的源漏极。由于离子注入次数少，故可以减少制造时间，进而降低制造成本。此外，具有轻掺杂、重掺杂的源漏极可降低漏极电流，从而提高显示面板工作的稳定性。

Description

一种阵列基板及其制作方法、及显示装置
相关申请的交叉参考
本申请主张在2015年4月30日在中国提交的中国专利申请号No.201510220042.0的优先权，其全部内容通过引用包含于此。
技术领域
本公开文本涉及液晶显示装置的制作领域，特别是一种阵列基板及其制作方法、及显示装置。
背景技术
在LCD(液晶显示器)或OLED(有机发光二极管)显示器中，每个像素点都是由集成在像素点后面的TFT(Thin Film Transistor，薄膜场效应晶体管)来驱动，从而可以实现高速度、高亮度、高对比度的显示屏幕信息。在现在的生产技术中，多采用多晶硅或非晶硅来制造TFT。多晶硅的载流子迁移率为10-200cm2/V，明显高于非晶硅的载流子迁移率(1cm2/V)，所以多晶硅相对于非晶硅具有更高的电容性和存储性。对于LCD和OLED而言，TFT一般形成于玻璃基板上，由于玻璃的热力学限制，多晶硅TFT的结晶特性及离子注入后退火的过程往往不能得到有效的恢复，则在反偏电压的情况下会出现较大的漏极电流，影响TFT的正常使用。
为了抑制TFT的漏极电流，一般在源极、漏极上分别设置轻掺杂区和重掺杂区，轻掺杂区可承受部分电压，能够抵消一部分漏极电流。
目前，实现LCD一般是在现有基础上增加一道离子注入工艺。即在栅极金属刻蚀后，先利用栅极进行轻掺杂，随后在增加一次掩膜(mask)的基础上，再利用反转光刻胶(PR)作为掩膜进行重掺杂。可见，现有技术的制作方法至少需要两次离子注入工艺，而离子注入工艺耗时长，成本高，制约了阵列基板的大规模生产。
发明内容
(一)要解决的技术问题
本公开文本要解决的技术问题是提供一种阵列基板及其制作方法、及显示装置，能够通过一次离子注入工艺形成包括轻掺杂区以及重掺杂区的薄膜晶体管的源极、漏极。
(二)技术方案
为解决上述技术问题，本公开文本的实施例提供一种阵列基板的制作方法，包括：
在衬底基板上依次形成不同层设置的半导体图形、栅极和第一绝缘图形，所述半导体图形与所述栅极相互绝缘；所述半导体图形在所述衬底基板上的正投影覆盖所述第一绝缘图形在所述衬底基板上的正投影，所述第一绝缘图形在所述衬底基板上的正投影覆盖所述栅极在所述衬底基板上的正投影；以及
以所述第一绝缘图形和所述栅极为掩膜，通过一次离子注入工艺对所述半导体图形进行处理，形成有源层、重掺杂源极区、轻掺杂源极区、重掺杂漏极区、轻掺杂漏极区，
其中，在所述离子注入工艺处理后，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重合，所述轻掺杂源极区和所述轻掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影重合但不与所述栅极在所述衬底基板上的正投影重合，所述重掺杂源极区和重掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影、所述栅极在所述衬底基板上的正投影均不重合。
可选的，所述制作方法还包括：
形成存储电容的步骤，所述存储电容包括上极板、下极板以及间隔所述上极板和所述下极板的第二绝缘图形；
其中，所述下极板与所述栅极为同层同材料形成，所述第一绝缘图形与所述第二绝缘图形为同层同材料形成。
可选的，所述制作方法还包括：
在衬底基板上形成半导体图形；
在形成有半导体图形的衬底基板上，形成第一绝缘层；
在形成有第一绝缘层的衬底基板上，形成由同一材料层构成的栅极以及下极板；
在形成有所述栅极和所述下极板的衬底基板上，形成由第二绝缘层构成的第一绝缘图形以及第二绝缘图形，所述第一绝缘图形覆盖所述栅极，所述第二绝缘图形覆盖所述下极板；
以所述第一绝缘图形和所述栅极为掩膜，通过一次离子注入工艺对所述半导体图形进行处理，形成有源层，以及分别具有重掺杂区和轻掺杂区的源极、漏极；以及
在所述第二绝缘图形上形成所述上极板。
可选的，形成所述第一绝缘图形和所述第二绝缘图形的构图工艺与形成所述上极板的构图工艺为采用同一掩膜板。
可选的，所述栅极的材料包括钼和/或铝，且所述栅极的厚度为1000埃～5000埃；
所述第一绝缘层的材料包括氧化硅和/或氮化硅，且所述第一绝缘层的厚度为500埃～2000埃。
可选的，所述栅极的厚度为1500埃～4000埃，并且所述第一绝缘层的厚度为600埃～1500埃。
其中，所述离子注入工艺的注入介质为含硼元素和/或含磷元素的气体，注入能量范围为10～200keV，注入剂量范围为1×1011～1×1020atoms/cm3。
此外，本公开文本的另一实施例还提供一种采用上述制作方法制得的阵列基板，所述阵列基板包括衬底基板，以及形成在衬底基板上的薄膜晶体管，所述薄膜晶体管包括栅极、源极、漏极和有源层；所述源极包括重掺杂源极区和轻掺杂源极区，所述漏极包括重掺杂漏极区和轻掺杂漏极区；所述阵列基板还包括：
设置在所述栅极上方的第一绝缘图形，其在所述衬底基板上的正向投影覆盖所述栅极在所述衬底基板上的正向投影；
其中，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重合，所述轻掺杂源极区和所述轻掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影重合但不与所述 栅极在所述衬底基板上的正投影重合，所述重掺杂源极区和重掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影、所述栅极在所述衬底基板上的正投影均不重合。
可选的，所述阵列基板还包括：
形成在所述衬底基板上的存储电容，所述存储电容包括上极板、下极板以及间隔所述上极板和所述下极板的第二绝缘图形；
所述下极板与所述栅极为同层同材料形成，所述第一绝缘图形与所述第二绝缘图形为同层同材料形成。
此外，本公开文本的另一实施例还提供一种包括上述阵列基板的显示装置。
(三)有益效果
本公开文本的上述技术方案的有益效果如下：
本公开文本的方案只需要一次离子注入工艺即可在薄膜晶体管的源极、漏极上形成轻掺杂区以及重掺杂区。由于离子注入次数降低，故可以减少制造时间，进而降低制造成本，并且薄膜晶体管的源极、漏极在设置有重掺杂区和轻掺杂区后，可降低漏极电流，从而提高显示装置工作的稳定性。
附图说明
为了更清楚地说明本公开文本实施例或现有技术中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开文本的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1和图2为根据本公开文本实施例的阵列基板制作方法的流程示意图；
图3A至图3F为根据本公开文本实施例的阵列基板制作方法的详细流程示意图；
图4为根据本公开文本实施例的阵列基板结构示意图；以及
图5为根据本公开文本实施例的阵列基板的另一结构示意图。
具体实施方式
下面结合附图和实施例，对本公开文本的具体实施方式做进一步描述。以下实施例仅用于说明本公开文本，但不用来限制本公开文本的范围。
为使本公开文本实施例的目的、技术方案和优点更加清楚，下面将结合本公开文本实施例的附图，对本公开文本实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开文本的一部分实施例，而不是全部的实施例。基于所描述的本公开文本的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开文本保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开文本所属领域内具有一般技能的人士所理解的通常意义。本公开文本专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
为使本公开文本要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
参考图1和图2，本公开文本的实施例提供了一种阵列基板的制作方法，包括：
在衬底基板1上依次形成不同层设置的半导体图形2、栅极4和第一绝缘图形5，所述半导体图形2与所述栅极4相互绝缘；所述半导体图形2在所述衬底基板1上的正投影C覆盖所述第一绝缘图形5在所述衬底基板1上的正投影B，所述第一绝缘图形5在所述衬底基板1上的正投影B覆盖所述栅极4在所述衬底基板1上的正投影A；
以所述第一绝缘图形5和所述栅极4为掩膜，通过一次离子注入工艺对所述半导体图形2进行处理，形成有源层2C、重掺杂源极区2A、轻掺杂源极区2B、重掺杂漏极区2D、轻掺杂漏极区2E；
其中，在所述离子注入工艺处理后，所述有源层2C在所述衬底基板1 上的正投影A与所述栅极4在所述衬底基板1上的正投影重合，所述轻掺杂源极区2B和所述轻掺杂漏极区2D在所述衬底基板1上的正投影E1、E2与所述第一绝缘图形5在所述衬底基板上的正投影B重合但不与所述栅极4在所述衬底基板上1的正投影A重合，所述重掺杂源极区2A和重掺杂漏极区2E在所述衬底基板1上的正投影D1、D2与所述第一绝缘图形5在所述衬底基板上的正投影B、所述栅极在所述衬底基板上的正投影A均不重合。
根据本实施例的制作方法只通过一次离子注入工艺即可形成具有轻掺杂、重掺杂的源漏极。由于离子注入次数少，故可以减少制造时间，进而降低制造成本。此外，具有轻掺杂、重掺杂的源漏极可降低漏极电流，从而提高显示面板工作的稳定性。
具体地，针对低温多晶硅薄膜晶体管的阵列基板，还需要在制作过程中，设置存储电容(Storing Capacity，简称Cs)来满足液晶的驱动要求。存储电容包括上极板、下极板以及绝缘所述上极板和所述下极板的第二绝缘图形。目前，存储电容的下极板也需要离子注入后形成，由于薄膜晶体管的半导体图形与存储电容的下极板区域不同，现有技术需分别采用两次离子注入工艺，并且每次离子注入工艺对应有不同的掩膜板，且工艺时间较长。为提高制作效率，并降低成本，下面本公开文本具体实施例提供了一种能够在上述唯一的离子注入工艺中，进一步制作存储电容下极板的方法。
下面结合图3，对本实施例具体的制造方法进行详细说明。
如图3所示，低温多晶硅薄膜晶体管的阵列基板的详细制作步骤包括：
步骤1：如图3A所示，在衬底基板1上形成半导体图形2。半导体图形2的厚度为100埃～3000埃，优选厚度为500埃～1000埃。在执行本步骤中，可先通过PECVD(等离子体增强化学气相沉积法)、LPCVD(低压力化学气相沉积法)或者溅射方法在衬底基板1沉积出半导体图形的材料层，之后通过构图工艺得到半导体图形2。
当然作为优选方案，可先在衬底基板1上沉积一缓冲层后，再形成半导体图形2。缓冲层用于阻挡衬底基板1中所含的杂质扩散进入薄膜晶体管的有源层中，防止薄膜晶体管的阈值电压和漏电流等特性发生变化。
步骤2：如图3B所示，在形成有半导体图形2的衬底基板1上，形成第 一绝缘层3。其中，第一绝缘层3可采用单层的氧化硅、氮化硅或者二者的叠层，厚度为500埃～2000埃，优选厚度为600埃～1500埃(可根据具体的设计需要选择合适的厚度)。
步骤3：如图3C所示，在形成有第一绝缘层3的衬底基板1上，形成由同一材料层构成的栅极4以及下极板4a。其中，栅极4和下极板4a可为单层、两层或两层以上的结构，材料可以是金属或金属合金，如钼、铝、钼钨等构成，厚度在1000埃～5000埃范围内，优选厚度为1500埃～4000埃。
步骤4：如图3D所示，在形成有所述栅极4和所述下极板4a的衬底基板1上，形成由第二绝缘层构成的第一绝缘图形5以及第二绝缘图形5a，第一绝缘图形5覆盖所述栅极4，第二绝缘图形5a覆盖所述下极板4a。其中，第二绝缘层可采用与第一绝缘层3相同的制作工艺。
在这里需要说明的是，在现有薄膜晶体管的结构中，栅极上方都会设置有起保护作用的栅绝缘层，即本文所指的第二绝缘层。在现有薄膜晶体管中，仅仅通过沉积来形成一整层的第二绝缘层即可。而本公开文本实施例还需要通过构图工艺对第二绝缘层进行图形化的处理，使第二绝缘层构成可在离子注入工艺充当掩膜的第一绝缘图形5。
步骤5：如图3E所示，以第一绝缘图形5和栅极4为掩膜，通过一次离子注入工艺对所述半导体图形进行处理，形成有源层2C、重掺杂源极区2A、轻掺杂源极区2B、重掺杂漏极区2D、轻掺杂漏极区2E。同时在本次离子注入工艺中，还对下极板4a进行离子注入。其中，离子注入工艺的注入介质为含硼元素和/或含磷元素的气体，注入能量范围为10-200keV，注入剂量范围为1×1011-1×1020atoms/cm3。
在具体离子注入过程中，第一绝缘图形5和栅极4分别能够阻挡一部分离子，而相互配合之后，能够完全阻挡离子注入。本公开文本通过设置第一绝缘图形5和栅极4的覆盖结构，使其构成了半阻挡、全阻挡和不阻挡3种离子通过率的掩膜，从而使原先半导体图形能够形成3种不同导电率区域，即导电率最高的重掺杂区，导电率次之的轻掺杂区以及导电率最低的有源层。
步骤6：如图3F所示，在所述第二绝缘图形5a上形成存储电容的上极板6a。在本步骤中，为节省制作成本，可将形成第一绝缘图形5和第二绝缘 图形5a的掩膜板用在形成上极板6a上。这样一来，存储电容的上极板6a则会与第二绝缘图形5a与的图案相同，而第一绝缘图形5的上方会留下未刻蚀的上极板6a的材料层，即与第一绝缘图形5相同图案的导电图形6(导电图形6可去除，也可不去除)。
以上是本实施例的制作方法的示意流程，相比与现有技术，本实施例的制作方法只通过一次离子注入工艺即可形在成薄膜晶体管的源极区域和漏极区域上形成重掺杂部分和轻掺杂部分，同时还对存储电容的下极板也进行离子掺杂。此外，与现有技术不同的是，虽然本公开文本需要对覆盖栅极和下极板的第二绝缘层进行图形化处理，但与上极板6a共用一个刻蚀所需的掩膜板，因此不会比现有技术使用更多的掩膜板。
当然，参考图5，在上述基础之上，还可以进一步形成第三绝缘层7，并对第三绝缘层7进行过孔，之后，形成导电图案8、9。其中，导电图案8通过第三绝缘层7的一个过孔与重掺杂源极区2A连接，从而与重掺杂源极区2A、轻掺杂源极区2B组成薄膜晶体管的源极。同理，导电图案9通过第三绝缘层7的另一个过孔与重掺杂漏极区2E连接，从而与重掺杂漏极区2E、轻掺杂源极区2D组成薄膜晶体管的漏极。
此外，如图4所示，本公开文本的另一实施例还提供了一种由上述制作方法得到的阵列基板，该阵列基板包括：
衬底基板1；
形成在衬底基板1上的薄膜晶体管，所述薄膜晶体管包括栅极4、源极、漏极和有源层2C；所述源极包括重掺杂源极区2A和轻掺杂源极区2B，所述漏极包括重掺杂漏极区2D和轻掺杂漏极区2E；
设置在所述栅极4上方的第一绝缘图形5，其在衬底基板1上的正向投影B覆盖栅极4在衬底基板1上的正向投影A；
其中，所述有源层2C在所述衬底基板1上的正投影A与所述栅极4在所述衬底基板1上的正投影重合，所述轻掺杂源极区2B和所述轻掺杂漏极区2D在所述衬底基板1上的正投影E1、E2与所述第一绝缘图形5在所述衬底基板上的正投影B重合但不与所述栅极4在所述衬底基板上1的正投影A重合，所述重掺杂源极区2A和重掺杂漏极区2E在所述衬底基板1上的正投影 D1、D2与所述第一绝缘图形5在所述衬底基板上的正投影B、所述栅极在所述衬底基板上的正投影A均不重合。
在本实施例的阵列基板中，具有重掺杂部分和轻掺杂部分的源、漏电极由一次离子注入工艺形成。由于离子注入次数降低，故可以减少阵列基板制造时间，进而降低制造成本。
具体地，本实施例的阵列基板还包括：
形成在所述衬底基板1上的存储电容，所述存储电容包括上极板6a、下极板4a以及间隔所述上极板6a和所述下极板4a的第二绝缘图形5a；
所述下极板4a与所述栅极4为同层同材料形成，所述第一绝缘图形5与所述第二绝缘图形5a为同层同材料形成。
进一步地，参考图5，本实施例的阵列基板还包括：
具有过孔的第三绝缘层7和导电图案8、9；
其中，导电图案8通过第三绝缘层7的一个过孔与重掺杂源极区2A连接，从而与重掺杂源极区2A、轻掺杂源极区2B组成薄膜晶体管的源极。同理，导电图案9通过第三绝缘层7的另一个过孔与重掺杂漏极区2E连接，从而与重掺杂漏极区2E、轻掺杂源极区2D组成薄膜晶体管的漏极。
本公开的实施例还提供了一种显示装置，该显示装置包括上述的阵列基板。
这里，该显示装置可以仅为显示面板，也可以为包括有显示面板的显示装置；其中，该显示装置可以为液晶面板、液晶显示装置、有机电致发光显示(Organic Light-Emitting Display，OLED)面板、OLED显示装置、或电子纸、数码相框等具有任何显示功能的产品或者部件。
以上所述是本公开文本的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开文本所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开文本的保护范围。

Claims (15)

  1. 一种阵列基板的制作方法，包括：
    在衬底基板上依次形成不同层设置的半导体图形、栅极和第一绝缘图形，所述半导体图形与所述栅极相互绝缘；所述半导体图形在所述衬底基板上的正投影覆盖所述第一绝缘图形在所述衬底基板上的正投影，所述第一绝缘图形在所述衬底基板上的正投影覆盖所述栅极在所述衬底基板上的正投影；以及
    以所述第一绝缘图形和所述栅极为掩膜，通过一次离子注入工艺对所述半导体图形进行处理，形成有源层、重掺杂源极区、轻掺杂源极区、重掺杂漏极区、轻掺杂漏极区，
    其中，在所述离子注入工艺处理后，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重合，所述轻掺杂源极区和所述轻掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影重合但不与所述栅极在所述衬底基板上的正投影重合，所述重掺杂源极区和重掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影、所述栅极在所述衬底基板上的正投影均不重合。
  2. 根据权利要求1所述的制作方法，还包括：
    形成存储电容的步骤，所述存储电容包括上极板、下极板以及间隔所述上极板和所述下极板的第二绝缘图形；
    其中，所述下极板与所述栅极为同层同材料形成，所述第一绝缘图形与所述第二绝缘图形为同层同材料形成。
  3. 根据权利要求2所述的制作方法，还包括：
    在衬底基板上形成半导体图形；
    在形成有半导体图形的衬底基板上，形成第一绝缘层；
    在形成有第一绝缘层的衬底基板上，形成由同一材料层构成的栅极以及下极板；
    在形成有所述栅极和所述下极板的衬底基板上，形成由第二绝缘层构成的第一绝缘图形以及第二绝缘图形，所述第一绝缘图形覆盖所述栅极，所述 第二绝缘图形覆盖所述下极板；
    以所述第一绝缘图形和所述栅极为掩膜，通过一次离子注入工艺对所述半导体图形进行处理，形成有源层、重掺杂源极区、轻掺杂源极区、重掺杂漏极区、轻掺杂漏极区；以及
    在所述第二绝缘图形上形成所述上极板。
  4. 根据权利要求2或3所述的制作方法，其中，
    形成所述第一绝缘图形和所述第二绝缘图形的构图工艺与形成所述上极板的构图工艺为采用同一掩膜板。
  5. 根据权利要求1至4中任一项所述的制作方法，其中，
    所述栅极的材料包括钼和/或铝，且所述栅极的厚度为1000埃～5000埃。
  6. 根据权利要求5所述的制作方法，其中，
    所述栅极的厚度为1500埃～4000埃。
  7. 根据权利要求3或4所述的制作方法，其中，
    所述第一绝缘层的材料包括氧化硅和/或氮化硅，且所述第一绝缘层的厚度为500埃～2000埃。
  8. 根据权利要求7所述的制作方法，其中，
    所述第一绝缘层的厚度为600埃～1500埃。
  9. 根据权利要求1所述的制作方法，其中，
    所述离子注入工艺的注入介质为含硼元素和/或含磷元素的气体，注入能量范围为10～200keV，注入剂量范围为1×1011～1×1020atoms/cm3。
  10. 一种阵列基板，包括：
    衬底基板；
    形成在衬底基板上的薄膜晶体管，其中，所述薄膜晶体管包括栅极、源极、漏极和有源层；所述源极包括重掺杂源极区和轻掺杂源极区，所述漏极包括重掺杂漏极区和轻掺杂漏极区；以及
    设置在所述栅极上方的第一绝缘图形，其中，所述第一绝缘图形在所述衬底基板上的正向投影覆盖所述栅极在所述衬底基板上的正向投影；
    其中，所述有源层在所述衬底基板上的正投影与所述栅极在所述衬底基板上的正投影重合，所述轻掺杂源极区和所述轻掺杂漏极区在所述衬底基板 上的正投影与所述第一绝缘图形在所述衬底基板上的正投影重合但不与所述栅极在所述衬底基板上的正投影重合，所述重掺杂源极区和重掺杂漏极区在所述衬底基板上的正投影与所述第一绝缘图形在所述衬底基板上的正投影、所述栅极在所述衬底基板上的正投影均不重合。
  11. 根据权利要求10所述的阵列基板，还包括：
    形成在所述衬底基板上的存储电容，所述存储电容包括上极板、下极板以及间隔所述上极板和所述下极板的第二绝缘图形；
    所述下极板与所述栅极为同层同材料形成，所述第一绝缘图形与所述第二绝缘图形为同层同材料形成。
  12. 根据权利要求10或11所述的阵列基板，其中，
    所述栅极的材料包括钼和/或铝，且所述栅极的厚度为1000埃～5000埃。
  13. 根据权利要求12所述的阵列基板，其中，
    所述栅极的厚度为1500埃～4000埃。
  14. 根据权利要求11所述的阵列基板，其中，
    所述下极板和所述栅极具有单层、两层或两层以上的结构。
  15. 一种显示装置，包括如权利要求10至14中任一项所述的阵列基板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110088909A (zh) * 2019-03-18 2019-08-02 京东方科技集团股份有限公司 光电传感器、显示设备和制造光电传感器的方法

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916584A (zh) 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置
CN105810573A (zh) * 2016-03-15 2016-07-27 深圳市华星光电技术有限公司 薄膜晶体管的制作方法
CN105762196B (zh) * 2016-05-16 2018-09-18 京东方科技集团股份有限公司 一种薄膜晶体管、其制作方法及相应装置
CN107887329A (zh) * 2016-09-30 2018-04-06 昆山国显光电有限公司 阵列基板的制造方法
CN107968124A (zh) * 2016-10-18 2018-04-27 上海和辉光电有限公司 一种半导体器件结构及其制备方法
CN106981520B (zh) * 2017-04-12 2020-07-07 京东方科技集团股份有限公司 薄膜晶体管及其制备方法、阵列基板和显示装置
CN109037232B (zh) * 2017-06-08 2019-11-01 京东方科技集团股份有限公司 阵列基板及其制造方法、显示面板以及显示装置
CN108288588A (zh) * 2018-01-31 2018-07-17 京东方科技集团股份有限公司 Nmos器件及其制备方法以及显示装置
CN109509706B (zh) * 2018-12-29 2023-05-02 重庆伟特森电子科技有限公司 一种碳化硅二极管的制备方法及碳化硅二极管
CN110098261A (zh) * 2019-05-05 2019-08-06 华南理工大学 一种薄膜晶体管及其制作方法、显示基板、面板、装置
US20210013238A1 (en) * 2019-07-09 2021-01-14 Sharp Kabushiki Kaisha Active matrix substrate and method for manufacturing same
CN111223877A (zh) * 2019-11-28 2020-06-02 云谷（固安）科技有限公司 阵列基板、阵列基板的制作方法和显示面板
CN114730806A (zh) * 2019-12-31 2022-07-08 广州新视界光电科技有限公司 一种薄膜晶体管的制作方法
CN111129162B (zh) * 2019-12-31 2022-10-04 华南理工大学 一种薄膜晶体管、显示基板、显示面板及显示装置
CN113140637A (zh) * 2020-01-20 2021-07-20 京东方科技集团股份有限公司 显示装置、阵列基板、薄膜晶体管及其制造方法
CN112309969B (zh) * 2020-10-29 2022-10-18 厦门天马微电子有限公司 阵列基板的成型方法、阵列基板以及显示装置
CN114792715B (zh) * 2022-04-08 2024-06-11 武汉华星光电技术有限公司 显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1296643A (zh) * 1999-03-10 2001-05-23 松下电器产业株式会社 薄膜晶体管、液晶面板和它们的制造方法
CN101009331A (zh) * 2006-01-23 2007-08-01 日本电气株式会社 薄膜晶体管及其制造方法
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4305192B2 (ja) * 2003-04-25 2009-07-29 セイコーエプソン株式会社 薄膜半導体装置の製造方法、電気光学装置の製造方法
US6846707B2 (en) * 2003-05-15 2005-01-25 Au Optronics Corp. Method for forming a self-aligned LTPS TFT
KR101353284B1 (ko) * 2012-04-25 2014-01-21 엘지디스플레이 주식회사 액정 디스플레이 장치와 이의 제조방법
KR102081283B1 (ko) * 2013-02-14 2020-04-16 삼성디스플레이 주식회사 박막 반도체 장치, 유기 발광 표시 장치, 및 이의 제조 방법
CN104485278A (zh) * 2014-12-12 2015-04-01 深圳市华星光电技术有限公司 一种阵列基板的掺杂方法和掺杂设备
CN104538307B (zh) * 2014-12-19 2018-07-06 深圳市华星光电技术有限公司 一种用于制作多晶硅薄膜晶体管的方法
CN104599959A (zh) * 2014-12-24 2015-05-06 深圳市华星光电技术有限公司 低温多晶硅tft基板的制作方法及其结构

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1296643A (zh) * 1999-03-10 2001-05-23 松下电器产业株式会社 薄膜晶体管、液晶面板和它们的制造方法
CN101009331A (zh) * 2006-01-23 2007-08-01 日本电气株式会社 薄膜晶体管及其制造方法
CN104916584A (zh) * 2015-04-30 2015-09-16 京东方科技集团股份有限公司 一种制作方法、阵列基板及显示装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110088909A (zh) * 2019-03-18 2019-08-02 京东方科技集团股份有限公司 光电传感器、显示设备和制造光电传感器的方法
CN110088909B (zh) * 2019-03-18 2023-05-30 京东方科技集团股份有限公司 光电传感器、显示设备和制造光电传感器的方法

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