WO2016145967A1 - 多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置 - Google Patents

多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置 Download PDF

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WO2016145967A1
WO2016145967A1 PCT/CN2016/074211 CN2016074211W WO2016145967A1 WO 2016145967 A1 WO2016145967 A1 WO 2016145967A1 CN 2016074211 W CN2016074211 W CN 2016074211W WO 2016145967 A1 WO2016145967 A1 WO 2016145967A1
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gate
active layer
insulating layer
gate insulating
array substrate
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French (fr)
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WO2016145967A9 (zh
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刘政
陆小勇
李小龙
詹裕程
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京东方科技集团股份有限公司
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Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a polysilicon thin film transistor and array substrate, a method of fabricating the same, and a display device.
  • the low temperature polysilicon array substrate Compared with the amorphous silicon array substrate, the low temperature polysilicon array substrate has the advantages of high mobility (up to several hundred times that of amorphous silicon), the thin film transistor can be made small in size, and the reaction speed is fast, and it is coming in recent years.
  • the array substrate of a display panel that is more optimistic is increasingly used in high-resolution, high-quality organic electroluminescence displays and liquid crystal display panels.
  • the composition of the low-temperature polysilicon thin film transistor is generally complicated, and the process is numerous. It takes a long time in mass production or general development, is difficult to monitor, and has high cost and poor stability.
  • FIG. 1 for the storage capacitor structure in which a low-temperature polysilicon transistor array substrate is formed by using a double-layered gate metal in the prior art, technical problems such as high leakage current and low reliability are very likely to occur.
  • FIG. 1 for the storage capacitor structure in which a low-temperature polysilicon transistor array substrate is formed by using a double-layered gate metal in the prior art, technical problems such as high leakage current and low reliability are very likely to occur.
  • 1, 1 is a substrate, 2 is an active layer, 3 is a first gate insulating layer, 4 is a first gate, 5 is a second gate insulating layer, 6 is a storage capacitor bottom electrode, and 7 is The storage capacitor top electrode forms a polysilicon thin film transistor on the left side and a storage capacitor on the right side, respectively.
  • the present disclosure provides a polysilicon thin film transistor and an array substrate, a method of fabricating the same, and a display device, which provide a solution to the problem of high leakage current and low reliability of the low temperature polysilicon thin film transistor fabricated in the prior art.
  • the present disclosure provides a method of fabricating a polysilicon thin film transistor, comprising:
  • the impurity concentration of the doping region is smaller than the impurity concentration of the source/drain implantation region.
  • the dose of the first ion implantation is lower than the dose of the second ion implantation.
  • the dose of the first ion implantation is 1 ⁇ 10 12 ⁇ 1 ⁇ 10 14 atoms/cm 3 ;
  • the dose of the second ion implantation is 1 ⁇ 10 14 to 1 ⁇ 10 18 atoms/cm 3 .
  • the present disclosure also provides a method of fabricating an array substrate, including:
  • a polysilicon thin film transistor as described above is formed on the substrate.
  • the method further includes:
  • a storage capacitor top electrode is formed over the second gate insulating layer corresponding to the storage capacitor bottom electrode.
  • the storage capacitor bottom electrode is formed simultaneously with the first gate
  • the storage capacitor top electrode is formed simultaneously with the second gate.
  • the method further includes:
  • a buffer layer is formed on the substrate.
  • the buffer layer is selected from the group consisting of silicon oxide, silicon nitride, or a combination thereof.
  • the present disclosure also provides a polysilicon thin film transistor, including:
  • the active layer includes an intermediate region, two doped regions respectively located on two sides of the intermediate region, and two source and drain implant regions respectively located outside the two doped regions;
  • the impurity concentration of the doping region is smaller than the impurity concentration of the source/drain implantation region.
  • the thickness of the active layer is the thickness of the active layer.
  • first gate insulating layer and/or the second gate insulating layer is a stack of silicon oxide, silicon nitride or both, and the thickness is
  • first gate and/or the second gate comprise a metal and/or a metal alloy, and the thickness is
  • an array substrate including:
  • the array substrate further includes:
  • the storage capacitor includes a storage capacitor bottom electrode formed on the first gate insulating layer and a storage capacitor top electrode formed on the second gate insulating layer.
  • a buffer layer is further included between the substrate and the polysilicon active layer.
  • the buffer layer is selected from the group consisting of silicon oxide, silicon nitride, or a combination thereof.
  • the present disclosure also provides a display device comprising the array substrate as described above.
  • the double-layer gate metal forming mask in the prior art can be used for the ion implantation process without increasing the mask.
  • a diaphragm while forming a storage capacitor A drain light doped (LDD) region is formed in the thin film transistor, thereby reducing the leakage current of the thin film transistor and improving its stability.
  • LDD drain light doped
  • FIG. 1 is a schematic structural view of a thin film transistor in the prior art
  • FIG. 2 is a flow chart of a method of fabricating a polysilicon thin film transistor according to an embodiment of the present disclosure
  • FIG. 3 is a flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 4 is a flow chart of a method of fabricating an array substrate according to an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of fabrication of an active layer according to an embodiment of the present disclosure.
  • FIG. 6 is a schematic diagram of fabrication of a first gate insulating layer, a first gate, and a storage capacitor bottom electrode according to an embodiment of the present disclosure
  • FIG. 7 is a schematic view of a first ion implantation of one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a second gate insulating layer, a second gate, and a storage capacitor top electrode according to an embodiment of the present disclosure
  • FIG. 9 is a schematic view of a second ion implantation of one embodiment of the present disclosure.
  • FIG. 10 is a schematic structural view of an array substrate according to an embodiment of the present disclosure.
  • Forming generally means sputtering, depositing layers of material, and etching the material as needed to pattern the composition.
  • the order of steps in the method of the present disclosure is not entirely in the order of the description, and some steps may be performed in the same order or in the same time based on the knowledge in the art.
  • an embodiment of the present disclosure provides a method of fabricating a polysilicon thin film transistor, including:
  • Step 201 forming a polysilicon active layer
  • Step 202 sequentially forming a first gate insulating layer and a first gate on the active layer, a projection of the first gate (here, “projection” refers to a projection of a projection surface at an active layer) Located in both end edges of the active layer;
  • Step 203 performing first ion implantation on the active layer by using the first gate as a mask, and forming two doped regions on opposite sides of the active layer respectively;
  • Step 204 sequentially forming a second gate insulating layer and a second gate on the first gate insulating layer and the first gate, wherein projections of both end edges of the second gate are respectively located in the first gate insulating layer and the first gate a projection of a gate and an edge of the active layer;
  • Step 205 performing a second ion implantation on the active layer by using the second gate as a mask, so that two source/drain implantation regions are formed on outer portions of the two doped regions of the active layer.
  • the dose of the first ion implantation may be smaller than the dose of the second ion implantation. low.
  • the dose of the first ion implantation may be 1 ⁇ 10 12 to 1 ⁇ 10 14 atoms/cm 3 ; the dose of the second ion implantation may be 1 ⁇ 10 14 to 1 ⁇ 10 18 atoms/cm 3 .
  • the impurity concentration of the doped region is less than the impurity concentration of the source/drain implant region after two ion implantations, the doped region herein may also be referred to as a lightly doped region.
  • an embodiment of the present disclosure further provides a method for fabricating an array substrate, including:
  • Step 301 providing a substrate
  • Step 302 Form a polysilicon thin film transistor as described above on the substrate.
  • the method may further include the step of fabricating the storage capacitor region:
  • a storage capacitor top electrode is formed over the second gate insulating layer corresponding to the storage capacitor bottom electrode.
  • the storage capacitor bottom electrode and the first gate may be simultaneously formed, and the storage capacitor top electrode and the second gate may be simultaneously formed.
  • a buffer layer may be formed on the substrate, and the buffer layer may include silicon oxide, silicon nitride or a laminate of the two.
  • An embodiment of the present disclosure provides a method for fabricating an array substrate. Referring to FIG. 4, specific steps may include:
  • Step 401 providing a substrate on which a polysilicon active layer is formed.
  • the substrate 1 may be a transparent substrate such as pre-cleaned glass, and may include a buffer layer formed by laminating silicon oxide, silicon nitride or both to prevent metal in the transparent substrate.
  • the ion impurities diffuse into the active layer to affect the operating characteristics of the TFT.
  • the polysilicon active layer 2 formed on the substrate 1 may be deposited by an EPCVD, LPCVD or sputtering method to form an amorphous silicon layer below 600 ° C, and subjected to excimer laser crystallization, metal induced crystallization, solid phase crystallization, etc.
  • a method is a polysilicon layer formed by converting an amorphous silicon layer.
  • the specific process and the structure of the array substrate may be different by using different crystallization methods.
  • heat treatment dehydrogenation, deposition induction metal, heat treatment crystallization, excimer laser need to be added according to the situation. Irradiation crystallization, doping of source and drain regions (P-type or N-type doping), and activation of dopant impurities, etc., but ultimately achieve the technical effects required by the present disclosure.
  • the thickness of the active layer 2 can be In one embodiment, the thickness can be
  • Step 402 sequentially forming a first gate insulating layer and a first gate on the active layer, wherein a projection of the first gate is located in both end edges of the active layer, and is in a predetermined storage capacitor A storage capacitor bottom electrode is formed above the first gate insulating layer corresponding to the region.
  • a first gate insulating layer 3 is first formed on the active layer 2, and then a first gate electrode 4 and a storage capacitor bottom electrode 6 are respectively formed on the first gate insulating layer 3, wherein A projection of a gate 4 is located in both end edges of the active layer 2.
  • Step 403 performing first ion implantation on the active layer by using the first gate as a mask, and forming two doping regions on opposite sides of the active layer.
  • ion implantation is performed using the first gate electrode 4 as a mask to form two doping regions 8 on both sides of the active layer 2, respectively.
  • Step 404 sequentially forming a second gate insulating layer and a second gate on the first gate insulating layer and the first gate, and forming a storage capacitor above the second gate insulating layer corresponding to the bottom electrode of the storage capacitor
  • the top electrode, the projection of the two end edges of the second gate are respectively located between the projection of the first gate and the end edges of the active layer.
  • a second gate insulating layer 5 is formed on the first gate insulating layer 3, the first gate 4, and the storage capacitor bottom electrode 6, and then the second gate electrode 9 and the storage capacitor top electrode are formed. 7, wherein the projections of the end edges of the second grid 9 are respectively located between the projection of the first gate 4 and the end edges of the active layer 2.
  • Step 405 performing a second ion implantation on the active layer by using the second gate as a mask, and forming two source/drain implantation regions on the outer portions of the two doped regions of the active layer.
  • the second layer 9 is used as a mask, and the active layer 2 is subjected to a second ion implantation, so that two outer portions of the two doped regions 8 of the active layer 2 are respectively formed.
  • the first and second gate insulating layers 3 and 5 may be a single layer of silicon oxide, silicon nitride or a combination of the two, which may be deposited by PECVD, LPCVD, APCVD or ECR-CVD, and the thickness is The appropriate thickness can be selected according to the specific design needs. In one embodiment, the thickness is The first and second gate electrodes 4 and 9 and the first and storage capacitor top electrodes 6 and 7 may be a single layer, two layers or more layers, and are composed of a metal, a metal alloy such as molybdenum, aluminum, molybdenum tungsten, etc., thickness in In one embodiment, in one embodiment, the thickness can be The thin film transistor gate and the ion implantation mask on the left side in FIG. 9 and the upper and lower electrodes of the right storage capacitor are formed.
  • the first and second ion implantation processes may employ ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid state diffusion implantation.
  • the embodiment of the present disclosure adopts a mainstream ion cloud implantation method, and can be implanted with a mixed gas containing boron such as B 2 H 6 /H 2 or phosphorus such as PH 3 /H 2 according to design requirements, and the ion implantation energy can be 10 ⁇ . 200 keV, in one embodiment, the energy is between 40 and 100 keV.
  • the implantation dose may be in the range of 1 x 10 11 to 1 x 10 20 atoms/cm 3 .
  • the first ion implantation is LDD implantation, which requires light dose implantation.
  • the dose is 1x10 12 ⁇ 1x10 14 atoms/cm 3 ;
  • the second ion implantation is source-drain implantation, requiring heavy dose injection, in one
  • the dose is 1 x 10 14 to 1 x 10 18 atoms/cm 3 .
  • an embodiment of the present disclosure further provides a polysilicon thin film transistor including:
  • a polysilicon active layer 2 comprising an intermediate region, two doped regions 8 respectively located on opposite sides of the intermediate region, and two source/drain implant regions respectively located outside the two doped regions 8 10;
  • the impurity concentration of the doped region is smaller than the impurity concentration of the source/drain implant region. Therefore, the doped region may also be referred to as a lightly doped region.
  • the thickness of the active layer 2 can be In one embodiment, the thickness is
  • the first gate insulating layer 3 and/or the second gate insulating layer 5 may be a single layer of silicon oxide, silicon nitride or a laminate of the two, and the thickness thereof may be In one embodiment, the thickness is
  • the first gate 4 and/or the second gate 9 may be composed of a metal, a metal alloy such as molybdenum, aluminum, molybdenum tungsten, etc., and the thickness is In one embodiment, the thickness is By selecting the above materials and sizes, polycrystalline silicon thin film transistors can achieve excellent performance.
  • an array substrate including:
  • a polysilicon thin film transistor as described in the embodiment of the present disclosure is formed on the substrate 1.
  • the array substrate may further include: a storage capacitor including a storage capacitor bottom electrode 6 formed on the first gate insulating layer 3 and a storage capacitor top electrode 7 formed on the second gate insulating layer 5.
  • a buffer layer may be further included between the substrate 1 and the polysilicon active layer 2.
  • Embodiments of the present disclosure also provide a display device including the array substrate as described above.
  • the display device may be a device having a display function, such as a display panel, a display, a television, a tablet, a mobile phone, a navigator, etc., which is not limited in this disclosure.
  • the first gate and the second gate are adjusted by adjusting the flow of the ion implantation process and the gate structure.
  • a high-performance thin film transistor and a storage capacitor with an LDD region are simultaneously formed, and a mask for forming an LDD region is not required.
  • the thin film transistor has a lightly doped high-resistance LDD region, which reduces the leakage current of the thin film transistor and improves its operational stability.

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Abstract

提供一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置，其中制作多晶硅薄膜晶体管的方法包括：形成多晶硅有源层（2）；在所述有源层（2）上依次形成第一栅极绝缘层（3）和第一栅极（4），所述第一栅极（4）的投影位于所述有源层（2）的两端边缘内；以所述第一栅极（4）为掩膜，对所述有源层（2）进行第一次离子注入，在所述有源层（2）的两侧分别形成两个掺杂区（8）；在所述第一栅极绝缘层（3）和所述第一栅极（4）上依次形成第二栅极绝缘层（5）和第二栅极（9），所述第二栅极（9）两端边缘的投影分别位于所述第一栅极（4）的投影和所述有源层（2）的两端边缘之间；以所述第二栅极（9）为掩膜，对所述有源层（2）进行第二次离子注入，从而在所述有源层（2）的两个掺杂区（8）的外侧部分形成两个源漏注入区（10）；并且所述两个掺杂区（8）的杂质浓度小于所述两个源漏注入区（10）的杂质浓度。

Description

多晶硅薄膜晶体管和阵列基板及制造方法与一种显示装置
相关申请的交叉引用
本申请要求于2015年03月17日递交的中国专利申请第201510116969.X号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开涉及显示技术领域，尤其涉及一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置。
背景技术
相对于非晶硅阵列基板，低温多晶硅阵列基板拥有高迁移率(可达非晶硅的数百倍)的优点，其薄膜晶体管尺寸可以做得很小，并且反应速度快，是近年来越来越被看好的一种显示面板的阵列基板，在高分辨率、高画质的有机电致发光显示和液晶显示面板上被越来越多的采用。
但是，低温多晶硅薄膜晶体管的构成一般较为复杂，工艺过程繁多，在大规模量产或一般研发中耗时长，难于监控，成本较高且稳定性差。例如，如图1所示，对于现有技术中利用双层栅极金属形成低温多晶硅晶体管阵列基板的存储电容结构来说，非常容易存在漏电流高、可靠性低等技术问题。在图1中，1为衬底，2为有源层，3为第一栅极绝缘层，4为第一栅极，5为第二栅极绝缘层，6为存储电容底电极，7为存储电容顶电极，其分别形成了左侧的多晶硅薄膜晶体管和右侧的存储电容。
发明内容
本公开提供一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置，提供了解决现有技术中所制造的低温多晶硅薄膜晶体管漏电流高、可靠性低的问题的方案。
在一个方面，本公开提供一种制作多晶硅薄膜晶体管的方法，包括：
形成多晶硅有源层；
在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内；
以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个掺杂区；
在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；
以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个掺杂区的外侧部分形成两个源漏注入区；
并且其中，所述掺杂区的杂质浓度小于所述源漏注入区的杂质浓度。
进一步地，
所述第一次离子注入的剂量比所述第二次离子注入的剂量低。
进一步地，
所述第一次离子注入的剂量为1x1012～1x1014atoms/cm3；
和/或，所述第二次离子注入的剂量为1x1014～1x1018atoms/cm3。
另一方面，本公开还提供一种制作阵列基板的方法，包括：
提供衬底；
在所述衬底上形成如上所述的多晶硅薄膜晶体管。
进一步地，所述方法还包括：
在在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极；
在与所述存储电容底电极对应的所述第二栅极绝缘层的上方形成存储电容顶电极。
可选地，所述存储电容底电极与所述第一栅极同时形成；
所述存储电容顶电极与所述第二栅极同时形成。
进一步地，在所述提供衬底和形成所述多晶硅有源层之间还包括：
在所述衬底上形成缓冲层。
可选地，所述缓冲层选自：氧化硅、氮化硅或者二者叠层。
再一方面，本公开还提供一种多晶硅薄膜晶体管，包括：
多晶硅有源层，所述有源层包括中间区，分别位于所述中间区两侧的两个掺杂区，及分别位于所述两个掺杂区外侧的两个源漏注入区；
形成于所述有源层上的第一栅极绝缘层和第一栅极，所述第一栅极的两端边缘的投影分别与所述中间区的两端边缘重合；
形成于所述第一栅极绝缘层和所述第一栅极上的第二栅极绝缘层和第二栅极，所述第二栅极的两端边缘的投影分别与所述两个轻掺杂区的外侧端边缘重合；
并且其中，所述掺杂区的杂质浓度小于所述源漏注入区的杂质浓度。
进一步地，所述有源层的厚度为
Figure PCTCN2016074211-appb-000001
进一步地，所述第一栅极绝缘层和/或第二栅极绝缘层为氧化硅、氮化硅或者二者的叠层，厚度为
Figure PCTCN2016074211-appb-000002
进一步地，所述第一栅极和/或第二栅极包括金属和/或金属合金，厚度为
Figure PCTCN2016074211-appb-000003
另一方面，本公开还提供一种阵列基板，包括：
衬底；
形成在所述衬底上的如上所述的多晶硅薄膜晶体管。
进一步地，所述阵列基板还包括：
存储电容，包括形成在第一栅极绝缘层上的存储电容底电极和形成在所述第二栅极绝缘层上的存储电容顶电极。
进一步地，在所述衬底和所述多晶硅有源层之间还包括：缓冲层。
可选地，所述缓冲层选自：氧化硅、氮化硅或者二者叠层。
再一方面，本公开还提供一种显示装置，包括如上所述的阵列基板。
可见，在本公开提供的一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置中，能够利用现有技术中的双层栅极金属形成掩膜进行离子注入工艺，在不增加掩膜板的情况下，在形成存储电容的同时在 薄膜晶体管中形成漏极轻掺杂(LDD)区域，从而起到降低薄膜晶体管漏电流，提高其稳定性的作用。
附图说明
为了更清楚地说明本公开实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中薄膜晶体管的结构示意图；
图2是本公开的一个实施例的制作多晶硅薄膜晶体管的方法流程图；
图3是本公开的一个实施例制作阵列基板的方法流程图；
图4是本公开的一个实施例的阵列基板的制作方法流程图；
图5是本公开的一个实施例的有源层制作示意图；
图6是本公开的一个实施例的第一栅极绝缘层、第一栅极和存储电容底电极制作示意图；
图7是本公开的一个实施例的的第一次离子注入示意图；
图8是本公开的一个实施例的第二栅极绝缘层、第二栅极和存储电容顶电极示意图；
图9是本公开的一个实施例的第二次离子注入示意图；
图10是本公开的一个实施例的阵列基板结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
注意，在对本公开中，“第一”和“第二”等术语仅用于区分不同实体或步骤，并不意味着重要程度的不同。“形成”各层如本领域所公知的，一般表示溅射、沉积各层材料，需要时再对材料进行刻蚀等构图工艺。本公开的方法中的步骤先后顺序并不完全以描述的顺序为准，基于本领域的知识，有些步骤可以调换顺序或同时进行。
本文所使用的术语仅用于描述特定的实施例，不旨在限制本发明。如本文所用的单数形式“一”、“一个”、“所述”也旨在包括复数形式，除非文中另有明确说明。要进一步理解，在本说明书中使用的用语“包括”和/或“包含”详述所述特征、整数、步骤、操作、元素和/或部件的存在，但不排除一个或者多个其它特征、总体、步骤、操作、元素部件和/或其组合。
参见图2，本公开的一个实施例提供一种制作多晶硅薄膜晶体管的方法，包括：
步骤201：形成多晶硅有源层；
步骤202：在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影(这里，“投影”是指投影面在有源层处的投影)位于所述有源层的两端边缘内；
步骤203：以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个掺杂区；
步骤204：在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；
步骤205：以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个掺杂区的外侧部分形成两个源漏注入区。
其中，由于第一次离子注入和第二次离子注入时分别间隔一层栅极绝缘层和两层栅极绝缘层，因此第一次离子注入的剂量可以比所述第二次离子注入的剂量低。可选地，第一次离子注入的剂量利用为1x1012～1x1014atoms/cm3；第二次离子注入的剂量可以为1x1014～1x1018atoms/cm3。由于两次离子注入之后，掺杂区的杂质浓度小 于所述源漏注入区的杂质浓度，因此，本文中的掺杂区也可被称为轻掺杂区。
参见图3，本公开实施例还提供一种制作阵列基板的方法，包括：
步骤301：提供衬底；
步骤302：在所述衬底上形成如上所述的多晶硅薄膜晶体管。
其中，方法还可以包括存储电容区域的制作步骤：
在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极；
在与所述存储电容底电极对应的所述第二栅极绝缘层的上方形成存储电容顶电极。
存储电容底电极与第一栅极可以同时形成，存储电容顶电极与第二栅极可以同时形成。
其中，为了防止衬底中的金属离子杂质扩散至有源层中影响TFT工作特性，可以在所述衬底上形成缓冲层，缓冲层可以包括氧化硅、氮化硅或二者的叠层。
本公开的实施例提供一种阵列基板的制作方法，参见图4，具体步骤可以包括：
步骤401：提供衬底，在衬底上形成多晶硅有源层。
参见图5，本步骤中，衬底1可以是预先清洗的玻璃等透明衬底，其上可包含采用氧化硅、氮化硅或者二者叠层形成的缓冲层，以防止透明基板中的金属离子杂质扩散至有源层中而影响TFT工作特性。在衬底1上形成的多晶硅有源层2可为PECVD、LPCVD或者溅射方法在600℃以下沉积形成非晶硅层，并通过准分子激光晶化、金属诱导晶化、固相晶化等方法将非晶硅层转变而成的多晶硅层。需要说明的是，采用不同的晶化方法，其具体的工艺过程及阵列基板的结构会有所不同，在制备过程中需要根据情况增加热处理脱氢、沉积诱导金属、热处理晶化、准分子激光照射晶化、源漏区的掺杂(P型或者N型掺杂)及掺杂杂质的激活等工艺，但最终均可实现本公开所需的技术效果。有源层2的厚度可以为
Figure PCTCN2016074211-appb-000004
在一个实施例中，厚度可以为
Figure PCTCN2016074211-appb-000005
步骤402：在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内，并在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极。
参见图6，本步骤中，在有源层2上首先形成第一栅极绝缘层3，然后在第一栅极绝缘层3上分别形成第一栅极4和存储电容底电极6，其中第一栅极4的投影位于有源层2两端边缘内。
步骤403：以第一栅极为掩膜，对有源层进行第一次离子注入，在有源层的两侧分别形成两个掺杂区。
如图7所示，以第一栅极4作为掩膜进行离子注入，以在有源层2的两侧分别形成两个掺杂区8。
步骤404：在第一栅极绝缘层和第一栅极上依次形成第二栅极绝缘层和第二栅极，并在与存储电容底电极对应的第二栅极绝缘层的上方形成存储电容顶电极，第二栅极两端边缘的投影分别位于第一栅极的投影和有源层的两端边缘之间。
参见图8，本步骤中，在第一栅极绝缘层3、第一栅极4和存储电容底电极6上形成第二栅极绝缘层5，然后形成第二栅极9和存储电容顶电极7，其中第二栅极9两端边缘的投影分别位于第一栅极4的投影和有源层2的两端边缘之间。
步骤405：以第二栅极为掩膜，对有源层进行第二次离子注入，在有源层的两个掺杂区的外侧部分形成两个源漏注入区。
参见图9，在本步骤中，以第二栅极9为掩膜，对有源层2进行第二次离子注入，从而在有源层2的两个掺杂区8的外侧部分分别形成两个源漏注入区10。
其中，第一和第二栅极绝缘层3和5可采用单层的氧化硅、氮化硅或者二者的叠层，可使用采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为
Figure PCTCN2016074211-appb-000006
可根据具体的设计需要选择合适的厚度，在一个实施例中，厚度为
Figure PCTCN2016074211-appb-000007
第一和第二栅极4和9以及 第一和存储电容顶电极6和7可为单层、两层或两层以上结构，由金属、金属合金如钼、铝、钼钨等构成，厚度在
Figure PCTCN2016074211-appb-000008
范围内，在一个实施例中，厚度可以为
Figure PCTCN2016074211-appb-000009
用以形成图9中左侧的薄膜晶体管栅极和离子注入掩模，以及右侧存储电容的上下电极。
第一次和第二次离子注入工艺可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法。本公开实施例采用主流的离子云式注入方法，可根据设计需要采用含硼如B2H6/H2或者含磷如PH3/H2的混合气体进行注入，离子注入能量可为10～200keV，在一个实施例中，能量在40～100keV。由于中间分别隔着一层栅极绝缘层和两层栅极绝缘层，因此对第一次离子注入可采用较小的注入能量，对第二次离子注入可采用较高的注入能量。注入剂量可在1x1011～1x1020atoms/cm3范围内。其中第一次离子注入为LDD注入，需要轻剂量注入，在一个实施例中，剂量为1x1012～1x1014atoms/cm3；第二次离子注入为源漏注入，需要重剂量注入，在一个实施例中，剂量为1x1014～1x1018atoms/cm3。
另外，在形成上述结构之后，还需要在第二栅极9之上分别形成源漏极，并将源漏极通过过孔分别与源漏注入区10连接。
参见图10，本公开的实施例还提供一种多晶硅薄膜晶体管，其包括：
多晶硅有源层2，所述有源层包括中间区，分别位于所述中间区两侧的两个掺杂区8，及分别位于所述两个掺杂区8外侧的两个源漏注入区10；
形成于所述有源层2上的第一栅极绝缘层3和第一栅极4，所述第一栅极4的两端边缘的投影分别与所述中间区的两端边缘重合；
形成于所述第一栅极绝缘层3和所述第一栅极4上的第二栅极绝缘层5和第二栅极9，所述第二栅极9的两端边缘的投影分别与所述两个轻掺杂区8的外侧端边缘重合。
其中，掺杂区的杂质浓度小于源漏注入区的杂质浓度，因此，掺杂区也可以被称为轻掺杂区。有源层2的厚度可以为
Figure PCTCN2016074211-appb-000010
在一个实 施例中，厚度为
Figure PCTCN2016074211-appb-000011
其中，第一栅极绝缘层3和/或第二栅极绝缘层5可以为单层的氧化硅、氮化硅或者二者的叠层，其厚度可以为
Figure PCTCN2016074211-appb-000012
在一个实施例中，厚度为
Figure PCTCN2016074211-appb-000013
其中，第一栅极4和/或第二栅极9可以由金属、金属合金如钼、铝、钼钨等构成，厚度为
Figure PCTCN2016074211-appb-000014
在一个实施例中，厚度为
Figure PCTCN2016074211-appb-000015
Figure PCTCN2016074211-appb-000016
通过选用上述材质和尺寸，多晶硅薄膜晶体管能达到优良的性能。
参见图10，本公开的实施例还提供一种阵列基板，包括：
衬底1；
形成在所述衬底1上的如本公开实施例所述的多晶硅薄膜晶体管。
其中，阵列基板还可以包括：存储电容，包括形成在第一栅极绝缘层3上的存储电容底电极6和形成在所述第二栅极绝缘层5上的存储电容顶电极7。
其中，在所述衬底1和所述多晶硅有源层2之间还可以包括：缓冲层。
本公开实施例还提供一种显示装置，包括如上所述的阵列基板。
显示装置可以为显示面板、显示器、电视机、平板电脑、手机、导航仪等具有显示功能的设备，本公开对此不做限定。
可见，在本公开实施例提供的一种多晶硅薄膜晶体管和阵列基板及其制造方法与一种显示装置中，通过调整离子注入工艺的流程和栅极结构，以第一栅极和第二栅极作为离子注入掩模同时形成带有LDD区域的高性能薄膜晶体管和存储电容，不需要专门的形成LDD区域的掩膜。在工艺复杂度保持不变的情况下，薄膜晶体管由于存在轻掺杂的高电阻LDD区，降低了薄膜晶体管的漏电流并提高了其工作稳定性。
最后应说明的是：以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修 改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。

Claims (17)

  1. 一种制作多晶硅薄膜晶体管的方法，其中，包括：
    形成多晶硅有源层；
    在所述有源层上依次形成第一栅极绝缘层和第一栅极，所述第一栅极的投影位于所述有源层的两端边缘内；
    以所述第一栅极为掩膜，对所述有源层进行第一次离子注入，在所述有源层的两侧分别形成两个掺杂区；
    在所述第一栅极绝缘层和所述第一栅极上依次形成第二栅极绝缘层和第二栅极，所述第二栅极两端边缘的投影分别位于所述第一栅极的投影和所述有源层的两端边缘之间；
    以所述第二栅极为掩膜，对所述有源层进行第二次离子注入，从而在所述有源层的两个掺杂区的外侧部分形成两个源漏注入区；
    并且其中，所述掺杂区的杂质浓度小于所述源漏注入区的杂质浓度。
  2. 根据权利要求1所述的制作多晶硅薄膜晶体管的方法，其中：
    所述第一次离子注入的剂量比所述第二次离子注入的剂量低。
  3. 根据权利要求1或2所述的制作多晶硅薄膜晶体管的方法，其中：
    所述第一次离子注入的剂量为1x1012～1x1014atoms/cm3；
    和/或，所述第二次离子注入的剂量为1x1014～1x1018atoms/cm3。
  4. 一种制作阵列基板的方法，其中，包括：
    提供衬底；
    在所述衬底上形成如权利要求1至3中任一项所述的多晶硅薄膜晶体管。
  5. 根据权利要求4所述的制作阵列基板的方法，其中，所述方法还包括：
    在与预定存储电容区域对应的所述第一栅极绝缘层的上方形成存储电容底电极；
    在与所述存储电容底电极对应的所述第二栅极绝缘层的上方形成存储电容顶电极。
  6. 根据权利要求5所述的制作阵列基板的方法，其中，
    所述存储电容底电极与所述第一栅极同时形成；
    所述存储电容顶电极与所述第二栅极同时形成。
  7. 根据权利要求5至6中任一项所述的制作阵列基板的方法，其中，在所述提供衬底和形成所述多晶硅有源层之间还包括：
    在所述衬底上形成缓冲层。
  8. 根据权利要求7所述的制作阵列基板的方法，其中，所述缓冲层选自：氧化硅、氮化硅或者二者叠层。
  9. 一种多晶硅薄膜晶体管，其中，包括：
    多晶硅有源层，所述有源层包括中间区，分别位于所述中间区两侧的两个掺杂区，及分别位于所述两个掺杂区外侧的两个源漏注入区；
    形成于所述有源层上的第一栅极绝缘层和第一栅极，所述第一栅极的两端边缘的投影分别与所述中间区的两端边缘重合；
    形成于所述第一栅极绝缘层和所述第一栅极上的第二栅极绝缘层和第二栅极，所述第二栅极的两端边缘的投影分别与所述两个轻掺杂区的外侧端边缘重合；
    并且其中，所述掺杂区的杂质浓度小于所述源漏注入区的杂质浓度。
  10. 根据权利要求7所述的多晶硅薄膜晶体管，其中：
    所述有源层的厚度为
    Figure PCTCN2016074211-appb-100001
  11. 根据权利要求7所述的多晶硅薄膜晶体管，其中：
    所述第一栅极绝缘层和/或第二栅极绝缘层为氧化硅、氮化硅或者二者的叠层，厚度为
    Figure PCTCN2016074211-appb-100002
  12. 根据权利要求9至11中任一项所述的多晶硅薄膜晶体管，其中：
    所述第一栅极和/或第二栅极包括金属和/或金属合金，厚度为
    Figure PCTCN2016074211-appb-100003
    Figure PCTCN2016074211-appb-100004
  13. 一种阵列基板，其中，包括：
    衬底；
    形成在所述衬底上的如权利要求9至12中任一项所述的多晶硅薄膜晶 体管。
  14. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括：
    存储电容，包括形成在第一栅极绝缘层上的存储电容底电极和形成在所述第二栅极绝缘层上的存储电容顶电极。
  15. 根据权利要求13至14中任一项所述的阵列基板，其中，在所述衬底和所述多晶硅有源层之间还包括：缓冲层。
  16. 根据权利要求15所述的制作阵列基板，其中，所述缓冲层选自：氧化硅、氮化硅或者二者叠层。
  17. 一种显示装置，其中，包括如权利要求13至16中任一项所述的阵列基板。
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