WO2014153841A1 - 低温多晶硅薄膜制作方法、薄膜晶体管制作方法 - Google Patents

低温多晶硅薄膜制作方法、薄膜晶体管制作方法 Download PDF

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WO2014153841A1
WO2014153841A1 PCT/CN2013/076884 CN2013076884W WO2014153841A1 WO 2014153841 A1 WO2014153841 A1 WO 2014153841A1 CN 2013076884 W CN2013076884 W CN 2013076884W WO 2014153841 A1 WO2014153841 A1 WO 2014153841A1
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amorphous silicon
forming
temperature polysilicon
silicon film
low temperature
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PCT/CN2013/076884
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English (en)
French (fr)
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张慧娟
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京东方科技集团股份有限公司
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Priority to US14/355,137 priority Critical patent/US9356123B2/en
Publication of WO2014153841A1 publication Critical patent/WO2014153841A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02592—Microstructure amorphous
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate

Definitions

  • Embodiments of the present invention relate to a method of fabricating a low temperature polysilicon film for a display such as a liquid crystal display (LCD) or an organic electroluminescent display (OLED), and a method of fabricating a thin film transistor.
  • a display such as a liquid crystal display (LCD) or an organic electroluminescent display (OLED)
  • OLED organic electroluminescent display
  • LTPS low temperature polysilicon Due to the atomic arrangement rule, high carrier mobility (10 ⁇ 300cm 2 /Vs), high driving current, can accelerate the reaction time of liquid crystal, reduce the volume of TFT, increase the transmission area, and obtain higher Brightness and resolution, so LTPS is widely used in the fabrication of thin film transistors to prepare active layers.
  • the conventional method of crystallizing amorphous silicon by RTA (rapid thermal annealing) to form polycrystalline silicon requires annealing at a temperature of about 750 ° C, and the softening temperature of the glass is about 700 ° C, so it cannot be used on ordinary glass. Crystallization is achieved; and in the case of high-temperature crystallization, the number of nucleation is too large, which is not conducive to the formation of large-sized crystal grains; further, high-temperature crystallization increases the internal stress of the film layer, resulting in more crystal defects.
  • the polycrystalline silicon thin film formed by the RTA method has a small grain size, uneven distribution, and high film roughness, which directly affects the electrical properties of the low temperature polysilicon thin film transistor (for example, mobility, leakage current, mobility, and threshold). Voltage uniformity, etc.).
  • an embodiment of the present invention provides a method for fabricating a low temperature polysilicon film, comprising: forming an amorphous silicon film;
  • the amorphous silicon film is subjected to multiple rapid thermal annealing at a preset temperature to form a low temperature polysilicon film, and the preset temperature is lower than the conventional RTA crystallization temperature.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor, comprising: forming a buffer layer on a substrate;
  • a source electrode and a drain electrode are formed on the substrate on which the interlayer insulating layer is formed.
  • the embodiment of the present invention further provides a method for fabricating a thin film transistor, comprising: forming a buffer layer on a substrate;
  • a source electrode and a drain electrode are formed on the substrate on which the interlayer insulating layer is formed.
  • FIG. 1 is a schematic flow chart of a method for fabricating a low-temperature polysilicon film according to an embodiment of the present invention
  • FIG. 2 is a schematic view showing deposition of an amorphous silicon film on a substrate according to an embodiment of the present invention
  • FIG. 3 is a schematic view showing a dehydrogenation process of an amorphous silicon film according to an embodiment of the present invention
  • FIG. 4 is a schematic view of forming a crystal grain after multiple rapid thermal annealing according to an embodiment of the present invention
  • FIG. 5 is a schematic view showing a grain growth of an embodiment of the present invention
  • FIG. 6 is a schematic structural view of a thin film transistor according to an embodiment of the present invention.
  • FIG. 7 is a schematic diagram of forming 30 display panels on a substrate according to an embodiment of the present invention
  • FIG. 8 is a schematic diagram showing I-V test results of a thin film transistor according to an embodiment of the present invention.
  • Embodiments of the present invention provide a method for fabricating a low temperature polysilicon film and a thin film transistor
  • the manufacturing method can form a uniform polysilicon film having a high mobility on a common glass substrate, thereby improving the electrical performance of the thin film transistor.
  • FIG. 1 is a schematic flow chart of a method for fabricating a low temperature polysilicon film according to an embodiment of the present invention. As shown in Figure 1, the method includes:
  • Step 101 forming an amorphous silicon film
  • Step 102 performing a plurality of rapid thermal annealing on the amorphous silicon film at a preset temperature to form a low temperature polysilicon film, wherein the preset temperature is lower than a conventional RTA crystallization temperature.
  • the conventional RTA crystallization temperature is 750 °C.
  • the substrate may be cleaned in advance to keep the substrate clean.
  • step 101 specifically includes:
  • the amorphous silicon film is deposited by plasma enhanced chemical vapor deposition.
  • step 102 specifically includes:
  • the amorphous silicon film is subjected to at least 3 rapid thermal annealing in a temperature range of 600 to 670 ° C, and the time of each rapid thermal annealing is not more than 30 s, and is cooled to room temperature.
  • the method before the step 102 is performed, the method further includes:
  • the amorphous silicon film is treated for 1 to 2 hours in a temperature range of 400 to 500 °C. Further, in another embodiment of the present invention, after the step of the foregoing steps, after step 102, the method further includes:
  • the low temperature polysilicon film is treated for at least 3 hours in a temperature range of 400 to 500 °C.
  • the conventional RTA crystallization temperature is generally annealed in a temperature range of about 750 ° C, and the softening temperature of the glass is about 700 ° C, so that crystallization cannot be achieved on ordinary glass; and in the case of high-temperature crystallization, the shape Too many cores are not conducive to the formation of large-sized grains; further high-temperature crystallization increases the internal stress of the film, resulting in more crystal defects.
  • the amorphous silicon film is subjected to multiple rapid thermal annealing in an environment lower than the conventional RTA crystallization temperature, thereby lowering the crystallization temperature, enabling crystallization on a common glass substrate and reducing the production of a low temperature polysilicon film.
  • the method for fabricating the low temperature polysilicon film of the embodiment of the present invention will be described in detail below with reference to Figs.
  • the method for fabricating low temperature polysilicon according to an embodiment of the invention includes the following steps:
  • the substrate may be a common glass substrate.
  • the substrate Before performing step S1, the substrate may be cleaned in advance to keep the substrate clean.
  • the buffer layer may be a composite buffer layer composed of a SiN x layer and a Si0 2 layer.
  • the step S1 specifically includes: depositing a layer of 50-150 nm thick by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method or other deposition method on the substrate (the thickness thereof may also be set as needed) SiN x layer to another value); then using a PECVD method, or other deposition methods for depositing a layer of 100 ⁇ 350 nm thick (the thickness thereof may be set to other values as required) of the Si0 2 layer, whereby the composite layer is formed on the substrate buffer .
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • the buffer layer may also be a SiO 2 or SiN 2 layer.
  • a layer of amorphous silicon material is deposited on the buffer layer on the substrate 1 by a PECVD method.
  • the thickness of the amorphous silicon material layer is preferably 50 nm, and the thickness thereof may be set to other values as needed.
  • the process condition for performing step S2 may be, for example, a reaction gas flow ratio of
  • the formed amorphous silicon thin film 2 contains hydrogen 3.
  • the amorphous silicon film is dehydrogenated.
  • the amorphous silicon film can be subjected to a high temperature treatment for 1 to 2 hours in a temperature range of 400 to 500 °C.
  • the amorphous silicon film is incubated at 450 ° C for 1.5 hours by a conventional annealing furnace to remove hydrogen residues in the amorphous silicon film, thereby avoiding hydrogen overflow during subsequent rapid thermal annealing and affecting the crystallization effect.
  • S4 performing a plurality of rapid thermal annealing on the amorphous silicon film in a preset temperature environment to form a low temperature polysilicon film, wherein the preset temperature is lower than a conventional RTA crystallization temperature;
  • the amorphous silicon film is subjected to at least 3 rapid thermal annealing in a temperature range of 600 to 670 ° C, and the time of each rapid thermal annealing is not more than 30 s, and is cooled to room temperature.
  • reference numeral 4 denotes crystal grains in the low-temperature polysilicon film formed through the step S4.
  • the amorphous silicon film is subjected to multiple rapid thermal annealing in an environment lower than the conventional RTA crystallization temperature, thereby lowering the crystallization temperature, enabling crystallization on a common glass substrate, thereby reducing the manufacturing cost of the low temperature polysilicon film. And through multiple rapid thermal annealing, the polycrystalline silicon crystal grains can be uniformly nucleated, and the low temperature crystallization can reduce the internal stress of the molybdenum layer, reduce the crystal defects, and can improve the mobility of the polycrystalline silicon film.
  • the low temperature polysilicon film is subjected to a high temperature treatment for at least 3 hours in a temperature range of 400 to 500 °C.
  • the low temperature polysilicon film is kept at a temperature of 450 ° C for 3 hours.
  • the low temperature polysilicon film is held at a preset high temperature for a period of time to promote grain growth.
  • This crystallization is divided into two distinct stages of nucleation and growth, which not only ensures uniform nucleation, but also ensures the size of the crystal grains.
  • polycrystalline silicon having a grain size of about 200 nm can be finally formed.
  • the increase in grain size can further increase the mobility of the polysilicon film, thereby improving the electrical performance of the thin film transistor.
  • the embodiment of the invention further provides a method for fabricating a thin film transistor, comprising:
  • Step 1 forming a buffer layer on the substrate
  • the buffer layer may be a composite buffer layer composed of a SiN x layer and a Si0 2 layer.
  • the buffer layer may also be a SiO 2 or SiN 2 layer.
  • Step 2 depositing an amorphous silicon film on the buffer layer
  • a layer of amorphous silicon material may be deposited on the buffer layer by PECVD.
  • the thickness of the amorphous silicon material layer is preferably 50 nm, and the thickness thereof may be set to other values as needed.
  • the process conditions for performing step 2 can be, for example: Sccm /500-1250 sccm, RF power is 80 ⁇ 120 W, the pressure in the deposition chamber is 1800 ⁇ 2200 mtorr and the temperature is 380 ⁇ 400 °C. At this time, the formed amorphous silicon film contains hydrogen;
  • Step 3 Using RTA for the amorphous silicon film in an environment lower than the conventional RTA crystallization temperature The device performs multiple rapid thermal annealing to form a low temperature polysilicon film, and the low temperature polysilicon film is patterned to form an active layer including a source region, a drain region and a channel region;
  • the amorphous silicon film can be dehydrogenated first.
  • the amorphous silicon film can be subjected to a high temperature treatment for 1 to 2 hours in a temperature range of 400 to 500 °C.
  • the amorphous silicon film is incubated at 450 ° C for 1.5 hours in a conventional annealing furnace to remove hydrogen residues in the amorphous silicon film, thereby avoiding hydrogen overflow during subsequent rapid thermal annealing and affecting the crystallization effect.
  • the amorphous silicon film is subjected to at least 3 rapid thermal annealing in a temperature range of 600 to 670 ° C, and the time of each rapid thermal annealing is not more than 30 s, and is cooled to room temperature.
  • the low temperature polysilicon film is further subjected to a high temperature treatment for at least 3 hours in a temperature range of 400 to 500 °C. Then, the low temperature polysilicon film is patterned by a mask to form an active layer including a source region, a drain region and a channel region;
  • Step 4 forming a gate insulating layer over the channel region and a gate electrode on the gate insulating layer; for example, a layer of SiN x or SiO 2 may be deposited over the channel region by PECVD or other deposition methods to form a gate insulating layer And forming a gate electrode by sputtering on the gate insulating layer; Step 5, doping impurities in the source region and the drain region by ion implantation, and forming an interlayer insulating layer over the gate electrode;
  • 81 ⁇ or SiO 2 may be deposited over the gate electrode by PECVD or other deposition methods to form an interlayer insulating layer;
  • Step 6 Form a source electrode and a drain electrode on the substrate on which the interlayer insulating layer is formed.
  • the source electrode and the drain electrode may be formed on the substrate on which the interlayer insulating layer is formed by sputtering.
  • the source electrode and the drain electrode may be connected to the source and drain regions of the active layer through via holes penetrating through the interlayer insulating layer and the gate insulating layer, respectively.
  • a top gate type thin film transistor is formed by the above steps, wherein the method of forming the low temperature amorphous silicon film on the substrate is the same as the method of fabricating the low temperature polysilicon film of the embodiment of the present invention.
  • a thin film transistor fabricated by the above thin film transistor fabrication method has a structure as shown in FIG.
  • the embodiment of the invention further provides a method for fabricating a thin film transistor, comprising:
  • Step 1 forming a buffer layer on the substrate
  • the buffer layer may be a composite buffer layer composed of a SiN x layer and a Si0 2 layer.
  • the buffer layer may also be a Si0 2 or SiN ⁇ punch layer;
  • Step 2 forming a gate electrode and a gate insulating layer on the buffer layer;
  • a gate electrode may be formed on the buffer layer by a sputtering method, and SiN x or SiO 2 may be deposited by a PECVD method or other deposition methods to form a gate insulating layer.
  • a gate insulating layer may be formed before the amorphous silicon film is formed;
  • Step 3 depositing an amorphous silicon film on the gate insulating layer
  • a layer of amorphous silicon material may be deposited on the gate insulating layer by PECVD.
  • the thickness of the amorphous silicon material layer is preferably 50 nm, and the thickness thereof may be set to other values as needed.
  • the process conditions for performing step 3 may be, for example, a reaction gas flow ratio of Sccm /500 ⁇ 1250 sccm, RF power is 80 ⁇ 120 W, the pressure in the deposition chamber is 1800 ⁇ 2200 mtorr and the temperature is 380 ⁇ 400 °C. At this time, the formed amorphous silicon film contains hydrogen;
  • Step 4 performing rapid thermal annealing on the amorphous silicon film by using an RTA device in an environment lower than the conventional RTA crystallization temperature to form a low temperature polysilicon film, and patterning the low temperature polysilicon film to form a source region, a drain region, and An active layer of the channel region;
  • the amorphous silicon film can be dehydrogenated first.
  • the amorphous silicon film can be subjected to a high temperature treatment for 1 to 2 hours in a temperature range of 400 to 500 °C.
  • the amorphous silicon film is incubated at 450 ° C for 1.5 hours in a conventional annealing furnace to remove hydrogen residues in the amorphous silicon film, thereby avoiding hydrogen overflow during subsequent rapid thermal annealing and affecting the crystallization effect.
  • the amorphous silicon film is subjected to at least 3 rapid thermal annealing in a temperature range of 600 to 670 ° C, and the time of each rapid thermal annealing is not more than 30 s, and is cooled to room temperature.
  • the low temperature polysilicon film is further subjected to a high temperature treatment for at least 3 hours in a temperature range of 400 to 500 °C.
  • the low temperature polysilicon film is then patterned through a mask to form an active layer including a source region, a drain region, and a channel region;
  • Step 5 Incorporating impurities into the source and drain regions by ion implantation, and forming an interlayer insulating layer over the active layer;
  • SiN x or SiO 2 may be deposited over the active layer by PECVD or other deposition methods to form an interlayer insulating layer;
  • Step 6 Form a source electrode and a drain electrode on the substrate on which the interlayer insulating layer is formed.
  • the source electrode and the drain electrode may be formed on the substrate on which the interlayer insulating layer is formed by sputtering.
  • the source electrode and the drain electrode may be respectively connected to the active layer through via holes penetrating through the interlayer insulating layer Source and drain areas.
  • the bottom gate type thin film transistor is formed by the above steps, wherein the method of forming the low temperature amorphous silicon film on the substrate is the same as the method of fabricating the low temperature polysilicon film of the embodiment of the present invention.
  • a plurality of display panels can be formed on one substrate by the method of fabricating the thin film transistor of the present invention. Taking 30 display panels uniformly formed on the substrate as an example, 15 test points are taken at intervals on the entire substrate. For example, one test point can be taken on each of the display panels numbered 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, for each test point.
  • the performance of the thin film transistor was tested, and the IV test results of the obtained thin film transistor are shown in Fig. 8.
  • the horizontal axis represents the gate voltage
  • the vertical axis represents the source-drain current of the thin film transistor. It can be seen that the I-V curves of the thin film transistors of the plurality of test points tend to be uniform, which proves that the thin film transistor fabricated by the embodiment of the present invention has uniform characteristics and is easy to drive.

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Abstract

提供一种低温多晶硅薄膜制作方法和一种薄膜晶体管制作方法。该低温多晶硅薄膜的制作方法包括：形成非晶硅薄膜；在预设温度下对非晶硅薄膜进行多次快速热退火，形成低温多晶硅薄膜，预设温度低于传统RTA晶化温度。

Description

低温多晶硅薄膜制作方法、 薄膜晶体管制作方法 技术领域
本发明的实施例涉及一种用于显示器如液晶显示器（LCD )或有机电致 发光显示器（OLED ) 的低温多晶硅薄膜制作方法、 薄膜晶体管制作方法。 背景技术
LTPS (低温多晶硅） 由于原子排列规则， 载流子迁移率高 ( 10~300cm2/Vs ) , 驱动电流高， 可以加快液晶的反应时间， 缩小 TFT的体 积， 增加透过面积， 得到更高的亮度和解析度， 因此薄膜晶体管的制作工艺 中广泛采用 LTPS制备有源层。
传统的采用 RTA (快速热退火 )使非晶硅晶化以形成多晶硅的方法需要 在 750°C左右的温度范围内进行退火， 而玻璃的软化温度在 700°C左右， 因此 无法在普通玻璃上实现晶化； 并且在高温晶化的情况下， 形核数量过多， 不 利于形成尺寸较大的晶粒； 再者高温晶化提高了膜层内应力， 使得晶体缺陷 较多。
因此， 目前利用 RTA方法形成的多晶硅薄膜晶粒尺寸偏小， 分布不均 匀， 薄膜粗糙度高， 直接影响了低温多晶硅薄膜晶体管的电学性能（例如， 迁移率大小、 漏电流大小、 迁移率及阈值电压的均匀性等） 。 发明内容
一方面， 本发明的实施例提供一种低温多晶硅薄膜的制作方法， 包括： 形成非晶硅薄膜；
在预设温度下对所述非晶硅薄膜进行多次快速热退火， 形成低温多晶硅 薄膜， 所述预设温度低于传统 RTA晶化温度。
另一方面， 本发明实施例还提供了一种薄膜晶体管的制作方法， 包括： 在基板上形成一緩沖层；
在所述緩沖层上以上述方法形成低温多晶硅薄膜；
对低温多晶硅薄膜进行构图， 形成包括源区、 漏区和沟道区的有源层； 在沟道区上方形成栅绝缘层， 并在栅绝缘层上形成栅电极； 通过离子注入的方式在源区和漏区掺入杂质， 在栅电极上方形成层间绝 缘层；
在形成有层间绝缘层的基板上形成源电极和漏电极。
再一方面， 本发明实施例还提供了一种薄膜晶体管的制作方法， 包括： 在基板上形成一緩沖层；
在所述緩沖层上形成栅电极和栅绝缘层；
在所述栅绝缘层以上述方法形成低温多晶硅薄膜；
对低温多晶硅薄膜进行构图， 形成包括源区、 漏区和沟道区的有源层； 通过离子注入的方式在源区和漏区掺入杂质， 并在有源层上方形成层间 绝缘层；
在形成有层间绝缘层的基板上形成源电极和漏电极。 附图说明
图 1为本发明实施例低温多晶硅薄膜的制作方法的流程示意图； 图 2为本发明实施例在基板上沉积非晶硅薄膜的示意图；
图 3为本发明实施例对非晶硅薄膜进行去氢工艺后的示意图；
图 4为本发明实施例在多次快速热退火之后形成晶粒的示意图； 图 5为本发明实施例晶粒长大后的示意图；
图 6为本发明实施例薄膜晶体管的结构示意图；
图 7为本发明实施例在一张基板上形成 30个显示面板的示意图； 图 8为本发明实施例薄膜晶体管的 I-V测试结果示意图。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合附图， 对本发明实施例的技术方案进行清楚、 完整地描述。 显然， 所描述的实施例 是本发明的一部分实施例， 而不是全部的实施例。 基于所描述的本发明的实 施例， 本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实 施例， 都属于本发明保护的范围。
本发明的实施例提供一种低温多晶硅薄膜制作方法以及一种薄膜晶体管 制作方法， 能够在普通玻璃基板上形成均匀的迁移率较高的多晶硅薄膜， 从 而能够提高薄膜晶体管的电学性能。
图 1为本发明实施例低温多晶硅薄膜的制作方法的流程示意图。 如图 1 所示， 该方法包括：
步骤 101: 形成非晶硅薄膜；
步骤 102: 在预设温度下对所述非晶硅薄膜进行多次快速热退火， 形成 低温多晶硅薄膜， 所述预设温度低于传统 RTA晶化温度。
传统 RTA晶化温度为 750°C。
进一步地， 本发明的另一实施例中， 在包括上述步骤的基础上， 在执行 步骤 101之前， 还可以预先对基板进行清洗， 使基板保持洁净。
进一步地，本发明的另一实施例中，在包括上述步骤的基础上，步骤 101 具体包括：
在基板上形成一緩沖层；
在所述緩沖层上， 采用等离子体增强化学气相沉积法沉积所述非晶硅薄 膜。
进一步地，本发明的另一实施例中，在包括上述步骤的基础上，步骤 102 具体包括：
在 600~670°C的温度范围内对所述非晶硅薄膜进行至少 3次快速热退火， 每次快速热退火的时间不大于 30s, 冷却至室温。
进一步地， 本发明的另一实施例中， 在包括上述步骤的基础上， 在执行 步骤 102之前还包括：
在 400~500°C的温度范围内， 对所述非晶硅薄膜进行 1 ~2小时的处理。 进一步地，本发明的另一实施例中，在包括上述步骤的基础上，步骤 102 之后还包括：
在 400~500°C的温度范围内， 对所述低温多晶硅薄膜进行至少 3小时的 处理。
传统的 RTA晶化温度一般在 750 °C左右的温度范围内进行退火，而玻璃 的软化温度在 700°C左右， 因此无法在普通玻璃上实现晶化； 并且在高温晶 化的情况下， 形核数量过多， 不利于形成尺寸较大的晶粒； 再者高温晶化提 高了膜层内应力， 使得晶体缺陷较多。 本发明实施例的低温多晶硅薄膜的制 作方法， 对非晶硅薄膜在低于传统 RTA 晶化温度的环境下进行多次快速热 退火， 降低了晶化温度， 使得能够在普通玻璃基板上实现晶化， 降低了低温 多晶硅薄膜的制作成本； 并且通过多次快速热退火， 可以使多晶硅晶粒均匀 形核， 再者低温晶化促 莫层内应力降低， 减少了晶体缺陷， 能够提高多晶 硅薄膜的迁移率， 进而提升薄膜晶体管的电学性能。
下面结合附图 2-4对本发明实施例的低温多晶硅薄膜的制作方法进行详 细介绍。 本发明实施例的低温多晶硅的制作方法包括以下步骤：
S1: 在基板上沉积緩沖层；
本发明实施例中， 基板可以为普通的玻璃基板， 在执行步骤 S1 之前， 可以预先对基板进行清洗， 使基板保持洁净。
緩沖层可为 SiNx层与 Si02层组成的复合緩沖层。 此时， 步骤 S1具体包 括： 在基板上先采用 PECVD ( Plasma Enhanced Chemical Vapor Deposition, 等离子体增强化学气相沉积法）法或者其它沉积方法沉积一层 50~150 nm厚 (其厚度亦可根据需要设置为其它值 )的 SiNx层； 再采用 PECVD法或者其 它沉积方法沉积一层 100~350 nm厚（其厚度亦可根据需要设置为其它值 ) 的 Si02层， 从而在基板上形成复合緩沖层。
另外， 緩沖层亦可为 Si02或 SiN^ 沖层。
S2: 在緩沖层上沉积非晶硅薄膜；
如图 2所示， 在基板 1上采用 PECVD法在緩沖层上沉积一层非晶硅材 料层，非晶硅材料层的厚度优选为 50纳米，其厚度亦可根据需要设置为其它 值。执行步骤 S2的工艺条件例如可以为：反应气体流量比为
Figure imgf000005_0001
sccm /500-1250 sccm, 射频功率为 80~120 W, 沉积腔内压强为 1800~2200 mtorr及温度为 380~400°C。 此时， 形成的非晶硅薄膜 2中含有氢 3。
S3: 对非晶硅薄膜进行去氢；
如图 3所示， 对非晶硅薄膜进行去氢。 例如， 可以在 400~500°C的温度 范围内， 对所述非晶硅薄膜进行 1~2小时的高温处理。 优选地， 通过传统退 火炉在 450°C下对非晶硅薄膜保温 1.5小时，去除非晶硅薄膜中的氢残留，避 免后续快速热退火过程中氢溢出， 影响晶化效果。
S4: 在预设温度的环境下对非晶硅薄膜进行多次快速热退火， 形成低温 多晶硅薄膜， 所述预设温度低于传统 RTA晶化温度； 例如，在 600~670°C温度范围内对非晶硅薄膜进行至少 3次快速热退火， 每次快速热退火的时间不大于 30s, 冷却至室温。 如图 4所示， 标记 4表示 经过步骤 S4形成的低温多晶硅薄膜中的晶粒。将非晶硅薄膜在低于传统 RTA 晶化温度的环境下进行多次快速热退火， 降低了晶化温度， 使得能够在普通 玻璃基板上实现晶化， 由此降低了低温多晶硅薄膜的制作成本； 并且通过多 次快速热退火， 可以使多晶硅晶粒均匀形核， 再者低温晶化促 莫层内应力 降低， 减少了晶体缺陷， 能够提高多晶硅薄膜的迁移率。
S5: 对低温多晶硅薄膜进行高温保温处理；
例如， 在 400~500°C的温度范围内， 对所述低温多晶硅薄膜进行至少 3 小时的高温处理。 优选地， 在 450°C的温度范围内， 对所述低温多晶硅薄膜 进行 3小时的保温。
形核之后， 将低温多晶硅薄膜在预设高温下保温一段时间， 能够促使晶 粒长大。 这样使晶化分为明显的形核与长大两个阶段， 既保证了均匀形核， 也保证了晶粒的尺寸。 如图 5所示， 晶粒 4长大后， 最终可以形成晶粒尺寸 在 200纳米左右的多晶硅。 晶粒尺寸的提高， 可以进一步提高多晶硅薄膜的 迁移率， 进而提升薄膜晶体管的电学性能。
本发明实施例还提供了一种薄膜晶体管的制作方法， 包括：
步骤 1、 在基板上形成一緩沖层；
緩沖层可为 SiNx层与 Si02层组成的复合緩沖层。例如，可以采用 PECVD 法或者其它沉积方法先沉积一层 50~150 nm厚（其厚度亦可根据需要设置为 其它值） 的 SiNx层； 再采用 PECVD法或者其它沉积方法沉积一层 100~350 nm厚（其厚度亦可根据需要设置为其它值） 的 Si02层， 从而在基板上形成 复合緩沖层。 另外， 緩沖层亦可为 Si02或 SiN^ 沖层。
步骤 2、 在所述緩沖层上沉积非晶硅薄膜；
可以采用 PECVD法在緩沖层上沉积一层非晶硅材料层， 非晶硅材料层 的厚度优选为 50纳米，其厚度亦可根据需要设置为其它值。执行步骤 2的工 艺条件例如可以为： 反应气体流量比为
Figure imgf000006_0001
sccm /500-1250 sccm, 射频功率为 80~120 W, 沉积腔内压强为 1800~2200 mtorr及温度为 380~400°C。 此时， 形成的非晶硅薄膜中含有氢；
步骤 3、在低于传统 RTA晶化温度的环境下对所述非晶硅薄膜使用 RTA 设备进行多次快速热退火形成低温多晶硅薄膜， 并对低温多晶硅薄膜进行构 图形成包括源区、 漏区和沟道区的有源层；
可以先对非晶硅薄膜进行去氢处理。 例如， 可以在 400~500°C的温度范 围内， 对所述非晶硅薄膜进行 1~2小时的高温处理。 优选地， 通过传统退火 炉在 450°C下对非晶硅薄膜保温 1.5小时，去除非晶硅薄膜中的氢残留，避免 后续快速热退火过程中氢溢出， 影响晶化效果。 在 600~670°C温度范围内对 非晶硅薄膜进行至少 3次快速热退火， 每次快速热退火的时间不大于 30s, 冷却至室温。 再在 400~500°C的温度范围内， 对所述低温多晶硅薄膜进行至 少 3小时的高温处理。 之后通过掩模板对低温多晶硅薄膜进行构图工艺， 形 成包括源区、 漏区和沟道区的有源层；
步骤 4、 在沟道区上方形成栅绝缘层， 并在栅绝缘层上栅电极； 例如， 可以在沟道区上方采用 PECVD 法或者其它沉积方法沉积一层 SiNx或 Si02以形成栅绝缘层， 并在栅绝缘层上采用溅射方式形成栅电极； 步骤 5、 通过离子注入的方式在源区和漏区掺入杂质， 在栅电极上方形 成层间绝缘层；
例如， 可以在栅电极上方采用 PECVD法或者其它沉积方法沉积 81^或 Si02以形成层间绝缘层；
步骤 6、 在形成有层间绝缘层的基板上形成源电极和漏电极。
例如， 可以采用溅射方式在形成有层间绝缘层的基板上形成源电极和漏 电极。 源电极和漏电极可以分别通过穿过层间绝缘层和栅绝缘层的过孔连接 到有源层的源区和漏区。
通过上述步骤形成了顶栅型的薄膜晶体管， 其中， 在基板上形成低温非 晶硅薄膜的方法与本发明实施例的低温多晶硅薄膜的制作方法相同。
采用上述薄膜晶体管制作方法制作的薄膜晶体管， 其结构如图 6所示。 本发明实施例还提供了一种薄膜晶体管的制作方法， 包括：
步骤 1、 在基板上形成一緩沖层；
緩沖层可为 SiNx层与 Si02层组成的复合緩沖层。例如，可以采用 PECVD 法或者其它沉积方法先沉积一层 50~150 nm厚（其厚度亦可根据需要设置为 其它值） 的 SiNx层； 再采用 PECVD法或者其它沉积方法沉积一层 100~350 nm厚（其厚度亦可根据需要设置为其它值） 的 Si02层， 从而在基板上形成 复合緩沖层。 另外， 緩沖层亦可为 Si02或 SiN^ 沖层；
步骤 2、 在所述緩沖层上形成栅电极和栅绝缘层；
例如， 可以在所述緩沖层上采用溅射方法形成栅电极， 并采用 PECVD 法或者其它沉积方法沉积 SiNx或 Si02以形成栅绝缘层。 此外， 因为栅绝缘 层和緩沖层的材料相同， 因此可以在形成非晶硅薄膜前形成一层栅绝缘层即 可；
步骤 3、 在所述栅绝缘层上沉积非晶硅薄膜；
可以采用 PECVD法在栅绝缘层上沉积一层非晶硅材料层， 非晶硅材料 层的厚度优选为 50 纳米， 其厚度亦可根据需要设置为其它值。 执行步骤 3 的工艺条件例如可以为：反应气体流量比为
Figure imgf000008_0001
sccm /500~1250 sccm, 射频功率为 80~120 W, 沉积腔内压强为 1800~2200 mtorr及温度为 380~400°C。 此时， 形成的非晶硅薄膜中含有氢；
步骤 4、 在低于传统 RTA晶化温度的环境下使用 RTA设备对所述非晶 硅薄膜进行多次快速热退火形成低温多晶硅薄膜， 并对低温多晶硅薄膜进行 构图形成包括源区、 漏区和沟道区的有源层；
可以先对非晶硅薄膜进行去氢。 例如， 可以在 400~500°C的温度范围内， 对所述非晶硅薄膜进行 1~2 小时的高温处理。 优选地， 通过传统退火炉在 450°C下对非晶硅薄膜保温 1.5小时， 去除非晶硅薄膜中的氢残留， 避免后续 快速热退火过程中氢溢出， 影响晶化效果。 在 600~670°C温度范围内对非晶 硅薄膜进行至少 3次快速热退火， 每次快速热退火的时间不大于 30s, 冷却 至室温。 再在 400~500°C的温度范围内， 对所述低温多晶硅薄膜进行至少 3 小时的高温处理。 之后通过掩模板对低温多晶硅薄膜进行构图， 形成包括源 区、 漏区和沟道区的有源层；
步骤 5、 通过离子注入的方式在源区和漏区掺入杂质， 并在有源层上方 形成层间绝缘层；
例如， 可以在有源层上方采用 PECVD法或者其它沉积方法沉积 SiNx或 Si02以形成层间绝缘层；
步骤 6、 在形成有层间绝缘层的基板上形成源电极和漏电极。
例如， 可以采用溅射方式在形成有层间绝缘层的基板上形成源电极和漏 电极。 源电极和漏电极可以分别通过穿过层间绝缘层的过孔连接到有源层的 源区和漏区。
通过上述步骤形成了底栅型的薄膜晶体管， 其中， 在基板上形成低温非 晶硅薄膜的方法与本发明实施例的低温多晶硅薄膜的制作方法相同。
如图 7所示， 利用本发明的薄膜晶体管的制作方法可以在一个基板上形 成多个显示面板。以基板上形成有均匀分布的 30个显示面板为例，在整个基 板上间隔地取 15个测试点。 例如， 可以在编号为 1、 3、 5、 7、 9、 11、 13、 15、 17、 19、 21、 23、 25、 27、 29的显示面板上各取一个测试点， 对每个测 试点的薄膜晶体管性能进行测试， 得到的薄膜晶体管的 I-V测试结果示于图 8。 在图 8中， 横轴为栅极电压， 纵轴为薄膜晶体管的源漏电流。 可以看出， 多个测试点的薄膜晶体管的 I-V曲线趋向一致， 证明本发明实施例制作的薄 膜晶体管的特性均匀， 易于驱动。
以上所述仅是本发明的示范性实施方式， 而非用于限制本发明的保护范 围， 本发明的保护范围由所附的权利要求确定。

Claims

权利要求书
1. 一种低温多晶硅薄膜的制作方法， 包括：
形成非晶硅薄膜；
在预设温度下对所述非晶硅薄膜进行多次快速热退火， 形成低温多晶硅 薄膜， 所述预设温度低于传统 RTA晶化温度。
2.根据权利要求 1所述的低温多晶硅薄膜的制作方法，其中所述形成非 晶硅薄膜包括：
在基板上形成一緩沖层；
在所述緩沖层上沉积所述非晶硅薄膜。
3.根据权利要求 1所述的低温多晶硅薄膜的制作方法，其中所述在预设 温度下对所述非晶硅薄膜进行多次快速热退火包括：
在 600~670°C的温度范围内， 对所述非晶硅薄膜进行至少 3次快速热退 火， 每次快速热退火的时间不大于 30s, 冷却至室温。
4.根据权利要求 3所述的低温多晶硅薄膜的制作方法，其中所述在预设 温度下对所述非晶硅薄膜进行多次快速热退火之前所述方法还包括：
在 400~500°C的温度范围内， 对所述非晶硅薄膜进行 1 ~2小时处理。
5.根据权利要求 3所述的低温多晶硅薄膜的制作方法，其中所述在预设 温度下对所述非晶硅薄膜进行多次快速热退火之后所述方法还包括：
在 400~500°C的温度范围内， 对所述低温多晶硅薄膜进行至少 3小时处 理。
6. 一种薄膜晶体管的制作方法， 包括：
在基板上形成一緩沖层；
在所述緩沖层上以权利要求 1-5任一项所述方法形成低温多晶硅薄膜； 对低温多晶硅薄膜进行构图， 形成包括源区、 漏区和沟道区的有源层； 在沟道区上方形成栅绝缘层， 并在栅绝缘层上形成栅电极；
通过离子注入的方式在源区和漏区掺入杂质， 在栅电极上方形成层间绝 缘层；
在形成有层间绝缘层的基板上形成源电极和漏电极。
7.一种薄膜晶体管的制作方法， 包括： 在基板上形成一緩沖层；
在所述緩沖层上形成栅电极和栅绝缘层；
在所述栅绝缘层上以权利要求 1-5 任一项所述方法形成低温多晶硅薄 膜；
对低温多晶硅薄膜进行构图， 形成包括源区、 漏区和沟道区的有源层； 通过离子注入的方式在源区和漏区掺入杂质， 并在有源层上方形成层间 绝缘层；
在形成有层间绝缘层的基板上形成源电极和漏电极。
PCT/CN2013/076884 2013-03-29 2013-06-06 低温多晶硅薄膜制作方法、薄膜晶体管制作方法 WO2014153841A1 (zh)

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