WO2017210923A1 - Tft背板的制作方法及tft背板 - Google Patents

Tft背板的制作方法及tft背板 Download PDF

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WO2017210923A1
WO2017210923A1 PCT/CN2016/086725 CN2016086725W WO2017210923A1 WO 2017210923 A1 WO2017210923 A1 WO 2017210923A1 CN 2016086725 W CN2016086725 W CN 2016086725W WO 2017210923 A1 WO2017210923 A1 WO 2017210923A1
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layer
amorphous silicon
oxygen
polysilicon
silicon film
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PCT/CN2016/086725
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English (en)
French (fr)
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周星宇
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深圳市华星光电技术有限公司
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Priority to US15/121,037 priority Critical patent/US10068809B2/en
Publication of WO2017210923A1 publication Critical patent/WO2017210923A1/zh

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    • H10K59/122—Pixel-defining structures or layers, e.g. banks

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT backplane and a TFT backplane.
  • An OLED (Organic Light-Emitting Diode) display also known as an organic electroluminescent display, is an emerging flat panel display device because of its simple preparation process, low cost, low power consumption, and high luminance.
  • the working temperature has wide adaptability, light volume, fast response, easy to realize color display and large screen display, easy to realize integration with integrated circuit driver, easy to realize flexible display, and the like, and thus has broad application prospects.
  • OLED can be divided into two types: passive matrix OLED (PMOLED) and active matrix OLED (AMOLED), namely direct addressing and thin film transistor matrix addressing.
  • PMOLED passive matrix OLED
  • AMOLED active matrix OLED
  • the AMOLED has pixels arranged in an array, belongs to an active display type, has high luminous efficiency, and is generally used as a high-definition large-sized display device.
  • Thin Film Transistor is the main driving component in AMOLED display devices, which is directly related to the development direction of high-performance flat panel display devices.
  • the thin film transistor has various structures, and the material of the active layer of the thin film transistor for preparing the corresponding structure is also various.
  • Low temperature poly-silicon (LTPS) material is one of the preferred ones, due to the low temperature polysilicon atom. Regular arrangement, high carrier mobility, for current-driven active matrix driven organic electroluminescent display devices, low temperature polysilicon thin film transistors can better meet the drive current requirements.
  • a method for forming a low-temperature polysilicon film currently used is a Boron-induced solid phase crystallization (SPC) method in which boron ions are implanted on the upper surface of an amorphous silicon (a-Si) film to induce crystal formation.
  • the core is then crystallized from top to bottom to form a polycrystalline silicon (poly-Si) film, but in the crystallization process, usually at the lower surface of the amorphous silicon film, that is, at the interface between the amorphous silicon film and the buffer layer.
  • Some crystal nuclei will also be randomly generated, and bottom-up crystallization will occur.
  • due to stress there are many crystal defects starting from the bottom, and the stacking is not very good.
  • the random crystal below will also affect the overall polysilicon film. Uniformity.
  • An object of the present invention is to provide a method for fabricating a TFT back sheet, which can suppress formation of a crystal nucleus on a lower surface during crystallization of an amorphous silicon film, thereby improving crystal quality and improving uniformity.
  • Another object of the present invention is to provide a TFT backplane, which has better crystal quality and uniformity of the polysilicon layer, improves the performance of the TFT, and enhances the driving effect.
  • the present invention first provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 Providing a substrate, and depositing a buffer layer on the substrate;
  • Step 2 forming an amorphous silicon film on the buffer layer, the amorphous silicon film comprising an oxygen-containing amorphous silicon film on the buffer layer and oxygen-free on the oxygen-containing amorphous silicon film Amorphous silicon film;
  • Step 3 performing boron ion doping on the amorphous silicon film, forming a boron ion doped layer on the upper surface of the amorphous silicon film, and performing rapid thermal annealing treatment on the amorphous silicon film to
  • the amorphous silicon film is crystallized into a low-temperature polysilicon film, and the low-temperature polysilicon film comprises an oxygen-containing low-temperature polysilicon film on the buffer layer and an oxygen-free low-temperature polysilicon film on the oxygen-containing low-temperature polysilicon film;
  • Step 4 removing a boron ion doped layer on the upper surface of the low temperature polysilicon film, and patterning the low temperature polysilicon film to obtain a first polysilicon layer and a second polysilicon layer which are spaced apart;
  • Step 5 forming a gate insulating layer on the first polysilicon layer, the second polysilicon layer, and the buffer layer, using a mask on both sides of the first polysilicon layer, and the whole
  • the two polysilicon layers are heavily doped with N-type or P-type, and a source contact region and a drain contact region are formed on both sides of the first polysilicon layer, and the source contact region and the drain contact region are
  • the inter-region forms a channel region, and the second polysilicon layer is heavily doped by an N-type or a P-type to form a conductor;
  • Step 6 Form a gate corresponding to the upper portion of the first polysilicon layer and a storage capacitor electrode corresponding to the upper portion of the second polysilicon layer on the gate insulating layer; the storage capacitor electrode and The second polysilicon layer forms a storage capacitor;
  • Step 7 forming a source and a drain on the interlayer dielectric layer, wherein the source and the drain are respectively in contact with a source of the first polysilicon layer through the first via hole and the second via hole The region and the drain contact region are in contact.
  • the thickness of the oxygen-containing amorphous silicon film is from one tenth to one-twentieth of the thickness of the amorphous silicon film.
  • the step 2 includes:
  • Step 21 a mixed gas of silane gas and oxygen is introduced over the buffer layer, and an oxygen-containing amorphous silicon film is deposited on the buffer layer;
  • Step 22 introducing a silane gas over the buffer layer, and depositing on the buffer layer to obtain an oxygen-free amorphous silicon film.
  • the flow rate of the silane gas is kept constant, and the flow rate of the oxygen is maximum at the beginning of the step 21, then gradually decreases, and decreases to zero at the end of the step 21.
  • the flow rate of the oxygen gas is less than or equal to one tenth of the flow rate of the silane gas; in the step 21 and the step 22, the silane gas includes one of monosilane and disilane. Or a variety.
  • the method for fabricating the TFT backplane further includes: before step 6 after the step 5, before depositing the interlayer dielectric layer after forming the gate and the storage capacitor electrode in the step 6, or depositing the layer in the step 6.
  • the entire substrate is subjected to rapid thermal annealing treatment, so that the source contact region of the first polysilicon layer is in contact with the drain in the step 5 The region, and the N-type or P-type ions doped in the entire second polysilicon layer are activated.
  • the method further includes a step of forming a planarization layer on the source, the drain, and the interlayer dielectric layer, and forming a third via hole corresponding to the drain on the planarization layer, in the planarization layer Forming a pixel electrode thereon, the pixel electrode being in contact with the drain through the third via hole;
  • a plurality of spacers disposed at intervals are formed on the pixel defining layer.
  • the present invention also provides a TFT backplane, comprising: a base substrate, a buffer layer disposed on the base substrate, and a first polysilicon layer and a second polycrystalline layer disposed on the buffer layer and spaced apart from each other a silicon layer, a gate insulating layer disposed on the first polysilicon layer, the second polysilicon layer, and the buffer layer, disposed on the gate insulating layer and corresponding to the first polysilicon a gate above the layer, a storage capacitor electrode disposed on the gate insulating layer and corresponding to the second polysilicon layer, and disposed on the gate, the storage capacitor electrode, and the gate insulating layer An interlayer dielectric layer, a source and a drain disposed on the interlayer dielectric layer;
  • the first polysilicon layer includes a source contact region and a drain contact region on both sides, and a channel region between the source contact region and the drain contact region; the source contact region and The drain contact regions are all N-type heavily doped regions or both are P-type heavily doped regions;
  • the interlayer dielectric layer and the gate insulating layer are respectively provided with a first via hole corresponding to the source contact region and the drain contact region, and a second via hole, wherein the source and the drain respectively pass
  • the first via hole and the second via hole are in contact with the source contact region of the first polysilicon layer and the drain contact region;
  • the entire second polysilicon layer is an N-type heavily doped region or a P-type heavily doped region, and the second polysilicon layer forms a storage capacitor with the storage capacitor electrode;
  • the first polysilicon layer and the second polysilicon layer each comprise an oxygen-containing low-temperature polysilicon film on the buffer layer and an oxygen-free low-temperature polysilicon film on the oxygen-containing low-temperature polysilicon film.
  • the thickness of the oxygen-containing low-temperature polysilicon film is one tenth to one-twentieth of the thickness of the first polysilicon layer and the second polysilicon layer.
  • the TFT backplane further includes: a flat layer disposed on the source, the drain, and the interlayer dielectric layer, a pixel electrode disposed on the planar layer, and the pixel electrode and the flat layer a pixel defining layer, and a plurality of spacers disposed on the pixel defining layer and spaced apart;
  • a third via hole corresponding to the drain is disposed on the flat layer, the pixel electrode is in contact with the drain through a third via hole; and the pixel defining layer is disposed on the pixel defining layer a fourth through hole above the electrode.
  • the invention also provides a method for fabricating a TFT backplane, comprising the following steps:
  • Step 1 Providing a substrate, and depositing a buffer layer on the substrate;
  • Step 2 forming an amorphous silicon film on the buffer layer, the amorphous silicon film comprising an oxygen-containing amorphous silicon film on the buffer layer and oxygen-free on the oxygen-containing amorphous silicon film Amorphous silicon film;
  • Step 3 performing boron ion doping on the amorphous silicon film, forming a boron ion doped layer on the upper surface of the amorphous silicon film, and performing rapid thermal annealing treatment on the amorphous silicon film to
  • the amorphous silicon film is crystallized into a low-temperature polysilicon film, and the low-temperature polysilicon film comprises an oxygen-containing low-temperature polysilicon film on the buffer layer and an oxygen-free low-temperature polysilicon film on the oxygen-containing low-temperature polysilicon film;
  • Step 4 removing a boron ion doped layer on the upper surface of the low temperature polysilicon film, and patterning the low temperature polysilicon film to obtain a first polysilicon layer and a second polysilicon layer which are spaced apart;
  • Step 5 forming a gate insulating layer on the first polysilicon layer, the second polysilicon layer, and the buffer layer, using a mask on both sides of the first polysilicon layer, and the whole
  • the two polysilicon layers are heavily doped with N-type or P-type, and a source contact region and a drain contact region are formed on both sides of the first polysilicon layer, and the source contact region and the drain contact region are
  • the inter-region forms a channel region, and the second polysilicon layer is heavily doped by an N-type or a P-type to form a conductor;
  • Step 6 Form a gate corresponding to the upper portion of the first polysilicon layer and a storage capacitor electrode corresponding to the upper portion of the second polysilicon layer on the gate insulating layer; the storage capacitor electrode and The second polysilicon layer forms a storage capacitor;
  • Step 7 forming a source and a drain on the interlayer dielectric layer, wherein the source and the drain are respectively in contact with a source of the first polysilicon layer through the first via hole and the second via hole The region and the drain contact region are in contact;
  • the method further includes: forming a first layer before the step 6 after the step 5, before depositing the interlayer dielectric layer after forming the gate and the storage capacitor electrode in the step 6, or after depositing the interlayer dielectric layer in the step 6.
  • the entire substrate is subjected to rapid thermal annealing treatment, so that the source contact region and the drain contact region of the first polysilicon layer and the entire second polycrystal in the step 5 are Activation of doped N-type or P-type ions in the silicon layer;
  • the method further includes a step of forming a planarization layer on the source, the drain, and the interlayer dielectric layer, and forming a third via hole corresponding to the drain on the planarization layer, in the planarization layer Forming a pixel electrode thereon, the pixel electrode being in contact with the drain through the third via hole;
  • a plurality of spacers disposed at intervals are formed on the pixel defining layer.
  • the present invention provides a method for fabricating a TFT back sheet by forming an oxygen-free amorphous silicon film on the buffer layer and oxygen-free amorphous silicon on the oxygen-containing amorphous silicon film.
  • the amorphous silicon film of the film is such that when the amorphous silicon film is crystallized by the boron ion-induced solid phase crystallization method, the contact interface between the amorphous silicon film and the buffer layer is an oxygen-containing amorphous silicon film.
  • the oxygen-containing amorphous silicon film is less likely to generate crystal nuclei during high-temperature crystallization, so that the generation of crystal nuclei occurs only in the boron ion doped layer on the upper surface of the amorphous silicon film, and crystallization occurs from top to bottom.
  • the grain quality is good and the film uniformity is good, thereby achieving the effect of improving the crystal quality and improving the uniformity.
  • the TFT back plate provided by the invention has simple process, and the crystal quality and uniformity of the polysilicon layer are better, the performance of the TFT is improved, and the driving effect is enhanced.
  • FIG. 1 is a flow chart of a method of fabricating a TFT backplane of the present invention
  • step 1 is a schematic diagram of step 1 of a method for fabricating a TFT backplane according to the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating a TFT backplane according to the present invention
  • 4-5 is a schematic diagram of step 3 of a method for fabricating a TFT backplane according to the present invention.
  • FIG. 6 is a schematic diagram of step 4 of a method for fabricating a TFT backplane according to the present invention.
  • step 7 is a schematic diagram of step 5 of a method for fabricating a TFT backplane according to the present invention.
  • step 6 is a schematic diagram of step 6 of a method for fabricating a TFT backplane according to the present invention.
  • step 7 is a schematic diagram of step 7 of a method for fabricating a TFT backplane according to the present invention.
  • FIG. 10 is a schematic view showing the step 8 of the method for fabricating the TFT backplane of the present invention and a schematic structural view of the TFT backplane of the present invention.
  • the present invention first provides a method for fabricating a TFT backplane, including the following steps:
  • Step 1 As shown in FIG. 2, a substrate 10 is provided on which a buffer layer 20 is deposited.
  • the base substrate 10 is a glass substrate.
  • the step 1 further includes: cleaning and baking the base substrate 10 before depositing the buffer layer 20 on the base substrate 10.
  • the buffer layer 20 includes one or a combination of two of a silicon nitride (SiN x ) layer and a silicon oxide (SiO x ) layer. Specifically, the thicknesses of the silicon nitride layer and the silicon oxide layer are respectively
  • Step 2 as shown in FIG. 3, forming an amorphous silicon film 310 on the buffer layer 20, the amorphous silicon film 310 including an oxygen-containing amorphous silicon film 311 on the buffer layer 20, and The oxygen-free amorphous silicon film 312 on the oxygen-containing amorphous silicon film 311.
  • the thickness of the oxygen-containing amorphous silicon film 311 is from one tenth to one-twentieth, preferably one tenth, of the thickness of the amorphous silicon film 310.
  • the step 2 includes:
  • Step 21 a mixed gas of silane gas and oxygen gas is introduced over the buffer layer 20, and an oxygen-containing amorphous silicon film 311 is deposited on the buffer layer 20.
  • the flow rate of the silane gas is kept constant, and the flow rate of the oxygen is maximum at the beginning of step 21, then gradually decreases, and decreases to the end of step 21 to zero.
  • the flow rate of the oxygen is less than or equal to one tenth of the flow rate of the silane gas.
  • Step 22 introducing a silane gas over the buffer layer 20, and depositing on the buffer layer 20 to obtain an oxygen-free amorphous silicon film 312.
  • the silane gas comprises one or more of monosilane (SiH 4 ) and disilane (Si 2 H 6 ).
  • Step 3 as shown in FIG. 4-5, the amorphous silicon film 310 is doped with boron ions, and a boron ion doped layer 313 is formed on the upper surface of the amorphous silicon film 310.
  • the silicon thin film 310 is subjected to rapid thermal annealing treatment to crystallize the amorphous silicon thin film 310 into a low temperature polysilicon film 330, and the low temperature polysilicon film 330 includes an oxygen-containing low temperature polysilicon film 331 on the buffer layer 20 and The oxygen-free low temperature polysilicon film 332 on the oxygen-containing low temperature polysilicon film 331.
  • the oxygen-containing amorphous silicon film 311 is in a high-temperature crystallization process.
  • the crystal nucleus is not easily generated in the middle, so that the generation of the crystal nucleus occurs only in the boron ion doped layer 313 on the upper surface, and crystallization occurs from the top to the bottom, the grain quality is good, and the film uniformity is good.
  • the annealing temperature of the rapid thermal annealing treatment is 600 ° C to 730 ° C, and the annealing holding time is 10 min -1 h.
  • the boron ion doping process implants an ion concentration of 1 ⁇ 10 15 to 1 ⁇ 10 16 ions/cm 2 and an ion energy of 5-20 keV.
  • Step 4 as shown in FIG. 6, the boron ion doped layer 313 on the upper surface of the low temperature polysilicon film 330 is removed, and the low temperature polysilicon film 330 is patterned to obtain the first polysilicon layer 30 disposed at intervals.
  • the second polysilicon layer 40 as shown in FIG. 6, the boron ion doped layer 313 on the upper surface of the low temperature polysilicon film 330 is removed, and the low temperature polysilicon film 330 is patterned to obtain the first polysilicon layer 30 disposed at intervals.
  • the second polysilicon layer 40 is
  • the boron ion doping layer 313 on the upper surface of the low temperature polysilicon film 330 is removed by dry etching the low temperature polysilicon film 330.
  • the step 4 further includes performing channel doping on the first polysilicon layer 30.
  • the process of the channel doping may be: performing P-type light doping on the entire first polysilicon layer 30, or performing P-type light doping on the intermediate region of the first polysilicon layer 30. .
  • the ion implanted in the P-type lightly doped process is boron ion (B+).
  • the P-type lightly doped process implant has an ion concentration of 1 ⁇ 10 12 to 1 ⁇ 10 13 ions/cm 2 and an ion energy of 5-20 keV.
  • Step 5 as shown in FIG. 7, a gate insulating layer 50 is formed on the first polysilicon layer 30, the second polysilicon layer 40, and the buffer layer 20, and the first plurality is used by using a mask.
  • Crystal silicon layer 30 N-type or P-type heavily doped on both sides and the entire second polysilicon layer 40, and a source contact region 31 and a drain contact region 32 are formed on both sides of the first polysilicon layer 30, A region between the source contact region 31 and the drain contact region 32 forms a channel region 33, and the second polysilicon layer 40 is heavily doped by an N-type or a P-type to form a conductor.
  • the ions implanted in the N-type heavily doped process are phosphorus ions (P+), and preferably, phosphorus ions are doped by using a phosphine (PH 3 ) gas.
  • P+ phosphorus ions
  • PH 3 phosphine
  • the ion implanted in the P-type heavily doped process is boron ion, and preferably, boron ion doping is performed using diborane (B 2 H 6 ) gas.
  • the heavily doped N-type ion implantation process is the concentration of 1 ⁇ 10 15 ⁇ 1 ⁇ 10 16 ions / cm 2, the ion energy of 5 ⁇ 50keV; ion implantation process of the P-type heavily doped The concentration is 1 ⁇ 10 15 to 1 ⁇ 10 16 ions/cm 2 , and the ion energy is 5 to 50 keV.
  • Step 6 as shown in FIG. 8, a gate electrode 61 corresponding to the upper portion of the first polysilicon layer 30 and a top portion of the second polysilicon layer 40 are formed on the gate insulating layer 50.
  • An interlayer dielectric layer 70 is deposited on the gate electrode 61, the storage capacitor electrode 62, and the gate insulating layer 50, and the interlayer dielectric layer 70 and the gate insulating layer 50 are respectively formed to correspond to source contacts. a first via 71 and a second via 72 above the region 31 and the drain contact region 32.
  • the gate electrode 61 and the storage capacitor electrode 62 are formed by depositing a gate metal layer on the gate insulating layer 50, and patterning the gate metal layer by using a photolithography process. The gate 61 and the storage capacitor electrode 62 are obtained.
  • the gate insulating layer 50 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer. Specifically, the thicknesses of the silicon nitride layer and the silicon oxide layer are respectively
  • the gate electrode 61 and the storage capacitor electrode 62 each include two molybdenum (Mo) layers and an aluminum (Al) layer between the two molybdenum layers, or only a single layer of molybdenum layer or a single layer of aluminum.
  • the thickness of the gate 61 is
  • the interlayer dielectric layer 70 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer. Specifically, the thickness of the interlayer dielectric layer 70 is
  • the method for fabricating the TFT backplane further includes: before step 6 after the step 5, before the interlayer dielectric layer 70 is deposited after the gate 61 and the storage capacitor electrode 62 are formed in the step 6, or After the step 6 of depositing the interlayer dielectric layer 70 to form the first via hole 71 and the second via hole 72, the entire substrate is subjected to rapid thermal annealing treatment, so that the step 1 is in the first polysilicon layer.
  • the source contact region 31 and the drain contact region 32 of 30, and the N-type or P-type ions doped in the entire second polysilicon layer 40 are activated to improve their effectiveness.
  • the rapid thermal annealing treatment has an annealing temperature of 450 ° C to 650 ° C and an annealing holding time of 1 min to 1 h.
  • Step 7 as shown in FIG. 9, a source 81 and a drain 82 are formed on the interlayer dielectric layer 70.
  • the source 81 and the drain 82 pass through the first via 71 and the second pass, respectively.
  • the hole 72 is in contact with the source contact region 31 of the first polysilicon layer 30 and the drain contact region 32.
  • the source 81 and the drain 82 each include two molybdenum layers and an aluminum layer between the two molybdenum layers, or only a single layer of molybdenum or a single layer of aluminum.
  • the thickness of the source 81 and the drain 82 are respectively
  • Step 8 as shown in FIG. 10, a flat layer 90 is formed on the source electrode 81, the drain electrode 82, and the interlayer dielectric layer 70, and the flat layer 90 is formed on the flat layer 90 corresponding to the upper portion of the drain electrode 82.
  • a third via 91 a pixel electrode 100 is formed on the flat layer 90, and the pixel electrode 100 is in contact with the drain 82 through a third via 91;
  • a plurality of spacers 130 disposed at intervals are formed on the pixel defining layer 110.
  • the fourth through hole 111 is used to form an organic light emitting layer of the OLED device, and the spacer 130 is used to support the upper cover plate after the package.
  • the material of the spacer 130 is an organic material.
  • the flat layer 90 and the pixel defining layer 110 are organic materials.
  • the material of the pixel electrode 100 is indium tin oxide (ITO).
  • an amorphous silicon film 310 including an oxygen-containing amorphous silicon film 311 and an oxygen-free amorphous silicon film 312 on the oxygen-containing amorphous silicon film 311 is formed on the buffer layer 20.
  • the amorphous silicon film 310 is crystallized by the boron ion-induced solid phase crystallization method, the contact interface between the amorphous silicon film 310 and the buffer layer 20 is an oxygen-containing amorphous silicon film 311, and oxygen is contained.
  • the amorphous silicon film 311 does not easily generate crystal nuclei during high-temperature crystallization, so that generation of crystal nuclei occurs only in the boron ion doped layer 313 on the upper surface of the amorphous silicon film 310, and crystallization occurs from top to bottom.
  • the quality is good, and the film uniformity is good, thereby achieving the effect of improving the crystal quality and improving the uniformity.
  • the present invention further provides a TFT backplane, including: a substrate substrate 10, a buffer layer 20 disposed on the base substrate 10, and a buffer layer. a first polysilicon layer 30 and a second polysilicon layer 40 disposed on the layer 20 and spaced apart from each other, and gates disposed on the first polysilicon layer 30, the second polysilicon layer 40, and the buffer layer 20 a pole insulating layer 50, a gate 61 disposed on the gate insulating layer 50 and corresponding to the upper surface of the first polysilicon layer 30, disposed on the gate insulating layer 50 and corresponding to the second
  • the storage capacitor electrode 62 above the polysilicon layer 40, the interlayer dielectric layer 70 disposed on the gate 61, the storage capacitor electrode 62, and the gate insulating layer 50 are disposed on the interlayer dielectric layer 70.
  • the first polysilicon layer 30 includes a source contact region 31 and a drain contact region 32 on both sides, and a channel region 33 between the source contact region 31 and the drain contact region 32;
  • the source contact region 31 and the drain contact region 32 are both N-type heavily doped regions or both are P-type heavily doped regions;
  • the interlayer dielectric layer 70 and the gate insulating layer 50 are respectively provided with a first via hole 71 corresponding to the source contact region 31 and the drain contact region 32, and a second via hole 72, the source 81 and the drain electrode 82 are in contact with the source contact region 31 of the first polysilicon layer 30 and the drain contact region 32 through the first via hole 71 and the second via hole 72, respectively;
  • the entire second polysilicon layer 40 is an N-type heavily doped region or a P-type heavily doped region, and the second polysilicon layer 40 forms a storage capacitor with the storage capacitor electrode 62;
  • the first polysilicon layer 30 and the second polysilicon layer 40 each include an oxygen-containing low-temperature polysilicon film 331 on the buffer layer 20 and an oxygen-free low temperature layer on the oxygen-containing low-temperature polysilicon film 331. Polysilicon film 332.
  • the TFT backplane further includes: a flat layer 90 disposed on the source 81, the drain 82, and the interlayer dielectric layer 70, and a pixel electrode 100 disposed on the flat layer 90. a pixel defining layer 110 on the pixel electrode 100 and the flat layer 90, and a plurality of spacers 130 disposed on the pixel defining layer 110 and spaced apart;
  • a third via hole 91 corresponding to the upper surface of the drain electrode 82 is disposed on the flat layer 90, and the pixel electrode 100 is in contact with the drain electrode 82 through a third via hole 91;
  • a fourth through hole 111 corresponding to the upper side of the pixel electrode 100 is provided.
  • the fourth through hole 111 is used to form an organic light emitting layer of the OLED device.
  • the material of the spacer 130 is an organic material.
  • the flat layer 90 and the pixel defining layer 110 are organic materials.
  • the material of the pixel electrode 100 is indium tin oxide.
  • the base substrate 10 is a glass substrate.
  • the buffer layer 20 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer. Specifically, the thicknesses of the silicon nitride layer and the silicon oxide layer are respectively
  • the thickness of the oxygen-containing low-temperature polysilicon film 331 is one tenth to one-twentieth of the thickness of the first polysilicon layer 30 and the second polysilicon layer 40. It is preferably one tenth.
  • the gate insulating layer 50 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer. Specifically, the thicknesses of the silicon nitride layer and the silicon oxide layer are respectively
  • the gate electrode 61 and the storage capacitor electrode 62 each include a molybdenum layer and an aluminum layer between the two molybdenum layers, or only a single layer of molybdenum layer or a single layer of aluminum.
  • the thickness of the gate 61 is
  • the ions doped in the N-type heavily doped region are phosphorus ions, and the P-type heavily doped
  • the ions incorporated in the region are boron ions.
  • the channel region 33 is a P-type lightly doped region, and the ions doped in the P-type lightly doped region are boron ions.
  • the concentration of the ions doped in the N-type heavily doped region is 1 ⁇ 10 15 to 1 ⁇ 10 16 ions/cm 2
  • the concentration of the ions doped in the heavily doped P-type region is 1 ⁇ 10.
  • the ion concentration of the P-type lightly doped region is 1 ⁇ 10 12 to 1 ⁇ 10 13 ions / cm 2 .
  • the interlayer dielectric layer 70 includes one or a combination of two of a silicon nitride layer and a silicon oxide layer. Specifically, the thickness of the interlayer dielectric layer 70 is
  • the source 81 and the drain 82 each include two molybdenum layers and an aluminum layer between the two molybdenum layers, or only a single layer of molybdenum or a single layer of aluminum.
  • the thickness of the source 81 and the drain 82 are respectively
  • the gate electrode 61, the source electrode 81, the drain electrode 82, and the first polysilicon layer 30 constitute a driving TFT for driving the organic light emitting layer of the OLED device to emit light.
  • the TFT backplane has a simple process, and the first polysilicon layer 30 and the second polysilicon layer 40 have better crystal quality and uniformity, which improves the performance of the TFT and enhances the driving effect thereof.
  • the present invention provides a method for fabricating a TFT backplane and a TFT backplane.
  • the method for fabricating the TFT back sheet of the present invention comprises: forming an amorphous silicon film comprising an oxygen-containing amorphous silicon film and an oxygen-free amorphous silicon film on the oxygen-containing amorphous silicon film on the buffer layer, thereby adopting
  • the amorphous silicon film is crystallized by the boron ion-induced solid phase crystallization method, the contact interface between the amorphous silicon film and the buffer layer is an oxygen-containing amorphous silicon film, and the oxygen-containing amorphous silicon film is The crystal nucleus is not easily generated during high-temperature crystallization, so that the nucleation occurs only in the boron ion doped layer on the upper surface of the amorphous silicon film, and crystallization occurs from top to bottom, the grain quality is good, and the film uniformity is good. Thereby, the effect of improving the crystal quality and improving the uniformity

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Abstract

一种TFT背板的制作方法及TFT背板。该制作方法通过在缓冲层（20）上制作包括含氧非晶硅薄膜（311）以及位于含氧非晶硅薄膜上的不含氧非晶硅薄膜（312）的非晶硅薄膜（310），使得采用硼离子诱导固相晶化法对非晶硅薄膜进行晶化处理时，由于非晶硅薄膜与缓冲层的接触界面为含氧非晶硅薄膜，而含氧非晶硅薄膜在高温结晶过程中不容易产生晶核，从而使得晶核的产生仅发生在非晶硅薄膜上表面的硼离子掺杂层中，并且自上而下发生结晶，晶粒质量好，薄膜均一性好，从而达到提高结晶质量及改善均一性的效果。该TFT背板，制程简单，其中多晶硅层的结晶质量与均一性较好，提升了TFT的性能，增强其驱动效果。

Description

TFT背板的制作方法及TFT背板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT背板的制作方法及TFT背板。
背景技术
OLED(Organic Light-Emitting Diode，有机发光二极管)显示器，也称为有机电致发光显示器，是一种新兴的平板显示装置，由于其具有制备工艺简单、成本低、功耗低、发光亮度高、工作温度适应范围广、体积轻薄、响应速度快，而且易于实现彩色显示和大屏幕显示、易于实现和集成电路驱动器相匹配、易于实现柔性显示等优点，因而具有广阔的应用前景。
OLED按照驱动方式可以分为无源矩阵型OLED(Passive Matrix OLED，PMOLED)和有源矩阵型OLED(Active Matrix OLED，AMOLED)两大类，即直接寻址和薄膜晶体管矩阵寻址两类。其中，AMOLED具有呈阵列式排布的像素，属于主动显示类型，发光效能高，通常用作高清晰度的大尺寸显示装置。
薄膜晶体管(Thin Film Transistor，简称TFT)是AMOLED显示装置中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管的有源层的材料也具有多种，低温多晶硅(Low Temperature Poly-silicon，简称LTPS)材料是其中较为优选的一种，由于低温多晶硅的原子规则排列，载流子迁移率高，对于电流驱动式的有源矩阵驱动式有机电致发光显示装置而言，低温多晶硅薄膜晶体管可以更好的满足驱动电流要求。
目前采用的一种形成低温多晶硅薄膜的方法是硼离子(Boron)诱导固相晶化(SPC)法，该方法是在非晶硅(a-Si)薄膜的上表面植入硼离子诱导产生晶核，然后自上而下结晶最终形成多晶硅(poly-Si)薄膜，但是，在晶化过程中，通常在非晶硅薄膜的下表面，即非晶硅薄膜与缓冲(buffer)层的界面处也会随机产生一些晶核，发生自下而上的结晶，一般由于应力作用，从下方开始的结晶缺陷比较多，堆叠也不是很好，另一方面下方随机的结晶，也会影响多晶硅薄膜整体的均一性。
发明内容
本发明的目的在于提供一种TFT背板的制作方法，在非晶硅薄膜的晶化过程中可抑制下表面晶核的形成，从而提高结晶质量，改善均一性。
本发明的目的还在于提供一种TFT背板，多晶硅层的结晶质量与均一性较好，提升了TFT的性能，增强其驱动效果。
为实现上述目的，本发明首先提供一种TFT背板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上沉积缓冲层；
步骤2、在所述缓冲层上形成非晶硅薄膜，所述非晶硅薄膜包括位于所述缓冲层上的含氧非晶硅薄膜以及位于所述含氧非晶硅薄膜上的不含氧非晶硅薄膜；
步骤3、对所述非晶硅薄膜进行硼离子掺杂，在所述非晶硅薄膜的上表面形成一硼离子掺杂层，对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜包括位于所述缓冲层上的含氧低温多晶硅薄膜及位于所述含氧低温多晶硅薄膜上的不含氧低温多晶硅薄膜；
步骤4、去除所述低温多晶硅薄膜上表面的硼离子掺杂层，对所述低温多晶硅薄膜进行图形化处理，得到间隔设置的第一多晶硅层与第二多晶硅层；
步骤5、在所述第一多晶硅层、第二多晶硅层、及缓冲层上形成栅极绝缘层，采用一道掩模对所述第一多晶硅层的两侧、及整个第二多晶硅层进行N型或者P型重掺杂，在所述第一多晶硅层的两侧形成源极接触区与漏极接触区，所述源极接触区与漏极接触区之间的区域形成沟道区，所述第二多晶硅层经过N型或者P型重掺杂后形成导体；
步骤6、在所述栅极绝缘层上形成对应于所述第一多晶硅层上方的栅极、及对应于所述第二多晶硅层上方的存储电容电极；所述存储电容电极与第二多晶硅层形成存储电容；
在所述栅极、存储电容电极、及栅极绝缘层上沉积层间介电层，在所述层间介电层及栅极绝缘层上形成分别对应于源极接触区及漏极接触区上方的第一通孔、及第二通孔；
步骤7、在所述层间介电层上形成源极与漏极，所述源极、及漏极分别通过第一通孔、及第二通孔与第一多晶硅层的源极接触区、及漏极接触区相接触。
所述含氧非晶硅薄膜的厚度为所述非晶硅薄膜的厚度的十分之一至二十分之一。
所述步骤2包括：
步骤21、在所述缓冲层上方通入硅烷气体和氧气的混合气体，在所述缓冲层上沉积得到含氧非晶硅薄膜；
步骤22、在所述缓冲层上方通入硅烷气体，在所述缓冲层上沉积得到不含氧非晶硅薄膜。
所述步骤21中，所述硅烷气体的流量一直保持不变，所述氧气的流量在步骤21开始时最大，之后逐渐减小，到步骤21结束时减少为零。
所述步骤21中，所述氧气的流量小于或等于所述硅烷气体的流量的十分之一；所述步骤21与步骤22中，所述硅烷气体包括甲硅烷、及乙硅烷中的一种或多种。
所述TFT背板的制作方法还包括：在所述步骤5之后步骤6之前、在所述步骤6形成栅极与存储电容电极之后沉积层间介电层之前、或者在所述步骤6沉积层间介电层之后形成第一通孔与第二通孔之前，对整个基板进行快速热退火处理，使所述步骤5中在所述第一多晶硅层的源极接触区与漏极接触区、及整个第二多晶硅层中掺杂的N型或P型离子活化。
还包括步骤8、在所述源极、漏极、及层间介电层上形成平坦层，在所述平坦层上形成对应于所述漏极上方的第三通孔，在所述平坦层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触；
在所述像素电极、及平坦层上形成像素定义层，在所述像素定义层上形成对应于所述像素电极上方的第四通孔；
在所述像素定义层上形成间隔设置的数个间隔物。
本发明还提供一种TFT背板，包括：衬底基板、设于所述衬底基板上的缓冲层、设于所述缓冲层上且间隔设置的第一多晶硅层与第二多晶硅层、设于所述第一多晶硅层、第二多晶硅层、及缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述第一多晶硅层上方的栅极、设于所述栅极绝缘层上且对应于所述第二多晶硅层上方的存储电容电极、设于所述栅极、存储电容电极、及栅极绝缘层上的层间介电层、设于所述层间介电层上的源极与漏极；
其中，所述第一多晶硅层包括位于两侧的源极接触区与漏极接触区、及位于源极接触区与漏极接触区之间的沟道区；所述源极接触区与漏极接触区均为N型重掺杂区或均为P型重掺杂区；
所述层间介电层及栅极绝缘层上设有分别对应于源极接触区及漏极接触区上方的第一通孔、及第二通孔，所述源极、及漏极分别通过第一通孔、及第二通孔与第一多晶硅层的源极接触区、及漏极接触区相接触；
整个第二多晶硅层为N型重掺杂区或P型重掺杂区，所述第二多晶硅层与存储电容电极形成存储电容；
所述第一多晶硅层、及第二多晶硅层均包括位于所述缓冲层上的含氧低温多晶硅薄膜及位于所述含氧低温多晶硅薄膜上的不含氧低温多晶硅薄膜。
所述含氧低温多晶硅薄膜的厚度为所述第一多晶硅层、及第二多晶硅层的厚度的十分之一至二十分之一。
所述TFT背板还包括：设于所述源极、漏极、及层间介电层上的平坦层、设于所述平坦层上的像素电极、设于所述像素电极、及平坦层上的像素定义层、以及设于所述像素定义层上且间隔设置的数个间隔物；
所述平坦层上设有对应于所述漏极上方的第三通孔，所述像素电极通过第三通孔与所述漏极相接触；所述像素定义层上设有对应于所述像素电极上方的第四通孔。
本发明还提供一种TFT背板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上沉积缓冲层；
步骤2、在所述缓冲层上形成非晶硅薄膜，所述非晶硅薄膜包括位于所述缓冲层上的含氧非晶硅薄膜以及位于所述含氧非晶硅薄膜上的不含氧非晶硅薄膜；
步骤3、对所述非晶硅薄膜进行硼离子掺杂，在所述非晶硅薄膜的上表面形成一硼离子掺杂层，对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜包括位于所述缓冲层上的含氧低温多晶硅薄膜及位于所述含氧低温多晶硅薄膜上的不含氧低温多晶硅薄膜；
步骤4、去除所述低温多晶硅薄膜上表面的硼离子掺杂层，对所述低温多晶硅薄膜进行图形化处理，得到间隔设置的第一多晶硅层与第二多晶硅层；
步骤5、在所述第一多晶硅层、第二多晶硅层、及缓冲层上形成栅极绝缘层，采用一道掩模对所述第一多晶硅层的两侧、及整个第二多晶硅层进行N型或者P型重掺杂，在所述第一多晶硅层的两侧形成源极接触区与漏极接触区，所述源极接触区与漏极接触区之间的区域形成沟道区，所述第二多晶硅层经过N型或者P型重掺杂后形成导体；
步骤6、在所述栅极绝缘层上形成对应于所述第一多晶硅层上方的栅极、及对应于所述第二多晶硅层上方的存储电容电极；所述存储电容电极与第二多晶硅层形成存储电容；
在所述栅极、存储电容电极、及栅极绝缘层上沉积层间介电层，在所述层间介电层及栅极绝缘层上形成分别对应于源极接触区及漏极接触区上方的第一通孔、及第二通孔；
步骤7、在所述层间介电层上形成源极与漏极，所述源极、及漏极分别通过第一通孔、及第二通孔与第一多晶硅层的源极接触区、及漏极接触区相接触；
还包括：在所述步骤5之后步骤6之前、在所述步骤6形成栅极与存储电容电极之后沉积层间介电层之前、或者在所述步骤6沉积层间介电层之后形成第一通孔与第二通孔之前，对整个基板进行快速热退火处理，使所述步骤5中在所述第一多晶硅层的源极接触区与漏极接触区、及整个第二多晶硅层中掺杂的N型或P型离子活化；
还包括步骤8、在所述源极、漏极、及层间介电层上形成平坦层，在所述平坦层上形成对应于所述漏极上方的第三通孔，在所述平坦层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触；
在所述像素电极、及平坦层上形成像素定义层，在所述像素定义层上形成对应于所述像素电极上方的第四通孔；
在所述像素定义层上形成间隔设置的数个间隔物。
本发明的有益效果：本发明提供的一种TFT背板的制作方法，通过在缓冲层上制作包括含氧非晶硅薄膜以及位于所述含氧非晶硅薄膜上的不含氧非晶硅薄膜的非晶硅薄膜，使得采用硼离子诱导固相晶化法对所述非晶硅薄膜进行晶化处理时，由于所述非晶硅薄膜与缓冲层的接触界面为含氧非晶硅薄膜，而含氧非晶硅薄膜在高温结晶过程中不容易产生晶核，从而使得晶核的产生仅发生在非晶硅薄膜上表面的硼离子掺杂层中，并且自上而下发生结晶，晶粒质量好，薄膜均一性好，从而达到提高结晶质量及改善均一性的效果。本发明提供的一种TFT背板，制程简单，其中的多晶硅层的结晶质量与均一性较好，提升了TFT的性能，增强其驱动效果。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的TFT背板的制作方法的流程图；
图2为本发明的TFT背板的制作方法的步骤1的示意图；
图3为本发明的TFT背板的制作方法的步骤2的示意图；
图4-5为本发明的TFT背板的制作方法的步骤3的示意图；
图6为本发明的TFT背板的制作方法的步骤4的示意图；
图7为本发明的TFT背板的制作方法的步骤5的示意图；
图8为本发明的TFT背板的制作方法的步骤6的示意图；
图9为本发明的TFT背板的制作方法的步骤7的示意图；
图10为本发明的TFT背板的制作方法的步骤8的示意图暨本发明的TFT背板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明首先提供一种TFT背板的制作方法，包括如下步骤：
步骤1、如图2所示，提供一衬底基板10，在所述衬底基板10上沉积缓冲层20。
具体的，所述衬底基板10为玻璃基板。
具体的，所述步骤1还包括：在所述衬底基板10上沉积缓冲层20之前，对所述衬底基板10进行清洗和烘烤。
具体的，所述缓冲层20包括氮化硅(SiNx)层、及氧化硅(SiOx)层中的一种或两种的组合。具体的，所述氮化硅层、及氧化硅层的厚度分别为
Figure PCTCN2016086725-appb-000001
步骤2、如图3所示，在所述缓冲层20上形成非晶硅薄膜310，所述非晶硅薄膜310包括位于所述缓冲层20上的含氧非晶硅薄膜311以及位于所述含氧非晶硅薄膜311上的不含氧非晶硅薄膜312。
具体的，所述含氧非晶硅薄膜311的厚度为所述非晶硅薄膜310的厚度的十分之一至二十分之一，优选为十分之一。
具体的，所述步骤2包括：
步骤21、在所述缓冲层20上方通入硅烷气体和氧气的混合气体，在所述缓冲层20上沉积得到含氧非晶硅薄膜311。
具体的，所述步骤21中，所述硅烷气体的流量一直保持不变，所述氧气的流量在步骤21开始时最大，之后逐渐减小，到步骤21结束时减少为 零。
优选的，所述步骤21中，所述氧气的流量小于或等于所述硅烷气体的流量的十分之一。
步骤22、在所述缓冲层20上方通入硅烷气体，在所述缓冲层20上沉积得到不含氧非晶硅薄膜312。
具体的，所述步骤21与步骤22中，所述硅烷气体包括甲硅烷(SiH4)、及乙硅烷(Si2H6)中的一种或多种。
步骤3、如图4-5所示，对所述非晶硅薄膜310进行硼离子掺杂，在所述非晶硅薄膜310的上表面形成一硼离子掺杂层313，对所述非晶硅薄膜310进行快速热退火处理，使所述非晶硅薄膜310结晶转化为低温多晶硅薄膜330，所述低温多晶硅薄膜330包括位于所述缓冲层20上的含氧低温多晶硅薄膜331及位于所述含氧低温多晶硅薄膜331上的不含氧低温多晶硅薄膜332。
具体的，所述步骤3的晶化过程中，由于所述非晶硅薄膜310与缓冲层20的接触界面为含氧非晶硅薄膜311，所述含氧非晶硅薄膜311在高温结晶过程中不容易产生晶核，使得晶核的产生仅发生在上表面的硼离子掺杂层313中，并且自上而下发生结晶，晶粒质量好，薄膜均一性好。
具体的，所述步骤3中，所述快速热退火处理的退火温度为600℃～730℃，退火保温时间为10min-1h。
具体的，所述步骤3中，所述硼离子掺杂制程植入的离子浓度为1×1015～1×1016ions/cm2，离子能量为5～20keV。
步骤4、如图6所示，去除所述低温多晶硅薄膜330上表面的硼离子掺杂层313，对所述低温多晶硅薄膜330进行图形化处理，得到间隔设置的第一多晶硅层30与第二多晶硅层40。
具体的，所述步骤4中，去除所述低温多晶硅薄膜330上表面的硼离子掺杂层313的方法为：对所述低温多晶硅薄膜330进行干蚀刻处理。
具体的，所述步骤4还包括：对所述第一多晶硅层30进行沟道掺杂。
具体的，所述沟道掺杂的制程可以为：对整个第一多晶硅层30进行P型轻掺杂，或者对所述第一多晶硅层30的中间区域进行P型轻掺杂。
具体的，所述P型轻掺杂制程植入的离子为硼离子(B+)。
具体的，所述P型轻掺杂制程植入的离子浓度为1×1012～1×1013ions/cm2，离子能量为5～20keV。
步骤5、如图7所示，在所述第一多晶硅层30、第二多晶硅层40、及缓冲层20上形成栅极绝缘层50，采用一道掩模对所述第一多晶硅层30的 两侧、及整个第二多晶硅层40进行N型或者P型重掺杂，在所述第一多晶硅层30的两侧形成源极接触区31与漏极接触区32，所述源极接触区31与漏极接触区32之间的区域形成沟道区33，所述第二多晶硅层40经过N型或者P型重掺杂后形成导体。
具体的，所述N型重掺杂制程植入的离子为磷离子(P+)，优选的，采用磷化氢(PH3)气体进行磷离子掺杂。
具体的，所述P型重掺杂制程植入的离子为硼离子，优选的，采用乙硼烷(B2H6)气体进行硼离子掺杂。
具体的，所述N型重掺杂制程植入的离子浓度为1×1015～1×1016ions/cm2，离子能量为5～50keV；所述P型重掺杂制程植入的离子浓度为1×1015～1×1016ions/cm2，离子能量为5～50keV。
步骤6、如图8所示，在所述栅极绝缘层50上形成对应于所述第一多晶硅层30上方的栅极61、及对应于所述第二多晶硅层40上方的存储电容电极62；所述存储电容电极62与第二多晶硅层40形成存储电容；
在所述栅极61、存储电容电极62、及栅极绝缘层50上沉积层间介电层70，在所述层间介电层70及栅极绝缘层50上形成分别对应于源极接触区31及漏极接触区32上方的第一通孔71、及第二通孔72。
具体的，所述栅极61、及存储电容电极62的形成方法为：在所述栅极绝缘层50上沉积栅极金属层，采用一道光刻制程对所述栅极金属层进行图形化处理，得到栅极61、及存储电容电极62。
具体的，所述栅极绝缘层50包括氮化硅层、及氧化硅层中的一种或两种的组合。具体的，所述氮化硅层、及氧化硅层的厚度分别为
Figure PCTCN2016086725-appb-000002
具体的，所述栅极61、及存储电容电极62均包括两钼(Mo)层及位于两钼层之间的一铝(Al)层、或仅包括单层钼层或单层铝层。具体的，所述栅极61的厚度为
Figure PCTCN2016086725-appb-000003
具体的，所述层间介电层70包括氮化硅层、及氧化硅层中的一种或两种的组合。具体的，所述层间介电层70的厚度为
Figure PCTCN2016086725-appb-000004
具体的，所述TFT背板的制作方法还包括：在所述步骤5之后步骤6之前、在所述步骤6形成栅极61与存储电容电极62之后沉积层间介电层70之前、或者在所述步骤6沉积层间介电层70之后形成第一通孔71与第二通孔72之前，对整个基板进行快速热退火处理，使所述步骤5中在所述第一多晶硅层30的源极接触区31与漏极接触区32、及整个第二多晶硅层40中掺杂的N型或P型离子活化，提高其有效性。所述快速热退火处理的退火温度为450℃～650℃，退火保温时间为1min-1h。
步骤7、如图9所示，在所述层间介电层70上形成源极81与漏极82，所述源极81、及漏极82分别通过第一通孔71、及第二通孔72与第一多晶硅层30的源极接触区31、及漏极接触区32相接触。
具体的，所述源极81与漏极82均包括两钼层及位于两钼层之间的一铝层、或仅包括单层钼层或单层铝层。具体的，所述源极81与漏极82的厚度分别为
Figure PCTCN2016086725-appb-000005
步骤8、如图10所示，在所述源极81、漏极82、及层间介电层70上形成平坦层90，在所述平坦层90上形成对应于所述漏极82上方的第三通孔91，在所述平坦层90上形成像素电极100，所述像素电极100通过第三通孔91与所述漏极82相接触；
在所述像素电极100、及平坦层90上形成像素定义层110，在所述像素定义层110上形成对应于所述像素电极100上方的第四通孔111；
在所述像素定义层110上形成间隔设置的数个间隔物130。
具体的，所述第四通孔111内用于形成OLED器件的有机发光层，所述间隔物130用于在封装后支撑上方的盖板。
具体的，所述间隔物130的材料为有机材料。
具体的，所述平坦层90与像素定义层110为有机材料。
具体的，所述像素电极100的材料为氧化铟锡(ITO)。
上述TFT背板的制作方法，通过在缓冲层20上制作包括含氧非晶硅薄膜311以及位于所述含氧非晶硅薄膜311上的不含氧非晶硅薄膜312的非晶硅薄膜310，使得采用硼离子诱导固相晶化法对非晶硅薄膜310进行晶化处理时，由于所述非晶硅薄膜310与缓冲层20的接触界面为含氧非晶硅薄膜311，而含氧非晶硅薄膜311在高温结晶过程中不容易产生晶核，使得晶核的产生仅发生在非晶硅薄膜310上表面的硼离子掺杂层313中，并且自上而下发生结晶，晶粒质量好，薄膜均一性好，从而达到提高结晶质量及改善均一性的效果。
请参阅图10，基于上述TFT背板的制作方法，本发明还提供一种TFT背板，包括：衬底基板10、设于所述衬底基板10上的缓冲层20、设于所述缓冲层20上且间隔设置的第一多晶硅层30与第二多晶硅层40、设于所述第一多晶硅层30、第二多晶硅层40、及缓冲层20上的栅极绝缘层50、设于所述栅极绝缘层50上且对应于所述第一多晶硅层30上方的栅极61、设于所述栅极绝缘层50上且对应于所述第二多晶硅层40上方的存储电容电极62、设于所述栅极61、存储电容电极62、及栅极绝缘层50上的层间介电层70、设于所述层间介电层70上的源极81与漏极82；
其中，所述第一多晶硅层30包括位于两侧的源极接触区31与漏极接触区32、及位于源极接触区31与漏极接触区32之间的沟道区33；所述源极接触区31与漏极接触区32均为N型重掺杂区或均为P型重掺杂区；
所述层间介电层70及栅极绝缘层50上设有分别对应于源极接触区31及漏极接触区32上方的第一通孔71、及第二通孔72，所述源极81、及漏极82分别通过第一通孔71、及第二通孔72与第一多晶硅层30的源极接触区31、及漏极接触区32相接触；
整个第二多晶硅层40为N型重掺杂区或P型重掺杂区，所述第二多晶硅层40与存储电容电极62形成存储电容；
所述第一多晶硅层30、及第二多晶硅层40均包括位于所述缓冲层20上的含氧低温多晶硅薄膜331及位于所述含氧低温多晶硅薄膜331上的不含氧低温多晶硅薄膜332。
具体的，所述TFT背板还包括：设于所述源极81、漏极82、及层间介电层70上的平坦层90、设于所述平坦层90上的像素电极100、设于所述像素电极100、及平坦层90上的像素定义层110、以及设于所述像素定义层110上且间隔设置的数个间隔物130；
所述平坦层90上设有对应于所述漏极82上方的第三通孔91，所述像素电极100通过第三通孔91与所述漏极82相接触；所述像素定义层110上设有对应于所述像素电极100上方的第四通孔111。
具体的，所述第四通孔111内用于形成OLED器件的有机发光层。
具体的，所述间隔物130的材料为有机材料。
具体的，所述平坦层90与像素定义层110为有机材料。
具体的，所述像素电极100的材料为氧化铟锡。
具体的，所述衬底基板10为玻璃基板。
具体的，所述缓冲层20包括氮化硅层、及氧化硅层中的一种或两种的组合。具体的，所述氮化硅层、及氧化硅层的厚度分别为
Figure PCTCN2016086725-appb-000006
具体的，所述含氧低温多晶硅薄膜331的厚度为所述第一多晶硅层30、及第二多晶硅层40的厚度的十分之一至二十分之一。优选为十分之一。
具体的，所述栅极绝缘层50包括氮化硅层、及氧化硅层中的一种或两种的组合。具体的，所述氮化硅层、及氧化硅层的厚度分别为
Figure PCTCN2016086725-appb-000007
具体的，所述栅极61、及存储电容电极62均包括两钼层及位于两钼层之间的一铝层、或仅包括单层钼层或单层铝层。具体的，所述栅极61的厚度为
Figure PCTCN2016086725-appb-000008
具体的，所述N型重掺杂区中掺入的离子为磷离子，所述P型重掺杂 区中掺入的离子为硼离子。
优选的，所述沟道区33为P型轻掺杂区，所述P型轻掺杂区中掺入的离子为硼离子。
具体的，所述N型重掺杂区中掺入的离子浓度为1×1015～1×1016ions/cm2，所述P型重掺杂区中掺入的离子浓度为1×1015～1×1016ions/cm2，所述P型轻掺杂区中掺入的离子浓度为1×1012～1×1013ions/cm2。
具体的，所述层间介电层70包括氮化硅层、及氧化硅层中的一种或两种的组合。具体的，所述层间介电层70的厚度为
Figure PCTCN2016086725-appb-000009
具体的，所述源极81与漏极82均包括两钼层及位于两钼层之间的一铝层、或仅包括单层钼层或单层铝层。具体的，所述源极81与漏极82的厚度分别为
Figure PCTCN2016086725-appb-000010
具体的，本发明的TFT背板中，所述栅极61、源极81、漏极82、及第一多晶硅层30构成一驱动TFT，用于驱动OLED器件的有机发光层发光。
上述TFT背板，制程简单，其中的第一多晶硅层30与第二多晶硅层40的结晶质量与均一性较好，提升了TFT的性能，增强其驱动效果。
综上所述，本发明提供一种TFT背板的制作方法及TFT背板。本发明的TFT背板的制作方法，通过在缓冲层上制作包括含氧非晶硅薄膜以及位于所述含氧非晶硅薄膜上的不含氧非晶硅薄膜的非晶硅薄膜，使得采用硼离子诱导固相晶化法对所述非晶硅薄膜进行晶化处理时，由于所述非晶硅薄膜与缓冲层的接触界面为含氧非晶硅薄膜，而含氧非晶硅薄膜在高温结晶过程中不容易产生晶核，从而使得晶核的产生仅发生在非晶硅薄膜上表面的硼离子掺杂层中，并且自上而下发生结晶，晶粒质量好，薄膜均一性好，从而达到提高结晶质量及改善均一性的效果。本发明的TFT背板，制程简单，其中的多晶硅层的结晶质量与均一性较好，提升了TFT的性能，增强其驱动效果。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (15)

  1. 一种TFT背板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上沉积缓冲层；
    步骤2、在所述缓冲层上形成非晶硅薄膜，所述非晶硅薄膜包括位于所述缓冲层上的含氧非晶硅薄膜以及位于所述含氧非晶硅薄膜上的不含氧非晶硅薄膜；
    步骤3、对所述非晶硅薄膜进行硼离子掺杂，在所述非晶硅薄膜的上表面形成一硼离子掺杂层，对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜包括位于所述缓冲层上的含氧低温多晶硅薄膜及位于所述含氧低温多晶硅薄膜上的不含氧低温多晶硅薄膜；
    步骤4、去除所述低温多晶硅薄膜上表面的硼离子掺杂层，对所述低温多晶硅薄膜进行图形化处理，得到间隔设置的第一多晶硅层与第二多晶硅层；
    步骤5、在所述第一多晶硅层、第二多晶硅层、及缓冲层上形成栅极绝缘层，采用一道掩模对所述第一多晶硅层的两侧、及整个第二多晶硅层进行N型或者P型重掺杂，在所述第一多晶硅层的两侧形成源极接触区与漏极接触区，所述源极接触区与漏极接触区之间的区域形成沟道区，所述第二多晶硅层经过N型或者P型重掺杂后形成导体；
    步骤6、在所述栅极绝缘层上形成对应于所述第一多晶硅层上方的栅极、及对应于所述第二多晶硅层上方的存储电容电极；所述存储电容电极与第二多晶硅层形成存储电容；
    在所述栅极、存储电容电极、及栅极绝缘层上沉积层间介电层，在所述层间介电层及栅极绝缘层上形成分别对应于源极接触区及漏极接触区上方的第一通孔、及第二通孔；
    步骤7、在所述层间介电层上形成源极与漏极，所述源极、及漏极分别通过第一通孔、及第二通孔与第一多晶硅层的源极接触区、及漏极接触区相接触。
  2. 如权利要求1所述的TFT背板的制作方法，其中，所述含氧非晶硅薄膜的厚度为所述非晶硅薄膜的厚度的十分之一至二十分之一。
  3. 如权利要求1所述的TFT背板的制作方法，其中，所述步骤2包括：
    步骤21、在所述缓冲层上方通入硅烷气体和氧气的混合气体，在所述 缓冲层上沉积得到含氧非晶硅薄膜；
    步骤22、在所述缓冲层上方通入硅烷气体，在所述缓冲层上沉积得到不含氧非晶硅薄膜。
  4. 如权利要求3所述的TFT背板的制作方法，其中，所述步骤21中，所述硅烷气体的流量一直保持不变，所述氧气的流量在步骤21开始时最大，之后逐渐减小，到步骤21结束时减少为零。
  5. 如权利要求3所述的TFT背板的制作方法，其中，所述步骤21中，所述氧气的流量小于或等于所述硅烷气体的流量的十分之一；所述步骤21与步骤22中，所述硅烷气体包括甲硅烷、及乙硅烷中的一种或多种。
  6. 如权利要求1所述的TFT背板的制作方法，还包括：在所述步骤5之后步骤6之前、在所述步骤6形成栅极与存储电容电极之后沉积层间介电层之前、或者在所述步骤6沉积层间介电层之后形成第一通孔与第二通孔之前，对整个基板进行快速热退火处理，使所述步骤5中在所述第一多晶硅层的源极接触区与漏极接触区、及整个第二多晶硅层中掺杂的N型或P型离子活化。
  7. 如权利要求1所述的TFT背板的制作方法，还包括步骤8、在所述源极、漏极、及层间介电层上形成平坦层，在所述平坦层上形成对应于所述漏极上方的第三通孔，在所述平坦层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触；
    在所述像素电极、及平坦层上形成像素定义层，在所述像素定义层上形成对应于所述像素电极上方的第四通孔；
    在所述像素定义层上形成间隔设置的数个间隔物。
  8. 一种TFT背板，包括：衬底基板、设于所述衬底基板上的缓冲层、设于所述缓冲层上且间隔设置的第一多晶硅层与第二多晶硅层、设于所述第一多晶硅层、第二多晶硅层、及缓冲层上的栅极绝缘层、设于所述栅极绝缘层上且对应于所述第一多晶硅层上方的栅极、设于所述栅极绝缘层上且对应于所述第二多晶硅层上方的存储电容电极、设于所述栅极、存储电容电极、及栅极绝缘层上的层间介电层、设于所述层间介电层上的源极与漏极；
    其中，所述第一多晶硅层包括位于两侧的源极接触区与漏极接触区、及位于源极接触区与漏极接触区之间的沟道区；所述源极接触区与漏极接触区均为N型重掺杂区或均为P型重掺杂区；
    所述层间介电层及栅极绝缘层上设有分别对应于源极接触区及漏极接触区上方的第一通孔、及第二通孔，所述源极、及漏极分别通过第一通孔、 及第二通孔与第一多晶硅层的源极接触区、及漏极接触区相接触；
    整个第二多晶硅层为N型重掺杂区或P型重掺杂区，所述第二多晶硅层与存储电容电极形成存储电容；
    所述第一多晶硅层、及第二多晶硅层均包括位于所述缓冲层上的含氧低温多晶硅薄膜及位于所述含氧低温多晶硅薄膜上的不含氧低温多晶硅薄膜。
  9. 如权利要求8所述的TFT背板，其中，所述含氧低温多晶硅薄膜的厚度为所述第一多晶硅层、及第二多晶硅层的厚度的十分之一至二十分之一。
  10. 如权利要求8所述的TFT背板，其中，所述TFT背板还包括：设于所述源极、漏极、及层间介电层上的平坦层、设于所述平坦层上的像素电极、设于所述像素电极、及平坦层上的像素定义层、以及设于所述像素定义层上且间隔设置的数个间隔物；
    所述平坦层上设有对应于所述漏极上方的第三通孔，所述像素电极通过第三通孔与所述漏极相接触；所述像素定义层上设有对应于所述像素电极上方的第四通孔。
  11. 一种TFT背板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上沉积缓冲层；
    步骤2、在所述缓冲层上形成非晶硅薄膜，所述非晶硅薄膜包括位于所述缓冲层上的含氧非晶硅薄膜以及位于所述含氧非晶硅薄膜上的不含氧非晶硅薄膜；
    步骤3、对所述非晶硅薄膜进行硼离子掺杂，在所述非晶硅薄膜的上表面形成一硼离子掺杂层，对所述非晶硅薄膜进行快速热退火处理，使所述非晶硅薄膜结晶转化为低温多晶硅薄膜，所述低温多晶硅薄膜包括位于所述缓冲层上的含氧低温多晶硅薄膜及位于所述含氧低温多晶硅薄膜上的不含氧低温多晶硅薄膜；
    步骤4、去除所述低温多晶硅薄膜上表面的硼离子掺杂层，对所述低温多晶硅薄膜进行图形化处理，得到间隔设置的第一多晶硅层与第二多晶硅层；
    步骤5、在所述第一多晶硅层、第二多晶硅层、及缓冲层上形成栅极绝缘层，采用一道掩模对所述第一多晶硅层的两侧、及整个第二多晶硅层进行N型或者P型重掺杂，在所述第一多晶硅层的两侧形成源极接触区与漏极接触区，所述源极接触区与漏极接触区之间的区域形成沟道区，所述第二多晶硅层经过N型或者P型重掺杂后形成导体；
    步骤6、在所述栅极绝缘层上形成对应于所述第一多晶硅层上方的栅极、及对应于所述第二多晶硅层上方的存储电容电极；所述存储电容电极与第二多晶硅层形成存储电容；
    在所述栅极、存储电容电极、及栅极绝缘层上沉积层间介电层，在所述层间介电层及栅极绝缘层上形成分别对应于源极接触区及漏极接触区上方的第一通孔、及第二通孔；
    步骤7、在所述层间介电层上形成源极与漏极，所述源极、及漏极分别通过第一通孔、及第二通孔与第一多晶硅层的源极接触区、及漏极接触区相接触；
    还包括：在所述步骤5之后步骤6之前、在所述步骤6形成栅极与存储电容电极之后沉积层间介电层之前、或者在所述步骤6沉积层间介电层之后形成第一通孔与第二通孔之前，对整个基板进行快速热退火处理，使所述步骤5中在所述第一多晶硅层的源极接触区与漏极接触区、及整个第二多晶硅层中掺杂的N型或P型离子活化；
    还包括步骤8、在所述源极、漏极、及层间介电层上形成平坦层，在所述平坦层上形成对应于所述漏极上方的第三通孔，在所述平坦层上形成像素电极，所述像素电极通过第三通孔与所述漏极相接触；
    在所述像素电极、及平坦层上形成像素定义层，在所述像素定义层上形成对应于所述像素电极上方的第四通孔；
    在所述像素定义层上形成间隔设置的数个间隔物。
  12. 如权利要求11所述的TFT背板的制作方法，其中，所述含氧非晶硅薄膜的厚度为所述非晶硅薄膜的厚度的十分之一至二十分之一。
  13. 如权利要求11所述的TFT背板的制作方法，其中，所述步骤2包括：
    步骤21、在所述缓冲层上方通入硅烷气体和氧气的混合气体，在所述缓冲层上沉积得到含氧非晶硅薄膜；
    步骤22、在所述缓冲层上方通入硅烷气体，在所述缓冲层上沉积得到不含氧非晶硅薄膜。
  14. 如权利要求13所述的TFT背板的制作方法，其中，所述步骤21中，所述硅烷气体的流量一直保持不变，所述氧气的流量在步骤21开始时最大，之后逐渐减小，到步骤21结束时减少为零。
  15. 如权利要求13所述的TFT背板的制作方法，其中，所述步骤21中，所述氧气的流量小于或等于所述硅烷气体的流量的十分之一；所述步骤21与步骤22中，所述硅烷气体包括甲硅烷、及乙硅烷中的一种或多种。
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