WO2016165223A1 - 一种多晶硅薄膜晶体管及其制作方法和显示装置 - Google Patents

一种多晶硅薄膜晶体管及其制作方法和显示装置 Download PDF

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WO2016165223A1
WO2016165223A1 PCT/CN2015/084319 CN2015084319W WO2016165223A1 WO 2016165223 A1 WO2016165223 A1 WO 2016165223A1 CN 2015084319 W CN2015084319 W CN 2015084319W WO 2016165223 A1 WO2016165223 A1 WO 2016165223A1
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layer
active layer
film transistor
amorphous silicon
thin film
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PCT/CN2015/084319
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English (en)
French (fr)
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刘政
龙春平
詹裕程
陆小勇
李小龙
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京东方科技集团股份有限公司
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Priority to US15/104,504 priority Critical patent/US9837542B2/en
Publication of WO2016165223A1 publication Critical patent/WO2016165223A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a polysilicon thin film transistor, a manufacturing method thereof, and a display device.
  • the low temperature polysilicon array substrate Compared with the amorphous silicon array substrate, the low temperature polysilicon array substrate has the advantages of high mobility (up to several hundred times that of amorphous silicon), and the thin film transistor can be made small in size and fast in response, which is in recent years.
  • An array substrate of a display panel which is increasingly optimistic is increasingly used in high resolution, high quality organic electroluminescence displays and liquid crystal display panels.
  • a plurality of thin film transistors of a small size are often required, so the process realization, electrical performance and reliability of the thin film transistor array substrate are required. Sexual requirements are higher.
  • polysilicon thin film transistor structure as shown in FIG.
  • 1, 1 is a substrate
  • 2 is an active layer
  • 3 is a gate insulating layer
  • 4 is a gate
  • 5 is an intermediate insulating layer
  • 6 is a via.
  • the backlight will illuminate the active layer channel region for a long time, resulting in deterioration of device characteristics and low product reliability.
  • the active layer grain size and the uniformity of the crystal grains in the channel region prepared by the excimer laser crystallization method are difficult to control.
  • the intermediate insulating layer and the gate insulating layer need to be etched to form via holes.
  • the thickness of the intermediate insulating layer is large, and is several thousand angstroms or more. Therefore, the requirements for via etching are relatively high, and a special ICP, ECCP, etc. etching device is required to be compatible, and it is easy to cause damage to the active layer or to form a poor contact between the source and drain metal and the source and drain regions.
  • the invention provides a polysilicon thin film transistor, a manufacturing method thereof and a display device, which increase the grain size of the active layer, improve the grain uniformity of the channel region, and effectively prevent the active layer from being deteriorated by the backlight.
  • the invention provides a polysilicon thin film transistor, comprising:
  • a polysilicon active layer formed on the substrate and the isolation layer on both sides of the active layer Forming two source-drain ion implantation regions,
  • the two end edges of the isolation layer are in both end edges of the active layer.
  • the expression "the both end edges of the isolation layer are in the both end edges of the active layer” means that the projection of the both end edges of the isolation layer on the substrate falls into Both end edges of the active layer are within a range of projections on the substrate and smaller than a projection on the substrate, and mean that the size of the isolation layer is smaller than the size of the active layer.
  • the polysilicon thin film transistor further includes:
  • the spacer layer is a single layer of silicon oxide, silicon nitride or a laminate of the two.
  • the thickness of the amorphous silicon layer is
  • the thickness of the isolation layer is
  • the amorphous silicon layer and the projection of the active layer on the substrate coincide;
  • the isolation layer coincides with a projection of the gate on the substrate.
  • the present invention also provides a method of fabricating a polysilicon thin film transistor, comprising:
  • the two end edges of the isolation layer are in both end edges of the active layer.
  • the method further includes:
  • the amorphous silicon layer is ion-implanted while ion-implanting the active layer, and a doped amorphous silicon layer is formed on both sides of the amorphous silicon layer.
  • the ion implantation of the active layer and the amorphous silicon layer further comprises: sequentially forming a gate insulating layer on the active layer and The pattern of the gate;
  • the spacer layer is a single layer of silicon oxide, silicon nitride or a laminate of the two.
  • the pattern of the isolation layer and the pattern of the gate are respectively formed by photolithography using the same mask.
  • the ion implantation energy is 10 to 200 keV;
  • the ion implantation dose is 1 ⁇ 10 11 to 1 ⁇ 10 20 atoms/cm 3 .
  • the present invention provides a display device comprising the polysilicon thin film transistor according to any one of the above.
  • the active layer can be increased by providing an isolation layer at both end edges of the active layer under the active layer of the polysilicon.
  • the grain size increases the uniformity of the crystal grains in the channel region, improves the electrical performance of the device, and effectively blocks the illumination of the active layer of the polysilicon by the backlight, thereby effectively preventing the deterioration of the active layer of the polysilicon by backlight illumination.
  • the polysilicon thin film transistor and the manufacturing method thereof and the display device provided by the invention can further block the illumination of the active layer of the polysilicon by the backlight, and effectively prevent the active layer of the polysilicon from being illuminated by the backlight.
  • the characteristic deterioration is caused, and the reliability of the device is improved.
  • the amorphous silicon layer can also It functions as an active layer, so it does not have an excessive influence on device performance, and thus it is possible to reduce the production cost without using a dedicated expensive etching device for preventing over-etching.
  • FIG. 1 is a schematic structural view of a polysilicon thin film transistor in the prior art
  • FIG. 2 is a schematic structural view of a polysilicon thin film transistor in Embodiment 1 of the present invention.
  • FIG. 3 is a schematic structural view of a polysilicon thin film transistor in Embodiment 2 of the present invention.
  • FIG. 4 is a flow chart showing a method of fabricating a polysilicon thin film transistor in Embodiment 3 of the present invention.
  • FIG. 5 is a flow chart of a method for fabricating a polysilicon thin film transistor according to Embodiment 4 of the present invention.
  • FIG. 6 is a schematic view showing the formation of an amorphous silicon layer in Embodiment 4 of the present invention.
  • Figure 7 is a schematic view showing the formation of an isolation layer in Embodiment 4 of the present invention.
  • Figure 8 is a schematic view showing the formation of an active layer in Embodiment 4 of the present invention.
  • FIG. 9 is a schematic view showing the formation of a gate insulating layer and a gate electrode in Embodiment 4 of the present invention.
  • Figure 10 is a schematic view showing ion implantation in Embodiment 4 of the present invention.
  • Embodiment 1 of the present invention first provides a polysilicon thin film transistor, as shown in FIG. 2, comprising:
  • a polysilicon active layer 2 formed on the substrate 1 and the isolation layer 8 is formed with two source/drain ion implantation regions 9 on both sides of the active layer 2, wherein both ends of the isolation layer 8 The edges are in the both end edges of the active layer 2.
  • the polysilicon thin film transistor may further include: a gate insulating layer 3, a gate electrode 4, and an intermediate insulating layer 5 which are sequentially formed on the active layer 2, and are formed on both sides of the intermediate insulating layer 5 and the gate insulating layer 3. Two vias 6.
  • the thickness of the active layer 2 may be Preferred thickness is
  • the formation method may be PECVD, LPCVD or sputtering, and the deposition temperature is below 600 °C.
  • the gate insulating layer 3 may be a single layer of silicon oxide, silicon nitride or a laminate of the two, and may be deposited by PECVD, LPCVD, APCVD or ECR-CVD.
  • the gate 4 may be a single layer, two layers or more layers, and is composed of a metal, a metal alloy such as molybdenum, aluminum, molybdenum tungsten, etc., and has a thickness of Within the range, the preferred thickness is
  • the intermediate insulating layer 5 may be a single layer of silicon oxide, silicon nitride or a laminate of the two. It can be deposited by PECVD, LPCVD, APCVD or ECR-CVD, and the thickness is The appropriate thickness can be selected according to the specific design needs.
  • the isolation layer 8 may be a single layer of silicon oxide, silicon nitride or a laminate of the two.
  • the isolation layer since both end edges of the isolation layer are in the both end edges of the active layer, there is a step structure, which enables the amorphous silicon at both ends of the isolation layer to be active.
  • the laser energy absorbed at the layer is low and can only be partially melted, thereby forming a polysilicon nucleus center to promote the polycrystalline silicon to grow along the channel and easily form larger crystal grains, and improve the grain uniformity of the channel region. Therefore, the electrical performance of the device can be improved.
  • the isolation layer also effectively blocks the illumination of the polysilicon active layer by the backlight, it is effective to prevent the polysilicon active layer from being deteriorated by the backlight.
  • Embodiment 2 of the present invention provides a polysilicon thin film transistor.
  • an amorphous silicon layer formed between the substrate 1 and the isolation layer 8 is further included. 7.
  • the amorphous silicon layer 7 corresponds to the position of the active layer 2, and two source-drain ion implantation regions are also formed on both sides of the amorphous silicon layer 7. Due to the high requirements for via etching in the prior art, the etching apparatus is generally susceptible to damage to the active layer or poor contact between the source and drain metal and the source and drain regions. Therefore, special etching is required. device.
  • the doped amorphous silicon layer 7 when the via hole 6 is formed on the intermediate insulating layer 5 due to the presence of the doped amorphous silicon layer 7, even if the polysilicon active layer 2 is over-etched, the doped amorphous silicon layer 7 is also It can act as an active layer, so it will still form good contact without affecting device performance, so there is no need for special etching equipment when etching vias, and amorphous silicon 7 can further block backlight illumination. The layer thus further avoids the backlight illumination causing deterioration of the characteristics of the polysilicon thin film transistor and improving the reliability of the device.
  • the thickness of the amorphous silicon layer 7 may be The forming method may be PECVD, LPCVD or sputtering, the deposition temperature is below 600 ° C; and/or the thickness of the isolation layer 8 may be It can be deposited by methods such as PECVD, LPCVD, APCVD or ECR-CVD.
  • the projections of the amorphous silicon layer 7 and the active layer 2 on the substrate 1 may coincide; and/or the projections of the isolation layer 8 and the gate 4 on the substrate may coincide, thereby ensuring that the same block is utilized.
  • the mask is patterned by photolithography to form a pattern of the amorphous silicon layer and the active layer; and/or, by using the same mask, photolithography is used to form the pattern of the isolation layer and the gate. There is no need to increase the number of masks, which greatly simplifies the fabrication process of the device and reduces the manufacturing cost.
  • the substrate 1 may be a transparent substrate such as pre-cleaned glass, which affects the operating characteristics of the TFT in order to prevent diffusion of metal ion impurities in the transparent substrate into the active layer, on the substrate 1 and amorphous silicon.
  • a buffer layer (not shown in FIG. 3) formed of silicon oxide, silicon nitride, or a combination of both may be included between the layers 7.
  • Embodiment 3 of the present invention provides a method for fabricating a polysilicon thin film transistor. Referring to FIG. 4, the method includes:
  • Step 401 forming a pattern of the isolation layer on the substrate
  • Step 402 depositing an amorphous silicon layer on the substrate and the isolation layer, converting it into a polysilicon layer, and forming a pattern of the polysilicon active layer;
  • Step 403 performing ion implantation on the active layer, and forming two source/drain ion implantation regions on both sides of the active layer, wherein both end edges of the isolation layer are at both ends of the active layer Inside the edge.
  • the amorphous silicon at both ends of the isolation layer can be made.
  • the laser energy absorbed at the active layer is low and can only be partially melted, thereby forming a polysilicon nucleus center to promote the polycrystalline silicon to grow along the channel and easily form larger crystal grains, and the crystal grains in the channel region are uniform.
  • the performance is improved, thereby improving the electrical performance of the device.
  • the isolation layer also effectively blocks the illumination of the polysilicon active layer by the backlight, it is effective to prevent the polysilicon active layer from being deteriorated by the backlight.
  • the method may further include: forming a pattern of the amorphous silicon layer on the substrate corresponding to the active layer; performing the ion implantation on the active layer to perform the amorphous silicon layer Ion implantation forms a doped amorphous silicon layer on both sides of the amorphous silicon layer, so that carriers on both sides of the amorphous silicon layer increase, and can function as a partial active layer, thereby improving device performance.
  • the etching device is generally easy to be used for the active layer. Over-cutting causes damage or poorly formed source-drain metal contact with source and drain regions, so special etching equipment is required.
  • the doped amorphous silicon layer can also have The role of the source layer, therefore, still forms a good contact, does not affect the performance of the device, so that no special etching equipment is needed to etch the via holes, and further avoidance because the amorphous silicon layer can further block the backlight from illuminating the active layer, thereby further avoiding The backlight illumination causes deterioration of the characteristics of the polysilicon thin film transistor and improves the reliability of the device.
  • the pattern of the gate insulating layer and the gate electrode may be sequentially formed on the active layer.
  • the method further includes: depositing an intermediate insulating layer on the gate insulating layer and the gate, and forming two via holes on both sides of the intermediate insulating layer and the gate insulating layer .
  • the isolation layer may be a single layer of silicon oxide, silicon nitride or a combination of the two.
  • the thickness of the amorphous silicon layer may be And/or, the thickness of the isolation layer can be
  • the method of the embodiment of the present invention may further comprise: forming a pattern of the amorphous silicon layer by photolithography using the same mask. a pattern of the active layer; and/or, using the same mask to form a pattern of the isolation layer and a pattern of the gate by photolithography, so that the formed amorphous silicon layer and the active layer are on the substrate The projections coincide; and/or the isolation layer coincides with the projection of the gate on the substrate.
  • the ion implantation process may employ ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid state diffusion implantation.
  • a mainstream ion cloud implantation method may be adopted, and a boron-containing gas such as B 2 H 6 /H 2 or a phosphorus-containing compound such as PH 3 /H 2 may be used according to design requirements, and the ion implantation energy may be 10 to 200 keV, preferably 40 to 100 keV.
  • the implantation dose may be in the range of 1 x 10 11 to 1 x 10 20 atoms/cm 3 , and the recommended dose is 1 x 10 14 to 1 x 10 18 atoms/cm 3 .
  • heat treatment dehydrogenation, deposition inducing metal, heat treatment crystallization, excimer laser irradiation crystallization, activation of doping impurities, etc. may be added as needed.
  • the method further includes: forming a buffer layer on the substrate to prevent metal ion impurities in the substrate from diffusing into the active layer to affect TFT working characteristics.
  • Embodiments of the present invention provide a method for fabricating a polysilicon thin film transistor. Referring to FIG. 5, the method includes:
  • Step 501 Form a buffer layer on the substrate.
  • the substrate 1 is a pre-cleaned glass transparent substrate.
  • a silicon oxide may be first formed on the substrate 1.
  • a buffer layer formed of silicon nitride or a combination of both.
  • Step 502 forming a pattern of an amorphous silicon layer on a region of the substrate corresponding to the active layer.
  • a pattern of the amorphous silicon layer 7 is formed on a buffer layer of the substrate 1 corresponding to an active layer of the polysilicon thin film transistor.
  • the thickness of the amorphous silicon layer 7 is The formation method may be PECVD, LPCVD or sputtering, and the deposition temperature is below 600 °C.
  • this step forms an amorphous silicon layer 7 using a mask of an active layer of a polysilicon thin film transistor.
  • Step 503 forming a pattern of an insulating isolation layer on a region corresponding to the gate on the amorphous silicon layer, and both end edges of the isolation layer are in both end edges of the amorphous silicon layer.
  • a pattern of the insulating isolation layer 8 is formed on the amorphous silicon layer 7 corresponding to the gate of the polysilicon thin film transistor, wherein both end edges of the isolation layer 8 are in the amorphous silicon layer 7.
  • the two ends of the isolation layer 8 and the amorphous silicon layer 7 are stepped to prepare the amorphous silicon to be converted into the nucleation center of the polysilicon in the subsequent step.
  • the spacer layer 8 can be a single layer of silicon oxide, silicon nitride, or a laminate of the two. It can be deposited by PECVD, LPCVD, APCVD or ECR-CVD, and the thickness is The appropriate thickness can be selected according to the specific design needs.
  • this step uses the mask of the gate of the polysilicon thin film transistor to form the isolation layer 8.
  • Step 504 depositing an amorphous silicon active layer on the amorphous silicon layer and the isolation layer, converting it into a polysilicon active layer, and forming a pattern of the active layer.
  • an amorphous silicon active layer is deposited on the amorphous silicon layer 7 and the isolation layer 8, and is crystallized, converted into a polysilicon active layer, and an active layer is formed by photolithography. Graphics. After depositing the amorphous silicon active layer, it may be converted into the polysilicon active layer 2 by laser scanning or the like.
  • the laser energy absorbed by the position indicated by the broken line is low, and only partially melted here, thereby forming a polysilicon nucleation center. It promotes the growth of polysilicon along the channel orientation (in the direction indicated by the dotted arrow in the figure) and easily forms larger grains, so that the electrical properties of the device can be improved.
  • the thickness of the active layer 2 is Preferred thickness is
  • the formation method may be PECVD, LPCVD or sputtering, and the deposition temperature is below 600 °C.
  • Step 505 sequentially forming a pattern of a gate insulating layer and a gate on the active layer.
  • a gate insulating layer 3 and a gate electrode 4 are sequentially formed on the active layer 2.
  • the gate insulating layer 3 may be a single layer of silicon oxide, silicon nitride or a laminate of the two, and may be deposited by PECVD, LPCVD, APCVD or ECR-CVD.
  • the thickness can be selected according to the specific design needs, and the thickness is preferably
  • the gate 4 may be a single layer, two layers or more layers, and is composed of a metal, a metal alloy such as molybdenum, aluminum, molybdenum tungsten, etc., and has a thickness of Within the range, the preferred thickness is
  • Step 506 performing ion implantation on the active layer and the amorphous silicon layer, forming two source-drain ion implantation regions on both sides of the active layer, and forming a doped amorphous silicon layer on both sides of the amorphous silicon layer.
  • the active layer 2 and the amorphous silicon layer 7 are both ion-implanted with the gate electrode 4 as a mask.
  • the ion implantation process adopts the mainstream ion cloud injection method, and is implanted with a mixed gas containing boron such as B 2 H 6 /H 2 or phosphorus such as PH 3 /H 2 , and the ion implantation energy can be 10 to 200 keV, and the implantation dose is 1x10 14 to 1x10 18 atoms/cm 3 .
  • Step 507 depositing an intermediate insulating layer on the gate insulating layer and the gate, and forming two via holes connecting the two source-drain ion implantation regions of the active layer on both sides of the intermediate insulating layer and the gate insulating layer.
  • the intermediate insulating layer 5 is deposited and a via hole 6 is formed. Due to the presence of the doped amorphous silicon layer 7, the active layer 2 can be effectively prevented from being over-etched and a good contact is formed.
  • the intermediate insulating layer 5 may be a single layer of silicon oxide, silicon nitride or a laminate of the two. It can be deposited by PECVD, LPCVD, APCVD or ECR-CVD, and the thickness is The appropriate thickness can be selected according to the specific design needs.
  • Embodiment 5 of the present invention further provides a display device comprising the polysilicon thin film transistor according to any one of the above.
  • display devices generally include a display substrate, and polysilicon thin film transistors are typically formed on a display substrate such as an array substrate.
  • the display device may be any device or device having a display function such as a display panel, a display, a television, a mobile phone, a navigator, an e-book, a tablet, or the like.

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Abstract

一种多晶硅薄膜晶体管及制作方法和显示装置，多晶硅薄膜晶体管包括：衬底（1）；形成于衬底（1）上的隔离层（8）；形成于衬底（1）和隔离层（8）上的多晶硅有源层（2），在有源层（2）的两侧形成有两个源漏离子注入区，其中，隔离层（8）的两端边缘在有源层（2）的两端边缘内。提供的多晶硅薄膜晶体管及其制作方法中，能够增大有源层的晶粒尺寸，提高其沟道区的晶粒均匀性，有效避免有源层受背光照射特性恶化，提高了器件的可靠性。

Description

一种多晶硅薄膜晶体管及其制作方法和显示装置 技术领域
本发明涉及显示技术领域，尤其涉及一种多晶硅薄膜晶体管及其制作方法和显示装置。
背景技术
相对于非晶硅阵列衬底，低温多晶硅阵列衬底拥有高迁移率(可达非晶硅的数百倍)的优点，其薄膜晶体管尺寸可以做得很小，并且反应速度快，是近年来越来越被看好的一种显示面板的阵列衬底，在高分辨率、高画质的有机电致发光显示和液晶显示面板上被越来越多的采用。但由于其构成一般较为复杂，工艺过程繁多，特别是在针对高分辨率的显示面板中，往往需要多个很小尺寸的薄膜晶体管，因此对薄膜晶体管阵列衬底的工艺实现、电学性能、可靠性的要求更高。在如图1所示的现有技术的多晶硅薄膜晶体管结构中，1为衬底，2为有源层，3为栅极绝缘层，4为栅极，5为中间绝缘层，6为过孔。其中，若低温多晶硅阵列衬底用于LCD显示面板产品中，背光源会长时间照射有源层沟道区导致器件特性恶化，产品可靠性低。另外，准分子激光晶化的方法制备的有源层晶粒尺寸和晶粒在沟道区的均匀性控制困难。而且，从图1中可以看出，现有结构中需要刻蚀中间绝缘层、栅极绝缘层才能形成过孔，一般来说，中间绝缘层的厚度是很大的，在几千埃以上，因此对过孔刻蚀的要求比较高，需要专用的ICP、ECCP等刻蚀设备才可以对应，且容易对有源层过刻造成破坏或形成不良的源漏金属与源漏区的接触。
发明内容
本发明提供一种多晶硅薄膜晶体管及其制作方法和显示装置，以增大有源层的晶粒尺寸，提高其沟道区的晶粒均匀性，有效避免有源层受背光照射导致特性恶化。
本发明提供一种多晶硅薄膜晶体管，包括：
衬底；
形成于所述衬底上的隔离层；
形成于所述衬底和所述隔离层上的多晶硅有源层，在所述有源层的两侧 形成有两个源漏离子注入区，
其中，所述隔离层的两端边缘在所述有源层的两端边缘内。
根据本申请的公开内容，表述“所述隔离层的两端边缘在所述有源层的两端边缘内”是指所述隔离层的两端边缘在所述衬底上的投影落入到所述有源层的两端边缘在所述衬底上的投影的范围之内且小于所述衬底上的投影，并且意味着所述隔离层的尺寸小于所述有源层的尺寸。
进一步地，还包括：
形成于所述衬底和所述隔离层之间的非晶硅层，所述非晶硅层与所述有源层的位置相对应，所述非晶硅层的两侧形成有两个源漏离子注入区。
进一步地，所述多晶硅薄膜晶体管还包括：
依次形成于所述有源层上的栅极绝缘层、栅极和中间绝缘层，以及形成在所述中间绝缘层和所述栅极绝缘层的两侧的两个过孔。
进一步地，
所述隔离层为单层的氧化硅、氮化硅或二者的叠层。
进一步地，
所述非晶硅层的厚度为
Figure PCTCN2015084319-appb-000001
和/或，所述隔离层的厚度为
Figure PCTCN2015084319-appb-000002
进一步地，
所述非晶硅层与所述有源层在所述衬底上的投影重合；
和/或，所述隔离层与所述栅极在所述衬底上的投影重合。
另一方面，本发明还提供一种制作多晶硅薄膜晶体管的方法，包括：
在衬底上形成隔离层的图形；
在所述衬底和所述隔离层上沉积非晶硅层，使之转变为多晶硅层，并形成多晶硅有源层的图形；
对所述有源层进行离子注入，在所述有源层的两侧形成两个源漏离子注入区，
其中，所述隔离层的两端边缘在所述有源层的两端边缘内。
进一步地，所述方法还包括：
在所述衬底上与所述有源层对应的区域形成非晶硅层的图形；
在对所述有源层进行离子注入的同时对所述非晶硅层进行离子注入，在所述非晶硅层的两侧形成掺杂的非晶硅层。
进一步地，在所述形成有源层的图形之后，所述对所述有源层和所述非晶硅层进行离子注入之前还包括：在所述有源层上依次形成栅极绝缘层和栅极的图形；
在所述对所述有源层和所述非晶硅层进行离子注入之后还包括：在所述栅极绝缘层和所述栅极上沉积中间绝缘层，并在所述中间绝缘层和所述栅极绝缘层的两侧形成两个过孔。
进一步地，
所述隔离层为单层的氧化硅、氮化硅或二者的叠层。
进一步地，
利用同一块掩膜板采用光刻刻蚀分别形成所述非晶硅层的图形与所述有源层的图形；
和/或，利用同一块掩膜板采用光刻刻蚀分别形成所述隔离层的图形与所述栅极的图形。
进一步地，
所述离子注入能量为10～200keV；
和/或，所述离子注入剂量为1x1011～1x1020atoms/cm3。
再一方面，本发明还提供一种显示装置，包括如上任一项所述的多晶硅薄膜晶体管。
可见，在本发明提供的多晶硅薄膜晶体管及其制作方法和显示装置中，通过在多晶硅有源层下设置两端边缘在有源层的两端边缘内的隔离层，能够增大有源层的晶粒尺寸，提高晶粒在沟道区的均匀性，提高器件的电学性能，同时也有效阻挡了背光对多晶硅有源层的照射，有效避免多晶硅有源层受背光照射导致特性恶化。
另外，通过进一步在隔离层下设置非晶硅层，本发明提供的多晶硅薄膜晶体管及其制作方法和显示装置能够进一步阻挡背光对多晶硅有源层的照射，更有效避免多晶硅有源层受背光照射导致特性恶化，提高了器件的可靠性；同时，由于存在非晶硅层，在刻蚀源漏过孔时，即使有一定的过刻蚀损害多晶硅有源层，由于非晶硅层同样也能起到有源层的作用，因此不会对器件性能造成过大影响，并因此可以不需要采用专用的防止过刻蚀的昂贵的刻蚀设备，降低了生产成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是现有技术中多晶硅薄膜晶体管结构示意图；
图2是本发明实施例1中多晶硅薄膜晶体管结构示意图；
图3是本发明实施例2中多晶硅薄膜晶体管结构示意图；
图4是本发明实施例3中制作多晶硅薄膜晶体管的方法流程图；
图5是本发明实施例4制作多晶硅薄膜晶体管的方法流程图；
图6是本发明实施例4中非晶硅层的形成示意图；
图7是本发明实施例4中隔离层的形成示意图；
图8是本发明实施例4中有源层的形成示意图；
图9是本发明实施例4中栅极绝缘层和栅极形成示意图；
图10是本发明实施例4中离子注入示意图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚，下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
实施例1：
本发明实施例1首先提供一种多晶硅薄膜晶体管，如图2所示，包括：
衬底1；
形成于衬底1上的隔离层8；
形成于所述衬底1和所述隔离层8上的多晶硅有源层2，在所述有源层2的两侧形成有两个源漏离子注入区9，其中，隔离层8的两端边缘在有源层2的两端边缘内。
其中，多晶硅薄膜晶体管还可以包括：依次形成于有源层2上的栅极绝缘层3、栅极4和中间绝缘层5，以及形成在中间绝缘层5和栅极绝缘层3的两侧的两个过孔6。
另外，在本发明实施例中，有源层2的厚度可以为
Figure PCTCN2015084319-appb-000003
优 选厚度为
Figure PCTCN2015084319-appb-000004
其形成方法可以为PECVD、LPCVD或者溅射方法，沉积温度在600℃以下。栅极绝缘层3可采用单层的氧化硅、氮化硅或者二者的叠层，可使用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为
Figure PCTCN2015084319-appb-000005
可根据具体的设计需要选择合适的厚度，其优选厚度为
Figure PCTCN2015084319-appb-000006
栅极4可为单层、两层或两层以上结构，由金属、金属合金如钼、铝、钼钨等构成，厚度在
Figure PCTCN2015084319-appb-000007
范围内，优选厚度为
Figure PCTCN2015084319-appb-000008
中间绝缘层5可采用单层的氧化硅、氮化硅或者二者的叠层。可采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为
Figure PCTCN2015084319-appb-000009
可根据具体的设计需要选择合适的厚度。
其中，隔离层8可以为单层的氧化硅、氮化硅或二者的叠层。
本实施例中在非晶硅有源层的晶化的过程中，由于隔离层两端边缘在有源层的两端边缘内，因此存在台阶结构，能够使得隔离层两端的非晶硅有源层处吸收的激光能量较低，仅能部分熔融，因而在此形成多晶硅形核中心，以促进多晶硅沿沟道定向生长并易形成较大晶粒，并使沟道区的晶粒均匀性提高，从而可以提高器件电学性能。同时在显示使用时，由于隔离层也有效阻挡了背光对多晶硅有源层的照射，因此有效避免多晶硅有源层受背光照射导致特性恶化。
实施例2：
本发明实施例2提供一种多晶硅薄膜晶体管，参见图3，其在本发明实施例1的结构基础上还包括：形成于所述衬底1和所述隔离层8之间的非晶硅层7，所述非晶硅层7与所述有源层2的位置相对应，所述非晶硅层7的两侧同样形成有两个源漏离子注入区。由于现有的工艺中对过孔刻蚀的要求比较高，一般刻蚀设备易对有源层过刻造成破坏或形成不良的源漏金属与源漏区的接触，因此需要使用专用的刻蚀设备。而本发明实施例中由于掺杂非晶硅层7的存在，在中间绝缘层5上形成过孔6时，即使多晶硅有源层2被过度刻蚀，但是由于掺杂非晶硅层7也能起到有源层的作用，因此仍然会形成良好的接触，不会影响器件性能，从而刻蚀过孔时无需专用的刻蚀设备，又由于非晶层硅7能进一步阻挡背光照射有源层，因此进一步避免了背光照射导致多晶硅薄膜晶体管特性恶化，提高了器件的可靠性。
可选地，非晶硅层7的厚度可以为
Figure PCTCN2015084319-appb-000010
其形成方法可以为PECVD、LPCVD或者溅射方法，沉积温度在600℃以下；和/或，隔离层8 的厚度可以为
Figure PCTCN2015084319-appb-000011
可采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积。
可选地，非晶硅层7与有源层2在衬底1上的投影可以重合；和/或，隔离层8与栅极4在衬底上的投影可以重合，从而能够保证利用同一块掩膜板采用光刻刻蚀分别形成非晶硅层的图形与有源层的图形；和/或，利用同一块掩膜板采用光刻刻蚀分别形成隔离层的图形与栅极的图形，无需增加掩膜板的个数，大大简化了器件的制作工艺，降低了制作成本。
在图3中，衬底1可以为预先清洗的玻璃等透明衬底，为了防止透明衬底中的金属离子杂质扩散至有源层中而影响TFT工作特性，在衬底1上和非晶硅层7之间可以包含采用氧化硅、氮化硅或者二者叠层形成的缓冲层(图3中未示出)。
实施例3：
本发明实施例3提供一种制作多晶硅薄膜晶体管的方法，参见图4，包括：
步骤401：在衬底上形成隔离层的图形；
步骤402：在所述衬底和所述隔离层上沉积非晶硅层，使之转变为多晶硅层，并形成多晶硅有源层的图形；
步骤403：对所述有源层进行离子注入，在所述有源层的两侧形成两个源漏离子注入区，其中，所述隔离层的两端边缘在所述有源层的两端边缘内。
本实施例在非晶硅有源层的晶化的过程中，由于预先形成的隔离层两端边缘在有源层的两端边缘内，因此存在台阶结构，能够使得隔离层两端的非晶硅有源层处吸收的激光能量较低，仅能部分熔融，因而在此形成多晶硅形核中心，以促进多晶硅沿沟道定向生长并易形成较大晶粒，并使沟道区的晶粒均匀性提高，从而可以提高器件电学性能。同时在显示使用时，由于隔离层也有效阻挡了背光对多晶硅有源层的照射，因此有效避免多晶硅有源层受背光照射导致特性恶化。
其中，方法还可以包括：在所述衬底上与所述有源层对应的区域形成非晶硅层的图形；在对所述有源层进行离子注入的同时对所述非晶硅层进行离子注入，在所述非晶硅层的两侧形成掺杂的非晶硅层，使得非晶硅层两侧的载流子增多，可以起到部分有源层的作用，从而提高了器件性能。
由于现有的工艺中对过孔刻蚀的要求比较高，一般刻蚀设备易对有源层 过刻造成破坏或形成不良的源漏金属与源漏区的接触，因此需要使用专用的刻蚀设备。而本发明实施例中由于掺杂非晶硅层的存在，在中间绝缘层上形成过孔时，即使多晶硅有源层被过度刻蚀，但是由于掺杂的非晶硅层也能起到有源层的作用，因此仍然会形成良好的接触，不会影响器件性能，从而刻蚀过孔时无需专用的刻蚀设备，又由于非晶层硅能进一步阻挡背光照射有源层，因此进一步避免了背光照射导致多晶硅薄膜晶体管特性恶化，提高了器件的可靠性。
其中，在形成有源层的图形之后，对有源层和非晶硅层进行离子注入之前还可以包括：在有源层上依次形成栅极绝缘层和栅极的图形。
在对有源层和非晶硅层进行离子注入之后还可以包括：在栅极绝缘层和栅极上沉积中间绝缘层，并在中间绝缘层和栅极绝缘层的两侧形成两个过孔。
其中，隔离层可以为单层的氧化硅、氮化硅或二者的叠层。
其中，可选地，非晶硅层的厚度可以为
Figure PCTCN2015084319-appb-000012
和/或，隔离层的厚度可以为
Figure PCTCN2015084319-appb-000013
为了不增加掩膜板而达成本发明实施例改进多晶硅薄膜晶体管制作方法的目的，本发明实施例方法还可以包括：利用同一块掩膜板采用光刻刻蚀分别形成非晶硅层的图形与有源层的图形；和/或，利用同一块掩膜板采用光刻刻蚀分别形成隔离层的图形与栅极的图形，从而使得所形成的非晶硅层与有源层在衬底上的投影重合；和/或，隔离层与栅极在衬底上的投影重合。
可选地，离子注入工艺可采用具有质量分析仪的离子注入、不具有质量分析仪的离子云式注入、等离子注入或者固态扩散式注入等方法。本实施例中，可以采用主流的离子云式注入方法，可根据设计需要采用含硼如B2H6/H2或者含磷如PH3/H2的混合气体进行注入，离子注入能量可为10～200keV，优选能量在40～100keV。注入剂量可在1x1011～1x1020atoms/cm3范围内，建议剂量为1x1014～1x1018atoms/cm3。另外，在具体的制作工艺过程中可以根据需要增加热处理脱氢、沉积诱导金属、热处理晶化、准分子激光照射晶化、掺杂杂质的激活等工艺。
可选地，在衬底上与有源层对应的区域形成非晶硅层之前还可以包括：在衬底上形成缓冲层，以防止衬底中的金属离子杂质扩散至有源层中而影响TFT工作特性。
实施例4：
本发明实施例提供一种制作多晶硅薄膜晶体管的方法，参见图5，包括：
步骤501：在衬底上形成缓冲层。
本步骤中，衬底1为预先清洗的玻璃透明衬底，为了防止衬底中的金属离子杂质扩散至有源层中而影响TFT工作特性，可以在衬底1上首先形成一层采用氧化硅、氮化硅或者二者叠层形成的缓冲层。
步骤502：在衬底上与有源层对应的区域形成非晶硅层的图形。
参见图6，本步骤中，在衬底1的缓冲层上与多晶硅薄膜晶体管的有源层对应的区域形成非晶硅层7的图形。其中，非晶硅层7的厚度为
Figure PCTCN2015084319-appb-000014
Figure PCTCN2015084319-appb-000015
其形成方法可以为PECVD、LPCVD或者溅射方法，沉积温度在600℃以下。此时，为了减少掩膜板的个数，本步骤采用多晶硅薄膜晶体管的有源层的掩膜板形成非晶硅层7。
步骤503：在非晶硅层上与栅极对应的区域形成绝缘的隔离层的图形，隔离层的两端边缘在非晶硅层的两端边缘内。
本步骤中，参见图7，在非晶硅层7上与多晶硅薄膜晶体管的栅极对应的区域形成绝缘的隔离层8的图形，其中，隔离层8的两端边缘在非晶硅层7的两端边缘内，以使得隔离层8和非晶硅层7的两端形成台阶，为后续步骤中非晶硅转化为多晶硅的形核中心做准备。隔离层8可为单层的氧化硅、氮化硅或者二者的叠层。可使用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为
Figure PCTCN2015084319-appb-000016
可根据具体的设计需要选择合适的厚度。并且，为了减少掩膜板的个数，本步骤采用多晶硅薄膜晶体管的栅极的掩膜板形成隔离层8。
步骤504：在非晶硅层和隔离层上沉积非晶硅有源层，使之转变为多晶硅有源层，并形成有源层的图形。
本步骤中，参见图8，在非晶硅层7和隔离层8上沉积非晶硅有源层，并使之晶化，转变为多晶硅有源层，并采用光刻工艺形成有源层2的图形。在沉积非晶硅有源层后，可以以激光扫描等方法使之转变为多晶硅有源层2。在晶化的过程中，由于隔离层8两端台阶和非晶硅层7的存在，使得虚线所示的位置吸收的激光能量较低，此处仅能部分熔融，因而形成多晶硅形核中心，促进多晶硅沿沟道定向(图中虚线箭头所指方向)生长并易形成较大晶粒，从而可以提高器件电学性能。
其中有源层2的厚度为
Figure PCTCN2015084319-appb-000017
优选厚度为
Figure PCTCN2015084319-appb-000018
其形成方法可以为PECVD、LPCVD或者溅射方法，沉积温度在600℃以下。
步骤505：在所述有源层上依次形成栅极绝缘层和栅极的图形。
参见图9，在有源层2上依次形成栅极绝缘层3和栅极4。其中，栅极绝缘层3可采用单层的氧化硅、氮化硅或者二者的叠层，可使用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为
Figure PCTCN2015084319-appb-000019
可根据具体的设计需要选择合适的厚度，优选厚度为
Figure PCTCN2015084319-appb-000020
栅极4可为单层、两层或两层以上结构，由金属、金属合金如钼、铝、钼钨等构成，厚度在
Figure PCTCN2015084319-appb-000021
范围内，优选厚度为
Figure PCTCN2015084319-appb-000022
步骤506：对有源层和非晶硅层进行离子注入，在有源层的两侧形成两个源漏离子注入区，在非晶硅层的两侧形成掺杂的非晶硅层。
参见图10，本步骤中，以栅极4为掩膜板对有源层2和非晶硅层7均进行离子注入。离子注入工艺采用主流的离子云式注入方法，采用含硼如B2H6/H2或者含磷如PH3/H2的混合气体进行注入，离子注入能量可为10～200keV，注入剂量为1x1014～1x1018atoms/cm3。
步骤507：在栅极绝缘层和栅极上沉积中间绝缘层，并在中间绝缘层和栅极绝缘层的两侧形成连接有源层的两个源漏离子注入区的两个过孔。
参见图3，本步骤中，沉积中间绝缘层5并形成过孔6，由于掺杂非晶硅层7的存在，可以有效避免有源层2被过度刻蚀并形成良好的接触。其中，中间绝缘层5可采用单层的氧化硅、氮化硅或者二者的叠层。可使用采用PECVD、LPCVD、APCVD或ECR-CVD等方法沉积，厚度为
Figure PCTCN2015084319-appb-000023
Figure PCTCN2015084319-appb-000024
可根据具体的设计需要选择合适的厚度。
至此，则完成了本发明实施例多晶硅薄膜晶体管制作方法的全过程。
实施例5：
本发明实施例5还提供了一种显示装置，包括如上任一项所述的多晶硅薄膜晶体管。应该理解，显示装置一般包括显示基板，而多晶硅薄膜晶体管一般形成在例如为阵列基板的显示基板上。显示装置可以为显示面板、显示器、电视机、手机、导航仪、电子书、平板电脑等任意具有显示功能的设备或器件。
最后应说明的是：以上实施例仅用以说明本发明的技术方案，而非对其限制；尽管参照前述实施例对本发明进行了详细的说明，本领域的普通 技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。

Claims (13)

  1. 一种多晶硅薄膜晶体管，其特征在于，包括：
    衬底；
    形成于所述衬底上的隔离层；
    形成于所述衬底和所述隔离层上的多晶硅有源层，在所述有源层的两侧形成有两个源漏离子注入区，
    其中，所述隔离层的两端边缘在所述有源层的两端边缘内。
  2. 根据权利要求1所述的多晶硅薄膜晶体管，其特征在于，还包括：
    形成于所述衬底和所述隔离层之间的非晶硅层，所述非晶硅层与所述有源层的位置相对应，所述非晶硅层的两侧形成有两个源漏离子注入区。
  3. 根据权利要求2所述的多晶硅薄膜晶体管，其特征在于，所述多晶硅薄膜晶体管还包括：
    依次形成于所述有源层上的栅极绝缘层、栅极和中间绝缘层，以及形成在所述中间绝缘层和所述栅极绝缘层的两侧的两个过孔。
  4. 根据权利要求1所述的多晶硅薄膜晶体管，其特征在于：
    所述隔离层为单层的氧化硅、氮化硅或二者的叠层。
  5. 根据权利要求2所述的多晶硅薄膜晶体管，其特征在于：
    所述非晶硅层的厚度为
    Figure PCTCN2015084319-appb-100001
    和/或，所述隔离层的厚度为
    Figure PCTCN2015084319-appb-100002
  6. 根据权利要求3所述的多晶硅薄膜晶体管，其特征在于：
    所述非晶硅层与所述有源层在所述衬底上的投影重合；
    和/或，所述隔离层与所述栅极在所述衬底上的投影重合。
  7. 一种制作多晶硅薄膜晶体管的方法，其特征在于，包括：
    在衬底上形成隔离层的图形；
    在所述衬底和所述隔离层上沉积非晶硅层，使之转变为多晶硅层，并形成多晶硅有源层的图形；
    对所述有源层进行离子注入，在所述有源层的两侧形成两个源漏离子注入区，
    其中，所述隔离层的两端边缘在所述有源层的两端边缘内。
  8. 根据权利要求7所述的制作多晶硅薄膜晶体管的方法，其特征在于，所述方法还包括：
    在所述衬底上与所述有源层对应的区域形成非晶硅层的图形；
    在对所述有源层进行离子注入的同时对所述非晶硅层进行离子注入，在所述非晶硅层的两侧形成掺杂的非晶硅层。
  9. 根据权利要求8所述的制作多晶硅薄膜晶体管的方法，其特征在于，在所述形成有源层的图形之后，所述对所述有源层和所述非晶硅层进行离子注入之前还包括：在所述有源层上依次形成栅极绝缘层和栅极的图形；
    在所述对所述有源层和所述非晶硅层进行离子注入之后还包括：在所述栅极绝缘层和所述栅极上沉积中间绝缘层，并在所述中间绝缘层和所述栅极绝缘层的两侧形成两个过孔。
  10. 根据权利要求7所述的制作多晶硅薄膜晶体管的方法，其特征在于：
    所述隔离层为单层的氧化硅、氮化硅或二者的叠层。
  11. 根据权利要求9所述的制作多晶硅薄膜晶体管的方法，其特征在于：
    利用同一块掩膜板采用光刻刻蚀分别形成所述非晶硅层的图形与所述有源层的图形；
    和/或，利用同一块掩膜板采用光刻刻蚀分别形成所述隔离层的图形与所述栅极的图形。
  12. 根据权利要求7所述的制作多晶硅薄膜晶体管的方法，其特征在于：
    所述离子注入能量为10～200keV；
    和/或，所述离子注入剂量为1x1011～1x1020atoms/cm3。
  13. 一种显示装置，其特征在于，包括权利要求1-6中任一项所述的多晶硅薄膜晶体管。
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