CN1638022A - 多晶硅膜的形成方法 - Google Patents

多晶硅膜的形成方法 Download PDF

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CN1638022A
CN1638022A CNA2004100857849A CN200410085784A CN1638022A CN 1638022 A CN1638022 A CN 1638022A CN A2004100857849 A CNA2004100857849 A CN A2004100857849A CN 200410085784 A CN200410085784 A CN 200410085784A CN 1638022 A CN1638022 A CN 1638022A
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film
amorphous silicon
silicon film
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孙暻锡
李镐年
柳明官
朴宰彻
金億洙
李俊昊
权世烈
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Hydis Technologies Co Ltd
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Abstract

本发明提供一种多晶硅(poly－Si)膜的形成方法，本发明的多晶硅膜形成方法是一种通过激光照射使非晶硅(a－Si)膜结晶化以形成多晶硅膜的方法，其包括以下步骤：在玻璃基板上依次蒸镀隔离膜及非晶硅膜；在上述玻璃基板的后面蒸镀具有激光反射功能的金属膜；从上述非晶硅膜的前面照射激光，同时使由上述金属膜反射的激光被该非晶硅膜再吸收，由此使该非晶硅膜二次结晶。本发明的特征在于使非晶硅膜二次结晶，故能形成具有非常大的晶粒的多晶硅膜。

Description

多晶硅膜的形成方法
技术领域
本发明涉及一种液晶显示装置的制造方法，更详细地说，涉及用于制造多晶硅薄膜晶体管的多晶硅膜的形成方法。
背景技术
在液晶显示装置或有机发光显示装置中作为开关元件使用的薄膜晶体管(Thin Film Transistor，以下简称为TFT)是在上述显示装置性能中最重要的构成因素。作为TFT性能判断基准的迁移率(mobility)或漏泄电流等，很大程度上是由作为载流子通道的活性层具有何种状态或构造来决定，也就是由作为活性层材料的硅薄膜具有何种状态或构造所左右。在目前广为使用的液晶显示装置中，TFT的活性层几乎都是非晶硅(amorphous silicon，以下简称为a-Si)。
但是，以a-Si作为活性层的a-Si TFT的迁移率很低，仅为0.5cm2/Vs左右，如把它用于制作液晶显示装置的所有各类开关元件，则会受到很大限制。这是因为液晶显示装置的外围电路所使用的驱动元件必须以高速运转，而上述的a-Si TFT不能满足作为外围电路驱动元件对运转速度的要求，这表明对a-Si TFT而言，实质上很难把它用于制作外围电路驱动元件。
另一方面，以多晶硅(polycrystalline silicon，以下简称为poly-Si)作为活性层的poly-Si TFT，因其迁移率高达数十～数百cm2/Vs，可以达到用于外围电路的驱动元件所要求的高驱动速度。因此，若能在玻璃基板上形成poly-Si膜，则不仅可用于像素开关元件，还可以实现应用于外围电路驱动元件。另外，不仅是对形成外围电路必需的其它模块工序已不再必要，而且在形成像素区域时，甚至可一并形成外围电路的驱动元件等部件，从而可望节省外围电路所用驱动部件的费用。
此外，poly-Si TFT因具有高迁移率，可比a-Si TFT更小型化，另外通过集成工艺可同时形成外围电路的驱动元件和像素领域的开关元件，因此更易做到线宽微细化，这对于得到用a-Si TFT-LCD很难实现的高解像度是非常有利的。
另外，由于poly-Si TFT具有高的电流特性，很适宜于作为下一代平板显示装置的有机发光显示装置驱动元件。
因此，最近正在活跃地开展着有关在玻璃基板上形成poly-Si膜以制造TFT的poly-Si TFT研究工作。
作为上述在玻璃基板上形成poly-Si膜的方法，可举出在蒸镀a-Si膜后进行热处理使a-Si结晶化的方法，但此时在600℃以上的高温下将发生玻璃基板的变形，由此会造成可靠性及收率的降低。
已提出了利用受激准分子激光(Excimer Laser)的低温多结晶化方法，可以做到仅使a-Si膜进行结晶化而不会对玻璃基板造成热损伤(thermaldamage)。此法又可再分为不使用掩膜的传统性受激准分子激光退火(ExcimerLaser Annealing，以下简称ELA)方法，以及使用掩膜控制激光照射区域的连续侧面结晶化(Sequential Lateral Solidification，以下简称为SLS)方法。
为了防止杂质由玻璃基板向硅层的扩散，上述两种方法都采取了在蒸镀了隔离膜的状态下再蒸镀a-Si膜的措施。其次为了去除a-Si膜内的氢，实行了脱氢热处理过程。然后使a-Si膜在极短的时间内暴露于受激准分子激光下，在不致诱发玻璃基板变形的情况下，使a-Si经由液态转变为poly-Si膜。
但是，上述两种方法在增大晶粒的尺寸方面都受到了限制。
也就是说在传统的ELA方法的情况下，其晶粒尺寸一般为0.1μm以下，而该种大小程度的晶粒尺寸对于集成驱动电路来说其迁移率不足。
在SLS方法的情况下，结晶化过程由照射区域的端部开始向内部诱导，最后才进行照射区域中心部的结晶化。在结晶化进行期间处于熔点以下的温度时，如果中心部的温度下降，就会进行成核(nucleation)，致使不能得到大的晶粒。其结果是采用现行的SLS方法后，多晶硅膜侧面生长的长度最大只能达到4μm，因此也难于把它实际应用于外围电路所用TFT中。
发明内容
因此，本发明是为了解决上述问题而提出的，其目的是提供一种能使晶粒尺寸极大化的poly-Si膜的形成方法。
本发明的另一目的是提供一种能使晶粒尺寸极大化且能提高poly-SiTFT性能的poly-Si膜的形成方法。
本发明的再一目的是提供一种能提高poly-Si TFT性能且可在单一基板上集成像素开关元件及外围电路驱动元件的poly-Si膜的形成方法。
为了达到上述目的，作为一种通过激光照射使a-Si膜结晶化以形成poly-Si膜的方法，本发明提供一种poly-Si膜的形成方法，该方法包括以下步骤：在玻璃基板上依次蒸镀隔离膜和a-Si膜的步骤；在上述玻璃基板的后面蒸镀具有激光反射功能的金属膜的步骤；以及从上述a-Si膜的前面照射激光，同时使由上述金属膜反射的激光被该a-Si膜再吸收，由此使该a-Si膜二次结晶。
上述金属膜由选自Mo、Al、A1Nd、Cr、Cu、MoW、W、Ta或Ti中任意一种的单一膜、或者至少两种或两种以上的复合膜构成。
此外，作为通过激光照射使a-Si膜结晶化以形成poly-Si膜的方法，本发明提供一种poly-Si膜的形成方法，该方法包含以下步骤：在玻璃基板上形成具有激光反射功能的栅电极的步骤；在基板的前表面上蒸镀栅极绝缘膜以覆盖所述栅电极的步骤；在上述栅极绝缘膜上依次蒸镀a-Si膜的步骤；以及从上述a-Si膜的前面照射激光，同时使由上述栅电极反射的激光被该a-Si膜再吸收，由此使该a-Si膜二次结晶的步骤。
关于上述本发明的目的、特征和优点等，参照以下对本发明的优选实施例的说明，将更为明确。
附图说明
图1A和图1B是说明通过本发明的实施例形成多晶硅膜的方法的工艺断面图。
图2A和图2B是由现行方法及本发明所形成的多晶硅膜的结晶照片。
图3是说明通过本发明其他实施例形成多晶硅膜的方法的断面图。
附图符号说明
10  玻璃基板
22  隔离膜
14  非晶硅膜
16  金属膜
20  激光
22  栅电极
24  栅极绝缘膜
具体实施形式
以下参照附图对符合本发明的详细说明实施例。
首先，对本发明的技术原理进行说明。本发明在通过受激准分子激光照射进行低温结晶化工艺流程时，在a-Si膜的下部形成具有高反射度的金属膜，经Si膜吸收后的部分透射光被上述金属膜反射，再次为Si膜所吸收，从而一次激光照射收到两次照射的效果。也就是通过二重激光照射的效果，以增大poly-Si膜的晶粒尺寸。
为了对本发明中poly-Si膜的形成方法作更详细的说明，图1A及图1B所示为不同工序的断面示意图，其说明如下。下述本发明的方法也可适用于形成具有顶栅极(トツプゲツト)结构的TFT。
如图1A所示，为了防止后续加热工程时从玻璃基板向活性层poly-Si膜有不必要的离子流入，在玻璃基板10上形成由SiOx、SiOxNy或SiNx等组成的隔离膜，然后在上述隔离膜12上蒸镀待结晶的a-Si膜14。然后，为了除去a-Si膜14内的氢，在400℃以上温度下对基板上的形成物进行脱氢热处理。
在进行通过激光照射使a-Si膜结晶化的工序之前，预先在玻璃基板的后面蒸镀具有激光反射功能的金属膜16。此处所说的金属膜16是由具有优良反射率的Mo、Al、AlNd、Cr、Cu、MoW、W、Ta或Ti的单一金属膜、或至少两种或两种以上的复合膜构成。
如图1B所示，按传统的ELA方法或SLS方法从a-Si膜前面用激光20照射a-Si，由此使上述a-Si膜结晶化形成poly-Si膜18。此时，照射激光20的一部分经a-Si膜吸收后，透过a-Si膜经由隔离膜12到达基板10，然后被在基板10后面形成的具有反射功能的金属膜16所反射，依次经由基板10和隔离膜12再次被a-Si膜吸收。因此，通过一次激光照射取得了二次激光照射的效果。由此，结晶化poly-Si膜18的晶粒大小程度较以前大幅增加。
更详细地说，以往是吸收激光后成为熔融液态状的Si膜部分从其与未受激光照射的Si膜部分的界面开始凝固，并往照射区的中心部诱导结晶化。在凝固过程中，由熔融状态的Si与下部膜层或基板的温度差所引起的热传导使中心部温度快速下降，因此在诱导结晶化尚未完成之前就已发生了晶核形成，致使生成小晶粒。因此，以往为了在发生成核前就完成结晶化过程，就只有采取减小照射区域范围的措施。一般来说，照射区域的大小约为5μm左右，结晶化完成后晶粒的大小最大约为3.5～4μm左右。
本发明中，透射的激光20由金属膜16反射后再次入射至Si膜，因此抑制了熔融态Si膜温度的下降，可使上述Si膜处于熔融状态的时间较以前延长，由此增加了诱导晶粒生长的时间，最终所得的poly-Si膜18的晶粒大小也较以往增加。例如，用激光照射区域的间隔约为10μm左右的狭缝进行激光照射时时，最终所得的poly-Si膜18的晶粒大小可比以往大约增加二倍。
图2A及图2B分别是用以往的方法及本发明形成的poly-Si膜的结晶照片。如图2A所示，在由以往技术所形成的poly-Si膜的情况下，由于中心部的晶核生成，晶粒的粒度不大。如图2B所示，在由本发明形成的poly-Si膜的情况下，因为一次激光照射实际产生了两次激光照射的效果，从而其晶粒的大小也相对较大。
从结果来看，本发明在进行激光照射前，在a-Si膜14的背面，或更正确地说，在玻璃基板10的后面形成具有激光反射功能的金属膜16，因而能很容易地形成大晶粒的poly-Si膜18。
下述内容未作图示。在去除了玻璃基板后面的金属膜的状态下，按照公知的TFT制造工艺，也就是依次进行有源模式(アクテイブパタ一ン)形成工序、栅极绝缘膜的蒸镀工序、栅极形成工序、离子注入工序、绝缘膜形成工序、接触孔形成工序以及源电极/漏电极形成工序，在玻璃基板的适当位置上形成poly-Si TFT，然后进行像素电极的形成工序，制成阵列基板。然后置于由另行工艺制造的彩色滤波(カラ一フイルタ一)基板和液晶层之间，使其合成一体，制成TFT-LCD。
图3是说明通过本发明其他实施例形成poly-Si膜的方法的断面图，对其说明如下。如果以前述的实施例可以适用于形成顶栅极结构的TFT，本实施例则可应用于形成底栅极(ボトムゲ-ト)结构的TFT。
首先在玻璃基板10上形成栅电极22后，再在基板前表面上形成栅极绝缘膜24。其次，在上述绝缘膜24上蒸镀待结晶化的a-Si膜14，然后用经过模式化的激光，也就是使用具有缝隙掩膜图形的激光20，照射上述a-Si膜14。
此时，已模式化的激光20被a-Si膜14吸收后，透过的激光由电极22反射，并再次被a-Si膜14吸收。与前述的实施例相同，由此能形成具有比以往大的晶粒的poly-Si膜。
此后，可实施通常的底栅极TFT制造工艺流程，继而形成像素电极，制成阵列基板。
发明效果
如上所述，本发明通过激光照射低温结晶化方法使a-Si膜结晶化成为poly-Si膜。在实行激光照射前，在玻璃基板的后面蒸镀具有激光反射功能的金属膜，在此状态下实行激光照射，就能使Si膜的熔融状态延长并从而增加了晶粒生长的时间，由此能形成具有较以前显著增大的晶粒的poly-Si膜。
因此，由于能制成具有大尺寸晶粒的poly-Si膜，使其具有高电子迁移率等特性，可提高poly-Si TFT性能，从而可提高液晶显示装置的产品性能。
以上对本发明的特定实施例进行了说明与图示，本领域技术人员可对此进行修正或作形式上的变化。因此，只要是真正属于本发明的思想范围内，即可认为所列的专利要求范围包含了这一切修正与形式变化。

Claims (3)

1、多晶硅膜的形成方法，该方法是利用激光照射通过使非晶硅膜结晶而形成多晶硅膜的方法，其特征在于，该方法包含以下步骤：
在玻璃基板上依次蒸镀隔离膜和非晶硅膜的步骤；
在上述玻璃基板的后面蒸镀具有激光反射功能的金属膜的步骤；和
从上述非晶硅膜的前面照射激光，同时使由上述金属膜反射的激光被该非晶硅膜再吸收，由此使该非晶硅膜二次结晶的步骤。
2、权利要求1所述的多晶硅膜形成方法，其特征在于，所述金属膜由选自Mo、Al、AlNd、Cr、Cu、MoW、W、Ta和Ti中任意一种的单一膜、或者其中至少两种或两种以上的复合膜构成。
3、多晶硅膜的形成方法，该方法是利用激光照射通过使非晶硅膜结晶而形成多晶硅膜的方法，其特征在于，该方法包含以下步骤：
在玻璃基板上形成具有激光反射功能的栅电极的步骤；
在基板的前表面上蒸镀栅极绝缘膜以覆盖上述栅电极的步骤；
在上述栅极绝缘膜上依次蒸镀非晶硅膜的步骤；和
从上述非晶硅膜的前面照射激光，同时使由上述栅电极反射的激光被该非晶硅膜再吸收，由此使该非晶硅膜二次结晶的步骤。
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Cited By (7)

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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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WO2009068756A1 (fr) 2007-11-28 2009-06-04 Commissariat A L'energie Atomique Procede de cristallisation
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CN102956499A (zh) * 2011-08-23 2013-03-06 广东中显科技有限公司 多晶硅薄膜的制备方法
FR3073321B1 (fr) * 2017-11-07 2019-12-20 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de cristallisation d'une couche utile
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Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3150840B2 (ja) 1994-03-11 2001-03-26 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP3424891B2 (ja) * 1996-12-27 2003-07-07 三洋電機株式会社 薄膜トランジスタの製造方法および表示装置
KR100269312B1 (ko) * 1997-10-14 2000-10-16 윤종용 실리콘막의결정화방법및이를이용한박막트랜지스터-액정표시장치(tft-lcd)의제조방법
JP2000208771A (ja) * 1999-01-11 2000-07-28 Hitachi Ltd 半導体装置、液晶表示装置およびこれらの製造方法
KR100290014B1 (ko) * 1999-04-01 2001-05-15 구본준, 론 위라하디락사 실리콘 박막 결정화방법과 이를 이용한 박막 트랜지스터 및 그제조방법
TW544743B (en) * 1999-08-13 2003-08-01 Semiconductor Energy Lab Method of manufacturing a semiconductor device
JP2001102323A (ja) * 1999-09-30 2001-04-13 Matsushita Electric Ind Co Ltd レーザアニール装置および薄膜トランジスタの製造方法
US6524877B1 (en) * 1999-10-26 2003-02-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, and method of fabricating the same
JP5025057B2 (ja) * 2001-05-10 2012-09-12 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP4008716B2 (ja) * 2002-02-06 2007-11-14 シャープ株式会社 フラットパネル表示装置およびその製造方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101894744B (zh) * 2010-06-11 2012-09-05 南开大学 一种采用背面保温层技术激光晶化多晶硅薄膜的方法
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US9837542B2 (en) 2015-04-16 2017-12-05 Boe Technology Group Co., Ltd. Polycrystalline silicon thin-film transistor
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