CN104900710A - 薄膜晶体管及其制备方法、阵列基板 - Google Patents

薄膜晶体管及其制备方法、阵列基板 Download PDF

Info

Publication number
CN104900710A
CN104900710A CN201510307486.8A CN201510307486A CN104900710A CN 104900710 A CN104900710 A CN 104900710A CN 201510307486 A CN201510307486 A CN 201510307486A CN 104900710 A CN104900710 A CN 104900710A
Authority
CN
China
Prior art keywords
reflector plate
film transistor
thin
active area
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510307486.8A
Other languages
English (en)
Inventor
卜倩倩
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201510307486.8A priority Critical patent/CN104900710A/zh
Publication of CN104900710A publication Critical patent/CN104900710A/zh
Priority to US15/099,185 priority patent/US9748284B2/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
    • H01L27/1285—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本发明提供一种薄膜晶体管及其制备方法、阵列基板，属于多晶硅薄膜晶体管制备技术领域，其可解决现有的多晶硅薄膜晶体管中难以控制有源区性能的问题。本发明的薄膜晶体管包括基底、由多晶硅构成的有源区，且至少在对应有源区的位置设有多个间隔的反射片；其中，所述有源区的多晶硅通过对非晶硅层进行激光照射形成，且所述激光从非晶硅层远离反射片的一侧射入。

Description

薄膜晶体管及其制备方法、阵列基板
技术领域
本发明属于多晶硅薄膜晶体管制备技术领域，具体涉及一种薄膜晶体管及其制备方法、阵列基板。
背景技术
在多晶硅薄膜晶体管中，采用多晶硅材料作构成有源区。其中，有源区的多晶硅可由非晶硅层形成，即可先形成非晶硅层，之后用激光照射非晶硅层使其熔化，熔化的硅再凝固后即转变为多晶硅，该工艺也称为“激光退火”。
发明人发现现有技术中至少存在如下问题：有源区中多晶硅的晶粒的尺寸、生长方向、分布等对薄膜晶体管的性能有重要影响，而这些参数均与激光退火中的温度分布(温度梯度)有关。但现有激光退火工艺只能通过调整激光功率简单的控制退火温度高低，而很难形成特定的温度梯度，故也就无法控制所得多晶硅有源区的性能。
发明内容
本发明针对现有的多晶硅薄膜晶体管中难以控制有源区性能的问题，提供一种多晶硅有源区性能很好的薄膜晶体管及其制备方法、阵列基板。
解决本发明技术问题所采用的技术方案是一种薄膜晶体管，包括基底、由多晶硅构成的有源区，且
至少在对应有源区的位置设有多个间隔的反射片；
其中，所述有源区的多晶硅通过对非晶硅层进行激光照射形成，且所述激光从非晶硅层远离反射片的一侧射入。
优选的是，每个反射片为矩形，长度在30～50nm，宽度在10～30nm；相邻反射片间的距离在30～70nm。
优选的是，所述反射片的厚度在50～80nm。
优选的是，所述有源区位于所述反射片远离基底的一侧。
优选的是，所述薄膜晶体管还包括栅绝缘层、栅极、源极、漏极；所述栅绝缘层、栅极、源极、漏极均位于所述有源区远离反射片的一侧。
优选的是，所述反射片由金属材料构成；所述有源区与反射片之间设有绝缘层。
进一步优选的是，所述金属材料包括钕和/或铝。
优选的是，所述薄膜晶体管还包括：设于所述反射片之间的间隙中的、与反射片厚度相同的填充层。
优选的是，所述反射片仅位于对应有源区的位置；或，在整个基底上均设有所述反射片。
解决本发明技术问题所采用的技术方案是一种阵列基板，其包括：
上述的薄膜晶体管。
解决本发明技术问题所采用的技术方案是一种上述薄膜晶体管的制备方法，其包括：
在基底上形成非晶硅层和反射片的步骤；
通过激光照射使所述非晶硅层晶化的步骤，其中激光从非晶硅层远离反射片的一侧射入。
本发明的薄膜晶体管中包括反射片，且其有源区的多晶硅材料是由非晶硅层经激光退火而得的，在激光退火中，由于非晶硅层很薄，故激光可穿过非晶硅层并被反射片反射回来而再次照射在非晶硅层上；这样，有反射片处的非晶硅层被激光两次照射，温度较高，无反射片处的非晶硅层只被激光照射一次，温度较低，从而在有反射片处和无反射片处间形成了可控的温度梯度(通过调整反射片即可控制)，故激光退火中形成的多晶硅的晶粒尺寸、生长方向、分布等也就可控，从而可改善薄膜晶体管的性能。
附图说明
图1为本发明的实施例的一种薄膜晶体管的剖面结构示意图；
图2为本发明的实施例的一种薄膜晶体管在形成反射片后的剖面结构示意图；
图3为本发明的实施例的一种薄膜晶体管在形成填充层后的剖面结构示意图；
图4为本发明的实施例的一种薄膜晶体管在非晶硅层后的剖面结构示意图；
图5为本发明的实施例的一种薄膜晶体管在激光退火时的剖面结构示意图；
图6为本发明的实施例的一种薄膜晶体管在形成有源区后的剖面结构示意图；
其中，附图标记为：1、反射片；31、非晶硅层；32、多晶硅层；3、有源区；4、栅极；51、源极；52、漏极；81、填充层；82、绝缘层；83、栅绝缘层；84、钝化层；9、基底。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
如图1至图6所示，本实施提供一种薄膜晶体管，其包括基底9、由多晶硅构成的有源区3，且
至少在对应有源区3的位置设有多个间隔的反射片1；
其中，有源区3的多晶硅通过对非晶硅层31进行激光照射形成，且激光从非晶硅层31远离反射片1的一侧射入。
也就是说，本实施例的薄膜晶体管包括设于基底9上的多晶硅的有源区3，且还包括许多间隔设置的、能反光的反射片1，反射片1至少分布在有源区3处，即有源区3处必然设有多个反射片1。
有源区3的多晶硅材料是由非晶硅层31经激光退火而得的，如图5所示，在激光退火工艺中，由于非晶硅层31很薄，故激光可穿过非晶硅层31，并被反射片1反射回来而再次照射在非晶硅层31上；这样，有反射片1处的非晶硅层31被激光两次照射，温度较高，无反射片1处的非晶硅层31只被激光照射一次，温度较低，从而在有反射片1处和无反射片1处间形成了可控的温度梯度(通过调整反射片1的尺寸、形状、位置即可控制)，故其形成的多晶硅的晶粒尺寸、生长方向、分布等也就可控，从而可改善薄膜晶体管的性能。
优选的，每个反射片1为矩形，长度在30～50nm，宽度在10～30nm；相邻反射片1间的距离在30～70nm。
也就是说，反射片1可以为矩形形式，且其形状和尺寸符合以上的条件。采用这样的反射片1时，每个反射片1基本对应一个晶粒，即反射片1形成的高温区即对应晶粒的核心部分，而其周围的低温区有利于该晶粒按预定方向(即温度梯度方向)生长，从而可得到最符合要求的晶粒。
优选的，反射片1的厚度在50～80nm。
显然，反射片1厚度太薄则无法起到良好的反射作用，而太厚则会对其他结构造成影响，而以上的厚度范围是优选的。
优选的，有源区3位于反射片1远离基底9的一侧。
也就是说，如图1所示，反射片1优选设于有源区3下方，即在制备时优选先形成反射片1，再制备有源区3。这是因为本实施例的薄膜晶体管在制备时，激光必须从有源区3(非晶硅层31)远离反射片1的一侧射入，而通常的激光退火工艺中，激光都是从非晶硅层31远离基底9的一侧射入的，故以上的结构正好可与现有的激光技术配合。
优选的，薄膜晶体管还包括栅绝缘层83、栅极4、源极51、漏极52；且栅绝缘层83、栅极4、源极51、漏极52均位于有源区3远离反射片1的一侧。
显然，在薄膜晶体管中，还包括栅绝缘层83、栅极4、源极51、漏极52等其他结构，而反射片1的存在对这些结构与有源区3的连接、感应等必然存在一定的影响，因此，优选使反射片1位于有源区3的一侧，而其他结构均位于有源区3的另一侧。
优选的，当反射片1设于有源区3下方(即有源区3位于反射片1远离基底9的一侧)时，其他结构均位于有源区3远离反射片1的一侧，即如图1所示，栅绝缘层83、栅极4、源极51、漏极52等均应位于有源区3上方，薄膜晶体管为顶栅型。以上结构之所以优选，是因为激光退火必然要在形成反射片1和非晶硅层31后进行，而进行激光退火时，优选没有其他结构(如栅极4、源极51、漏极52等，因为它们会影响激光传递)，而根据以上结构，在形成反射片1和非晶硅层31时其他结构均未形成，故最有利于进行激光退火。
优选的，反射片1由金属材料构成；有源区3与反射片1之间设有绝缘层82；而该金属材料更优选包括钕和/或铝。
也就是说，可用金属制造以上的反射片1，这是因为金属是最常用的反射材料，制备工艺成熟、成本低；具体的，最优选的金属材料可为钕、铝、钕铝合金等，因为其具有较高的反射率。又由于金属是导电的，故金属构成的反射片1若与有源区3接触则会影响其性能，因此还需要在反射片1与有源区3间增设由绝缘材料(氧化硅、氮化硅等)构成的绝缘层82。
当然，若采用绝缘反光材料制备反射片1也是可行的，而此时反射片1可直接与有源区3接触，其间不必设置绝缘层82。
优选的，薄膜晶体管还包括：设于反射片1之间的间隙中的、与反射片1厚度相同的填充层81。
可见，反射片1是间隔设置的，由此反射片1和其间隔处的上表面是凹凸不平的，而这种凹凸会对在其上形成的结构造成影响。为此，如图1所示，可在反射片1间的缝隙中形成与反射片1等厚的填充层81，填充层81的上表面与反射片1的上表面一起构成平坦的面，便于形成其他结构。
当然，若不设置填充层81，或者反射片1上设置一个较厚的层而将以上凹凸消除，也都是可行的。
优选的，根据本实施例的一种优选方式，反射片1仅位于对应有源区3的位置。
也就是说，可仅在有源区3所对应的区域中才设有以上的反射片1，从而避免反射片1对其他位置的结构造成不良影响。
优选的，作为本实施例的另一种优选方式，在整个基底9上均设有反射片1。
也就是说，反射片1可以在整个基底9上均有分布(当然反射片1间仍有间隔)。这是因为薄膜晶体管通常用于阵列基板等之中，一个阵列基板中往往包括很多处于特定位置的薄膜晶体管(有源区3)，若反射片1仅位于有源区3，则对于反射片1形成位置的精度要求很高。
本实施例还提供一种阵列基板，其包括上述的薄膜晶体管。
本实施的阵列基板可为用于液晶显示、有机发光二极管显示等的阵列基板，其中包括排成阵列的大量薄膜晶体管，在这些薄膜晶体管中至少有一个为上述的薄膜晶体管。
当然，在阵列基板中，还可包括引线(栅极线、数据线、公共电极线等)、像素电极、公共电极、有机发光二极管、像素界定层等其他已知结构，在此不再详细描述。
本实施例还提供一种上述薄膜晶体管的制备方法，其包括：
在基底9上形成非晶硅层31和反射片1的步骤；
通过激光照射使非晶硅层31晶化的步骤，其中激光从非晶硅层31远离反射片1的一侧射入。
也就是说，在制备上述薄膜晶体管时，先要形成非晶硅层31和反射片1，之后从非晶硅层31远离反射片1的一侧射入激光，进行激光退火，将非晶硅层31晶化。其中，非晶硅层31和反射片1的形成顺序可依照薄膜晶体管的结构决定，只要二者都在激光退火前形成即可。
当然，薄膜晶体管的制备过程中还包括形成多晶硅有源区3的步骤；具体的，其可以是对完整的非晶硅层31进行晶化而得到完整的多晶硅层32，之后再对多晶硅层32进行构图得到有源区3；或者，也可先通过构图使非晶硅层31形成对应有源区3的图形，之后再剩余的非晶硅层31晶化，直接形成有源区3。
其中，构图工艺是指除去一个完整的层的一部分，从而使其剩余部分形成所需结构的工艺，其具体可包括形成材料层-涂布光刻胶-曝光-显影-刻蚀-光刻胶剥离等步骤中的一步或多步。
同时，薄膜晶体管的制备方法还包括形成栅绝缘层83、栅极4、源极51、漏极52等其他结构的步骤，这些步骤可根据薄膜晶体管的结构设定。
具体的，下面提供一种完整的薄膜晶体管的制备方法：
S101、通过构图工艺，在基底9上形成包括反射片1的图形。
也就是说，如图2所示，通过构图工艺在基底9上形成上述的反射片1。其中，基底9可由玻璃构成，而反射片1可由上述的金属构成，其尺寸、形状符合以上的要求。
S102、通过构图工艺，在完成前述步骤的基底9上形成包括填充层81的图形。
也就是说，如图3所示，通过构图工艺在反射片1间的空隙中形成上述的填充层81。其中，填充层81可由氮化硅(SiNx)构成，因为氮化硅与玻璃的结合力较强。
S103、在完成前述步骤的基底9上形成绝缘层82。
也就是说，形成覆盖反射片1和填充层81的绝缘层82，以保证反射片1与有源区3隔开。其中，绝缘层82可由氧化硅(SiOx)构成，因为氧化硅与硅的结合强度较高。
S104、在完成前述步骤的基底9上形成非晶硅层31。
也就是说，如图4所示，形成覆盖在绝缘层82上的非晶硅层31。其中，非晶硅层31的厚度可在40～50nm之间。
S105、进行激光退火，使非晶硅层31晶化形成多晶硅层32，其中，激光从非晶硅层31远离反射片1的一侧射入。
也就是说，如图5所示，从非晶硅层31上方用激光照射非晶硅层31，在照射过程中，反射片1处的激光被反射片1回来，再次照射非晶硅层31，使该处的非晶硅层31局部升温，形成所需的温度梯度，保证所形成的多晶硅层32的晶粒的尺寸、生长方向、分布等符合要求。
其中，激光退火的参数可为：
激光波长：308nm；
激光能量：200～500豪焦/平方厘米；
重叠度(激光两次扫过区域中重叠部分的比)：96～99％。
S106、通过构图工艺，用多晶硅层32形成包括有源区3的图形。
也就是说，如图6所示，除去有源区3外的多晶硅层32，使剩余的多晶硅层32形成有源区3。
当然，本工艺也可在步骤S104中对非晶硅层31进行，也就是说，可以现在S104步骤中将非晶硅层31图案化(对应有源区3的图案)，这样在S105步骤的激光退火中，剩余非晶硅层31晶化后即直接转变为有源区3。
S107、形成包括栅绝缘层83、栅极4、钝化层84、源极51、漏极52的图形，得到薄膜晶体管。
也就是说，用常规工艺继续形成薄膜晶体管中的栅绝缘层83、栅极4、钝化层84、源极51、漏极52等其他结构，从而完成薄膜晶体管的制备，得到如图1所示的薄膜晶体管。由于这些结构的具体形式、制备方法等是已知的且多样的，故在此不再详细描述。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (11)

1.一种薄膜晶体管，包括基底、由多晶硅构成的有源区，其特征在于，
至少在对应有源区的位置设有多个间隔的反射片；
其中，所述有源区的多晶硅通过对非晶硅层进行激光照射形成，且所述激光从非晶硅层远离反射片的一侧射入。
2.根据权利要求1所述的薄膜晶体管，其特征在于，
每个反射片为矩形，长度在30～50nm，宽度在10～30nm；
相邻反射片间的距离在30～70nm。
3.根据权利要求1所述的薄膜晶体管，其特征在于，
所述反射片的厚度在50～80nm。
4.根据权利要求1至3中任意一项所述的薄膜晶体管，其特征在于，
所述有源区位于所述反射片远离基底的一侧。
5.根据权利要求1至3中任意一项所述的薄膜晶体管，其特征在于，还包括栅绝缘层、栅极、源极、漏极；
所述栅绝缘层、栅极、源极、漏极均位于所述有源区远离反射片的一侧。
6.根据权利要求1至3中任意一项所述的薄膜晶体管，其特征在于，
所述反射片由金属材料构成；
所述有源区与反射片之间设有绝缘层。
7.根据权利要求6所述的薄膜晶体管，其特征在于，
所述金属材料包括钕和/或铝。
8.根据权利要求1至3中任意一项所述的薄膜晶体管，其特征在于，还包括：
设于所述反射片之间的间隙中的、与反射片厚度相同的填充层。
9.根据权利要求1至3中任意一项所述的薄膜晶体管，其特征在于，
所述反射片仅位于对应有源区的位置；
或
在整个基底上均设有所述反射片。
10.一种阵列基板，其特征在于，包括：
权利要求1至9中任意一项所述的薄膜晶体管。
11.一种薄膜晶体管的制备方法，其特征在于，所述薄膜晶体管权利要求1至9中任意一项所述的薄膜晶体管，所述薄膜晶体管的制备方法包括：
在基底上形成非晶硅层和反射片的步骤；
通过激光照射使所述非晶硅层晶化的步骤，其中激光从非晶硅层远离反射片的一侧射入。
CN201510307486.8A 2015-06-08 2015-06-08 薄膜晶体管及其制备方法、阵列基板 Pending CN104900710A (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201510307486.8A CN104900710A (zh) 2015-06-08 2015-06-08 薄膜晶体管及其制备方法、阵列基板
US15/099,185 US9748284B2 (en) 2015-06-08 2016-04-14 Thin film transistor, method for fabricating the same, and array substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510307486.8A CN104900710A (zh) 2015-06-08 2015-06-08 薄膜晶体管及其制备方法、阵列基板

Publications (1)

Publication Number Publication Date
CN104900710A true CN104900710A (zh) 2015-09-09

Family

ID=54033253

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510307486.8A Pending CN104900710A (zh) 2015-06-08 2015-06-08 薄膜晶体管及其制备方法、阵列基板

Country Status (2)

Country Link
US (1) US9748284B2 (zh)
CN (1) CN104900710A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017107274A1 (zh) * 2015-12-21 2017-06-29 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制备方法
WO2022164109A1 (ko) * 2021-01-27 2022-08-04 주식회사 엘지에너지솔루션 보호회로부 및 리드부와 보호회로부의 접합방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246554A (ja) * 1996-03-04 1997-09-19 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法および液晶表示装置
US20040161913A1 (en) * 2000-11-29 2004-08-19 Ritsuko Kawasaki Laser irradiation method and method of manufacturing a semiconductor device
CN1638022A (zh) * 2003-12-30 2005-07-13 京东方显示器科技公司 多晶硅膜的形成方法
CN104157700A (zh) * 2014-09-01 2014-11-19 信利（惠州）智能显示有限公司 低温多晶硅薄膜晶体管及其制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005250454A (ja) * 2004-02-06 2005-09-15 Sanyo Electric Co Ltd 光センサ付きディスプレイおよびその製造方法
TWI327447B (en) * 2006-10-16 2010-07-11 Chimei Innolux Corp Method of fabricating a thin film transistor
JPWO2011161714A1 (ja) * 2010-06-21 2013-08-19 パナソニック株式会社 シリコン薄膜の結晶化方法およびシリコンｔｆｔ装置の製造方法
KR102108359B1 (ko) * 2013-04-03 2020-05-11 삼성디스플레이 주식회사 유기 발광 표시 장치 및 이의 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09246554A (ja) * 1996-03-04 1997-09-19 Matsushita Electric Ind Co Ltd 薄膜トランジスタの製造方法および液晶表示装置
US20040161913A1 (en) * 2000-11-29 2004-08-19 Ritsuko Kawasaki Laser irradiation method and method of manufacturing a semiconductor device
CN1638022A (zh) * 2003-12-30 2005-07-13 京东方显示器科技公司 多晶硅膜的形成方法
CN104157700A (zh) * 2014-09-01 2014-11-19 信利（惠州）智能显示有限公司 低温多晶硅薄膜晶体管及其制备方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017107274A1 (zh) * 2015-12-21 2017-06-29 武汉华星光电技术有限公司 一种低温多晶硅薄膜晶体管及其制备方法
US10192975B2 (en) 2015-12-21 2019-01-29 Wuhan China Star Optoelectronics Technology Co., Ltd Low temperature polycrystalline silicon thin film transistor
WO2022164109A1 (ko) * 2021-01-27 2022-08-04 주식회사 엘지에너지솔루션 보호회로부 및 리드부와 보호회로부의 접합방법

Also Published As

Publication number Publication date
US20160358952A1 (en) 2016-12-08
US9748284B2 (en) 2017-08-29

Similar Documents

Publication Publication Date Title
KR101230299B1 (ko) 박막 트랜지스터 표시판
CN102498552B (zh) 使用脉冲序列退火方法将薄膜固相再结晶的方法
US20160020096A1 (en) Manufacture Method Of Low Temperature Poly Silicon, Manufacturing Method Of TFT Substrate Utilizing The Method, And TFT Substrate Structure
KR100507553B1 (ko) 결정성 반도체막, 그의 제조방법, 반도체장치 및 그의제조방법
CN103700695A (zh) 低温多晶硅薄膜及其制备方法、晶体管
CN104157700B (zh) 低温多晶硅薄膜晶体管及其制备方法
KR101309491B1 (ko) 액정 표시 장치 및 그 제조 방법
TW544939B (en) Thin film semiconductor device, production process and information display
CN104900710A (zh) 薄膜晶体管及其制备方法、阵列基板
KR100742380B1 (ko) 마스크 패턴, 박막 트랜지스터의 제조 방법 및 이를사용하는 유기 전계 발광 표시 장치의 제조 방법
KR100796590B1 (ko) 다결정 실리콘 박막의 제조 방법, 이에 사용되는 마스크패턴 및 이를 사용하는 평판 표시 장치의 제조 방법
CN110211968A (zh) 一种显示基板及其制作方法、显示装置
CN100364053C (zh) 利用激光辐照装置制造薄膜晶体管及多晶化的方法
CN206210847U (zh) 一种适于封装的基板膜层及一种oled器件封装结构
JP2005123573A (ja) 多結晶シリコン薄膜の製造方法及びこれを使用して製造されたディスプレーデバイス
KR20060010560A (ko) 다결정 규소용 마스크 및 이의 제조방법과, 이를 이용한박막트랜지스터의 제조방법
CN107430990A (zh) 薄膜晶体管基板、显示面板以及激光退火方法
KR101912760B1 (ko) 박막 트랜지스터 및 이의 제작 방법, 어레이 기판 및 디스플레이 장치
US20190096918A1 (en) An array substrate, mask plate and array substrate manufacturing method
US10923505B2 (en) Method for fabricating a display substrate by generating heat with a light shielding layer for crystallization of a semiconductor layer
KR100803867B1 (ko) 비정질 실리콘층의 결정화 방법 및 이를 이용한 박막트랜지스터의 제조방법
JP4278013B2 (ja) 薄膜素子の製造方法
KR101100875B1 (ko) 결정화용 레이저빔 조사 장치, 이를 이용한 결정화 방법및 이를 포함하는 박막 트랜지스터 표시판의 제조 방법
CN102646602A (zh) 多晶薄膜制备方法、多晶薄膜及由其制备的薄膜晶体管
JPH11330481A (ja) 薄膜トランジスタ及び液晶表示装置

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20150909

RJ01 Rejection of invention patent application after publication