WO2018192009A1 - 一种制作低温多晶硅薄膜晶体管的方法 - Google Patents

一种制作低温多晶硅薄膜晶体管的方法 Download PDF

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WO2018192009A1
WO2018192009A1 PCT/CN2017/083060 CN2017083060W WO2018192009A1 WO 2018192009 A1 WO2018192009 A1 WO 2018192009A1 CN 2017083060 W CN2017083060 W CN 2017083060W WO 2018192009 A1 WO2018192009 A1 WO 2018192009A1
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layer
forming
source
contact layer
depositing
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李松杉
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武汉华星光电技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02669—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using crystallisation inhibiting elements
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Definitions

  • the present invention relates to the field of display panel technologies, and in particular, to a method for fabricating a low temperature polysilicon thin film transistor.
  • a thin film transistor that drives a display device by applying a driving voltage
  • the active layer of the TFT has been used for stability and processing to a good amorphous silicon (a-Si) material, but the carrier mobility of the a-Si material is low, which cannot satisfy the large-size, high-resolution display device.
  • the requirements in particular, cannot meet the requirements of next-generation active matrix organic light-emitting display devices.
  • Low Temperature Poly-silicon can produce high-density pixels and can be applied due to high electron mobility, good subthreshold swing, large switching current ratio, and low power consumption.
  • OLED organic light emitting diode
  • LTPS-PTFT low temperature polysilicon thin film transistor
  • the production process is complicated and the production cost is high. Therefore, how to reduce the manufacturing process of the low-temperature polysilicon thin film transistor and reduce the manufacturing cost has become an urgent problem to be solved.
  • the present invention proposes a method for fabricating a low-temperature polysilicon thin film transistor.
  • S11 a process of forming a gate layer on a base substrate
  • the process of forming the source/drain contact layer comprises: forming a channel protective layer, and depositing an ohmic contact layer by plasma enhanced chemical vapor deposition, wherein the reactive gas used comprises diborane, and then The ohmic contact layer is patterned to form the source and drain contact layers.
  • the source-drain contact layer is formed by the above method. Since the reaction gas used contains diborane, boron ions enter the ohmic contact layer during the deposition of the ohmic contact layer by plasma enhanced chemical vapor deposition (PECVD).
  • PECVD plasma enhanced chemical vapor deposition
  • the source and drain contact layers are formed to contain boron ions, thereby reducing the impedance of the source and drain contact layers and reducing the contact resistance with the source and drain electrodes.
  • This method eliminates the need to use a mask to define the boron ion implantation region, while eliminating the boron ion implantation process, simplifying the process flow and reducing manufacturing costs.
  • the reaction gas further includes silane and hydrogen.
  • the reaction gas is a mixed gas of silane, hydrogen, and diborane.
  • the material used to deposit the ohmic contact layer includes P+a-Si.
  • the process of forming the channel protective layer includes: depositing an etch barrier layer on the active layer, and then sequentially performing a heating hydrogenation process and a patterning process on the etch stop layer to form the Channel protection layer.
  • the etch barrier layer comprises at least one of a silicon oxide layer or a silicon nitride layer.
  • the etch stop layer may be a silicon oxide layer or a silicon nitride layer, or may be a superposed layer of a silicon oxide layer and a silicon nitride layer.
  • the process of forming the active layer includes: depositing a gate insulating layer on the entire surface of the base substrate, then depositing an amorphous silicon layer, and transforming the amorphous silicon layer by an excimer laser annealing process As a polysilicon layer, the polysilicon layer is patterned to form the active layer.
  • the polysilicon layer and ion activation are realized by an excimer laser annealing process, which avoids the problem that the substrate substrate as a whole is affected by heat by the thermal annealing process, which is beneficial to the flexible display.
  • the local high temperature of the excimer laser annealing process can also improve the lattice integrity of the polysilicon, thereby improving the performance of the TFT.
  • the process of forming the gate layer includes depositing a first metal layer on a full surface of the base substrate, and patterning the first metal layer to form the gate layer. Further, a buffer layer is formed on the entire surface of the base substrate before depositing the first metal layer.
  • the buffer layer includes at least one of a silicon nitride layer or a silicon oxide layer.
  • the buffer layer can increase the degree of adhesion between the gate layer and the substrate. At the same time, it is also possible to prevent metal ions in the base substrate from diffusing to the gate layer, thereby reducing generation of leakage current.
  • the material of the gate layer includes at least one of molybdenum, niobium, aluminum, and tungsten. These metals are commonly used in the fabrication of TFTs and are easy to use.
  • the process of forming the source-drain electrode layer includes depositing a second metal layer, and patterning the second metal layer to form the source-drain electrode layer.
  • the metal forming the second metal layer includes at least one of molybdenum and aluminum.
  • the invention also proposes a low temperature polysilicon thin film transistor which is fabricated by the above method.
  • the method for fabricating a low-temperature polysilicon thin film transistor according to the present invention deposits an ohmic contact layer by PECVD in the process of forming a source-drain contact layer, and the reaction gas used therein contains diborane. .
  • the reaction gas used therein contains diborane.
  • boron ions enter therein, thereby reducing the impedance of the source/drain contact layer and reducing the contact resistance with the source and drain.
  • the method of forming the source-drain contact layer eliminates the need to define a boron ion implantation region by using a mask, and eliminates the boron ion implantation process, which simplifies the process flow and reduces the manufacturing cost.
  • the low temperature polysilicon thin film transistor proposed by the present invention is produced by the method proposed by the present invention, thereby reducing the manufacturing cost.
  • FIG. 1 is a schematic view showing a method of fabricating a low temperature polysilicon thin film transistor of the present invention
  • FIG. 2 is a schematic structural view of forming a gate layer
  • FIG. 3 is a schematic structural view after forming an active layer
  • FIG. 4 is a schematic structural view of a source/drain contact layer
  • FIG. 5 is a schematic structural view of a source/drain electrode layer
  • FIG. 6 is a schematic view showing the structure of an array substrate including the low temperature polysilicon thin film transistor of the present invention.
  • FIG. 1 shows a method of fabricating a low temperature polysilicon thin film transistor in the embodiment, which mainly includes the following steps:
  • S11 a process of forming a gate layer on a base substrate
  • S14 a process of forming a source-drain electrode layer.
  • S11 a process of forming a gate layer on a base substrate.
  • a buffer layer 112 is formed on the entire surface of the base substrate 111, and the buffer layer 112 includes a silicon nitride layer 1121 and a silicon oxide layer 1122.
  • the buffer layer 112 may also include only the silicon nitride layer 1121 or the silicon oxide layer 1122.
  • a first metal layer is deposited on the buffer layer 112, and preferably, the material constituting the first metal layer is molybdenum.
  • the material of the first metal layer may be at least one of molybdenum, niobium, aluminum, and tungsten.
  • the first metal layer is patterned by photolithography to form a gate layer 113.
  • the buffer layer 112 can increase the degree of adhesion between the gate layer 113 and the base substrate 111, and at the same time, can prevent metal ions in the base substrate 111 from diffusing to the gate layer 113, thereby reducing generation of leakage current.
  • the process of forming the buffer layer is not included in the process of forming the gate layer 113.
  • S12 a process of forming an active layer.
  • a gate insulating layer 121 is deposited over the gate layer 113.
  • the material of the gate insulating layer 121 is silicon oxide.
  • an amorphous silicon layer is deposited over the gate insulating layer 121, and the amorphous silicon layer is processed by an excimer laser annealing process to be converted into a polysilicon layer. Then, the polysilicon layer is patterned to form the active layer 122.
  • the polysilicon layer is realized by the excimer laser annealing process, which avoids the problem that the whole substrate substrate is affected by the thermal display by the thermal annealing process, and is beneficial to realize the flexible display.
  • the local high temperature of the excimer laser annealing process can also improve the lattice integrity of the polysilicon, thereby improving the performance of the TFT.
  • the active layer 122 on the base substrate 111 The upper full surface deposition etch stop layer, preferably the etch stop layer comprises a silicon oxide layer and a silicon nitride layer. In other embodiments, the etch stop layer may also include only a silicon oxide layer or a silicon nitride layer.
  • the etch stop layer is subjected to a heat hydrogenation treatment and patterned by a photolithography technique to form a channel protective layer 131. Since the etch barrier layer in this embodiment includes a silicon oxide layer and a silicon nitride layer, the channel protective layer 131 herein includes a first channel protective layer 1311 and a second channel protective layer 1312.
  • An ohmic contact layer is deposited by a PECVD method over the channel protective layer 131 using a reaction gas containing diborane.
  • the material of the ohmic contact layer is preferably P+a-Si, and the reaction gas is preferably a mixed gas of silane, hydrogen and diborane.
  • the ohmic contact layer is also patterned by photolithography to form a source/drain contact layer 132.
  • the reaction gas used contains diborane
  • boron ions enter the ohmic contact layer, so that the formed source and drain contact layer 132 contains boron ions, thereby reducing the source.
  • the impedance of the drain contact layer 132 is such that the contact impedance with the source and drain is reduced. This method eliminates the need to use a mask to define the boron ion implantation region, while eliminating the boron ion implantation process, simplifying the process flow and reducing manufacturing costs.
  • the thin film transistor fabricated is P-type.
  • the material of the ohmic contact layer may also be N+a-Si, and the thin film transistor fabricated at this time is N-type.
  • S14 a process of forming a source-drain electrode layer.
  • a second metal layer is deposited over the source and drain contact layer 132.
  • the material of the second metal layer includes at least one of molybdenum and aluminum.
  • the second metal layer is patterned by photolithography to form a source/drain electrode layer 141.
  • the low temperature polysilicon thin film transistor proposed by the present invention is fabricated by the above method.
  • Embodiment 2 is a diagrammatic representation of Embodiment 1:
  • the step S15 is included. As shown in FIG. 6, an organic photoresist flat insulating layer 151 is formed over the source/drain electrode layer 141, and then an Anode electrode layer 152 is formed. A pixel definition layer (PDL) and a spacer (PS) layer are then fabricated.
  • PDL pixel definition layer
  • PS spacer

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Abstract

一种制作低温多晶硅薄膜晶体管的方法，包括：依次在衬底基板（111）上形成栅极层（113）、有源层（122）、源漏极接触层（132）和源漏电极（141）。形成源漏极接触层（132）的过程包括：形成沟道保护层（131）；使用包含乙硼烷的反应气体，通过等离子体增强化学气相沉积的方法沉积欧姆接触层，并对其进行构图，形成源漏极接触层（132）。在沉积欧姆接触层的过程中，硼离子会进入源漏极接触层中。此种方法不再需要采用掩膜定义硼离子植入区域，省去了硼离子植入的过程，简化了工艺流程，降低了制造成本。

Description

一种制作低温多晶硅薄膜晶体管的方法
相关申请的交叉引用
本申请要求享有于2017年4月17日提交的名称为“一种制作低温多晶硅薄膜晶体管的方法”的中国专利申请CN201710249455.0的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本发明涉及显示面板技术领域，尤其涉及一种制作低温多晶硅薄膜晶体管的方法。
背景技术
在各种显示装置的像素单元中，通过施加驱动电压来驱动显示装置的薄膜晶体管(Thin Film Transistor，TFT)被大量应用。在TFT的有源层一直使用稳定性和加工向较好的非晶硅(a-Si)材料，但是a-Si材料的载流子迁移率较低，不能满足大尺寸、高分辨率显示器件的要求，特别是不能满足下一代有源矩阵式有机发光显示器件的要求。
与非晶硅相比，低温多晶硅(Low Temperature Poly-silicon，LTPS)由于电子迁移率高、亚阈值摆幅好、开关态电流比大、耗电低，同时可以制作高密度像素，且可以应用在柔性有机发光二极管(OLED)基板上等特点，近几年引起了广泛的关注。但是，在制作低温多晶硅薄膜晶体管(LTPS-PTFT)的过程中，需要用掩膜定义源漏极接触区域，然后利用离子植入机植入硼，再进行高温快速退火活化后形成源漏极接触区，其制作工艺流程复杂、制作成本高。因此，如何减少低温多晶硅薄膜晶体管的制作工艺流程并降低制作成本成为亟待解决的问题。
发明内容
针对现有技术中的如何减少低温多晶硅薄膜晶体管的制作工艺流程并降低其制作成本的问题，本发明提出了一种制作低温多晶硅薄膜晶体管的方法。
本发明提出的制作低温多晶硅薄膜晶体管的方法，其中，所述方法包括以下步骤：
S11：在衬底基板上形成栅极层的过程；
S12：形成有源层的过程；
S13：形成源漏极接触层的过程；
S14：形成源漏电极的过程，
其中，形成所述源漏极接触层的过程包括：形成沟道保护层，并通过等离子体增强化学气相沉积的方法沉积欧姆接触层，其中使用的反应气体包含乙硼烷，然后，对所述欧姆接触层进行图形化处理，形成所述源漏极接触层。
采用上述方法形成源漏极接触层，由于使用的反应气体中包含有乙硼烷，在采用等离子体增强化学气相沉积(PECVD)的方法沉积欧姆接触层的过程中，硼离子会进入欧姆接触层中，使得形成的源漏极接触层中包含有硼离子，从而降低了源漏极接触层的阻抗，使之与源漏极的接触阻抗减小。此种方法不再需要采用掩膜定义硼离子植入区域，同时省去了硼离子植入的过程，简化了工艺流程，降低了制造成本。
作为对本发明的进一步改进，所述反应气体还包括硅烷和氢气。此时，反应气体为硅烷、氢气和乙硼烷的混合气体。
进一步，沉积所述欧姆接触层使用的材料包括P+a-Si。
作为对本发明的进一步改进，形成所述沟道保护层的过程包括：在所述有源层上沉积蚀刻阻挡层，然后对所述蚀刻阻挡层依次进行加热氢化处理和图形化处理，形成所述沟道保护层。
进一步，所述蚀刻阻挡层包括氧化硅层或氮化硅层中的至少一种。蚀刻阻挡层可以为氧化硅层或氮化硅层，也可以为氧化硅层和氮化硅层的叠加层。
作为对本发明的进一步改进，形成所述有源层的过程包括：在衬底基板全表面沉积栅极绝缘层，然后沉积非晶硅层，通过准分子激光退火工艺使所述非晶硅层转变为多晶硅层，对所述多晶硅层进行图形化处理，形成所述有源层。
通过准分子激光退火工艺实现多晶硅层和离子激活，避免了采用热退火工艺导致的衬底基板整体受热影响柔性显示装置的问题，有利于实现柔性显示。此外，准分子激光退火工艺的局部高温还可以提高多晶硅的晶格完整性，从而提高了TFT的性能。
作为对本发明的进一步改进，形成所述栅极层的过程包括：在衬底基板全表面沉积第一金属层，对所述第一金属层进行图形化处理，形成所述栅极层。进一步，在沉积所述第一金属层之前，在衬底基板全表面制作缓冲层。所述缓冲层包括氮化硅层或氧化硅层中的至少一种。
缓冲层可以提高栅极层与衬底基板之间的附着程度。同时，还可以防止衬底基板中的金属离子扩散至栅极层，减少漏电流的产生。
作为对栅极层的进一步改进，所述栅极层的材料包括钼、钽、铝、钨中的至少一种。这些金属均为TFT制作过程中常用的金属材料，方便使用。
作为对本发明的进一步改进，形成源漏电极层的过程包括沉积第二金属层，对所述第二金属层进行图形化处理，形成所述源漏电极层。形成第二金属层的金属包括钼、铝中的至少一种。
本发明同时提出了一种低温多晶硅薄膜晶体管，该低温多晶硅薄膜晶体管采用上述方法制作而成。
综上所述，本发明提出的制作低温多晶硅薄膜晶体管的方法，在形成源漏极接触层的过程中，采用PECVD的方法沉积一层欧姆接触层，同时使用的反应气体中包含有乙硼烷。从而，在沉积欧姆接触层的过程中，硼离子会进入其中，从而降低了源漏极接触层的阻抗，使之与源漏极的接触阻抗减小。这种形成源漏极接触层的方法，不再需要采用掩膜定义硼离子植入区域，同时省去了硼离子植入的过程，简化了工艺流程，降低了制造成本。本发明提出的低温多晶硅薄膜晶体管由于采用本发明提出的方法制成，从而降低了制造成本。
附图说明
在下文中将基于实施例并参考附图来对本发明进行更详细的描述。其中：
图1为本发明的制作低温多晶硅薄膜晶体管的方法示意图；
图2为形成栅极层的结构示意图；
图3为形成有源层后的结构示意图；
图4为形成源漏极接触层后的结构示意图；
图5为形成源漏电极层后的结构示意图；
图6为包含有本发明的低温多晶硅薄膜晶体管的阵列基板的结构示意图。
在附图中，相同的部件使用相同的附图标记。附图并未按照实际的比例。
具体实施方式
以下将结合附图对本发明的内容作出详细的说明，下文中的“上”“下”“左”“右”均为相对于图示方向，不应理解为对本发明的限制。
图1示出了本实施例中的制作低温多晶硅薄膜晶体管的方法，主要包括以下步骤：
S11：在衬底基板上形成栅极层的过程；
S12：形成有源层的过程；
S13：形成源漏极接触层的过程；
S14：形成源漏电极层的过程。
下面将对各个过程进行更加详细的说明。
S11：在衬底基板上形成栅极层的过程。如图2所示，首先，在衬底基板111的全表面上制作缓冲层112，缓冲层112包括氮化硅层1121和氧化硅层1122。当然，在其他实施例中，缓冲层112也可以只包括氮化硅层1121或氧化硅层1122。然后，在缓冲层112上沉积第一金属层，优选地，构成该第一金属层的材料为钼。在其他实施例中，该第一金属层的材料可以为钼、钽、铝、钨中的至少一种。采用照相蚀刻技术对第一金属层进行构图，形成栅极层113。
缓冲层112能够提高栅极层113与衬底基板111之间的附着程度，同时，还可以防止衬底基板111中的金属离子扩散至栅极层113，减少漏电流的产生。
当然，在其他实施例中，在形成栅极层113的过程中，不含有形成缓冲层的过程。
S12：形成有源层的过程。如图3所示，在栅极层113的上方沉积栅极绝缘层121，优选地，栅极绝缘层121的材料为氧化硅。接着，在栅极绝缘层121上方沉积非晶硅层，采用准分子激光退火工艺对非晶硅层进行处理，使之转变为多晶硅层。然后，对多晶硅层进行构图，形成有源层122。
在此过程中，通过准分子激光退火工艺实现多晶硅层，避免了采用热退火工艺导致的衬底基板整体受热影响柔性显示的问题，有利于实现柔性显示。此外，准分子激光退火工艺的局部高温还可以提高多晶硅的晶格完整性，从而提高了TFT的性能。
S13：形成源漏极接触层的过程。如图4所示，在衬底基板111的有源层122 上方的全表面沉积蚀刻阻挡层，优选地，该蚀刻阻挡层包括氧化硅层和氮化硅层。在其他实施例中，蚀刻阻挡层也可仅包括氧化硅层或氮化硅层。对蚀刻阻挡层进行加热氢化处理，并采用照相蚀刻技术对其进行构图，形成沟道保护层131。由于该实施例中的蚀刻阻挡层包括氧化硅层和氮化硅层，所以，这里的沟道保护层131包括第一沟道保护层1311和第二沟道保护层1312。
在沟道保护层131上方，使用包含乙硼烷的反应气体，通过PECVD的方法沉积欧姆接触层。该欧姆接触层的材料优选为P+a-Si，反应气体优选为为硅烷、氢气和乙硼烷的混合气体。在这里，同样采用照相蚀刻技术对该欧姆接触层进行构图，形成源漏极接触层132。当使用的反应气体包含乙硼烷时，在采用PECVD的方法沉积欧姆接触层中，硼离子会进入欧姆接触层中，使得形成的源漏极接触层132中包含有硼离子，从而降低了源漏极接触层132的阻抗，使之与源漏极的接触阻抗减小。此种方法不再需要采用掩膜定义硼离子植入区域，同时省去了硼离子植入的过程，简化了工艺流程，降低了制造成本。
当欧姆接触层的材料为P+a-Si时，制作出的薄膜晶体管为P型。当然，欧姆接触层的材料也可以为N+a-Si，此时制作出的薄膜晶体管为N型。
S14：形成源漏电极层的过程。如图5所示，在源漏极接触层132的上方，沉积第二金属层，优选地，该第二金属层的材料包括钼、铝中的至少一种。采用照相蚀刻技术对第二金属层进行构图，形成源漏电极层141。
本发明提出的低温多晶硅薄膜晶体管，采用上述方法制作而成。
实施例二：
在制作包含有以上述方法制作的低温多晶硅薄膜晶体管的阵列基板时，除了包括实施例一总的制作步骤外，还包括步骤S15。如图6所示，在源漏电极层141上方制作有机光阻平坦绝缘层151，接着制作Anode电极层152。然后制作像素定义层(PDL)和隔离柱(PS)层。
最后说明的是，以上实施例仅用于说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换。尤其是，只要不存在结构上的冲突，各实施例中的特征均可相互结合起来，所形成的组合式特征仍属于本发明的范围内。只要不脱离本发明技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (15)

  1. 一种制作低温多晶硅薄膜晶体管的方法，其中，所述方法包括以下步骤：
    S11：在衬底基板上形成栅极层的过程；
    S12：形成有源层的过程；
    S13：形成源漏极接触层的过程；
    S14：形成源漏电极层的过程，
    其中，形成所述源漏极接触层的过程包括：
    形成沟道保护层，并通过等离子体增强化学气相沉积的方法沉积欧姆接触层，其中使用的反应气体包含乙硼烷，然后，对所述欧姆接触层进行图形化处理，形成所述源漏极接触层。
  2. 根据权利要求1所述的方法，其中，所述反应气体还包括硅烷和氢气。
  3. 根据权利要求1所述的方法，其中，沉积所述欧姆接触层使用的材料包括P+a-Si。
  4. 根据权利要求2所述的方法，其中，沉积所述欧姆接触层使用的材料包括P+a-Si。
  5. 根据权利要求1所述的方法，其中，形成所述沟道保护层的过程包括：在所述有源层上沉积蚀刻阻挡层，然后对所述蚀刻阻挡层依次进行加热氢化处理和图形化处理，形成所述沟道保护层。
  6. 根据权利要求2所述的方法，其中，形成所述沟道保护层的过程包括：在所述有源层上沉积蚀刻阻挡层，然后对所述蚀刻阻挡层依次进行加热氢化处理和图形化处理，形成所述沟道保护层。
  7. 根据权利要求5所述的方法，其中，所述蚀刻阻挡层包括氧化硅层或氮化硅层中的至少一种。
  8. 根据权利要求6所述的方法，其中，所述蚀刻阻挡层包括氧化硅层或氮化硅层中的至少一种。
  9. 根据权利要求1所述的方法，其中，形成所述有源层的过程包括：在衬底基板全表面沉积栅极绝缘层，然后沉积非晶硅层，通过准分子激光退火工艺使所述非晶硅层转变为多晶硅层，对所述多晶硅层进行图形化处理，形成所述有源层。
  10. 根据权利要求1所述的方法，其中，形成所述栅极层的过程包括：在衬 底基板全表面沉积第一金属层，对所述第一金属层进行图形化处理，形成所述栅极层。
  11. 根据权利要求10所述的方法，其中，在沉积所述第一金属层之前，在衬底基板全表面制作缓冲层。
  12. 根据权利要求11所述的方法，其中，所述缓冲层包括氮化硅层或氧化硅层中的至少一种。
  13. 根据权利要求10所述的方法，其中，所述栅极层的材料包括钼、钽、铝、钨中的至少一种。
  14. 根据权利要求11所述的方法，其中，所述栅极层的材料包括钼、钽、铝、钨中的至少一种。
  15. 根据权利要求12所述的方法，其中，所述栅极层的材料包括钼、钽、铝、钨中的至少一种。
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