WO2019001115A1 - 薄膜晶体管及其制作方法、阵列基板及显示装置 - Google Patents

薄膜晶体管及其制作方法、阵列基板及显示装置 Download PDF

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WO2019001115A1
WO2019001115A1 PCT/CN2018/083984 CN2018083984W WO2019001115A1 WO 2019001115 A1 WO2019001115 A1 WO 2019001115A1 CN 2018083984 W CN2018083984 W CN 2018083984W WO 2019001115 A1 WO2019001115 A1 WO 2019001115A1
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film transistor
thin film
layer
substrate
doped
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PCT/CN2018/083984
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French (fr)
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王利忠
周天民
温钰
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京东方科技集团股份有限公司
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Priority to US16/615,358 priority Critical patent/US11217697B2/en
Publication of WO2019001115A1 publication Critical patent/WO2019001115A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table further characterised by the doping material
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the present disclosure relates to the field of thin film transistor fabrication processes and display technologies, and in particular, to a thin film transistor and a method for fabricating the same, an array substrate, and a display device.
  • the low temperature poly-silicon thin film transistor Because of its high reaction speed, high aperture ratio, high brightness, etc., it is increasingly favored by the market, and it can also be applied to flexible display fields and organic light emitting diode displays.
  • the low-temperature polysilicon film generally exhibits a high value due to a large number of defects in the film, which limits the application of the low-temperature polysilicon film in the display field.
  • a technical solution adopted to solve the technical problem of the present invention is to provide a thin film transistor, an active layer of the thin film transistor including a channel region, a source region, and a drain region, the source region and the drain region Provided on both sides of the channel region, the channel region includes polysilicon doped with a Group 5 element.
  • the fifth group element has a doping concentration of 1E11 to 1E12.
  • the Group 5 element is phosphorus or arsenic.
  • the thin film transistor is an N-type thin film transistor.
  • the source region and the drain region are polysilicon doped with boron ions, and the doping concentration of the boron ions is 1E15 to 5E15.
  • the thin film transistor further includes: a substrate, a buffer layer, and a gate insulating layer, wherein the buffer layer is located on one side of the substrate, and the active layer is sequentially stacked on a side of the buffer layer away from the substrate, a gate insulating layer, a gate, the gate corresponding to a location of the channel region.
  • the substrate includes a base substrate and a polyimide resin formed over the base substrate, the base substrate being a glass substrate or a flexible substrate.
  • the buffer layer is a two-layer structure.
  • the buffer layer includes a SiN layer and a SiO 2 layer formed over the SiN layer.
  • the present disclosure also provides a method for fabricating a thin film transistor, comprising the following steps:
  • the active layer includes a channel region, the channel region being polysilicon doped with a Group 5 element.
  • the step of forming an active layer of the thin film transistor includes: forming a fifth silicon-doped amorphous silicon layer by a film forming process, and crystallizing the amorphous silicon, A polysilicon layer doped with a Group 5 element is formed.
  • the reaction gas used in the step of forming the amorphous silicon layer doped with the fifth group element is H2, PH3, and SiH4, and the gas ratio is 1:0.15 to 0.35:0.1 to 0.3, and the reaction temperature is Between 250 ° C ⁇ 450 ° C.
  • the step of forming an active layer of the thin film transistor includes: forming a polysilicon layer by a film forming process, and ion doping the polysilicon layer, the ion being an ion of a fifth group element, Thereby, a polysilicon layer doped with a Group 5 element is formed.
  • the active layer is doped with boron ions to form a source region and a drain region of the active layer, and the doping concentration of the boron ions is 1E15 to 5E15.
  • the present disclosure also provides an array substrate comprising the thin film transistor of any of the above aspects.
  • the present disclosure also provides a display device including the above array substrate.
  • FIG. 1 is a partial schematic structural view of a thin film transistor provided by the present disclosure.
  • FIG. 2 is a schematic flow chart of a method for fabricating a thin film transistor according to the present disclosure.
  • FIG. 3 is a schematic view showing the overall structure of a thin film transistor provided by the present disclosure.
  • FIG. 4 is a schematic structural view of an array substrate provided by the present disclosure.
  • the present disclosure provides a thin film transistor and a method of fabricating the same, an array substrate, and a display device to increase a PN junction potential difference by ion doping, thereby reducing an off-state current.
  • FIG. 1 A schematic diagram of a partial structure of a thin film transistor provided by the present disclosure is shown in FIG. 1.
  • the active layer of the thin film transistor includes a channel region 40, a source region 31 and a drain region 30, and the source region 31 and the drain region.
  • a polar region of 30 decibels is disposed on both sides of the channel region 40, and the channel region 40 includes polysilicon doped with a Group 5 element.
  • the doping concentration of the fifth group element is 1E11 to 1E12.
  • a Group V element is added to the channel region to form an N-type thin film transistor, wherein the Group 5 element is preferably phosphorus or arsenic.
  • This embodiment illustrates the present disclosure by taking phosphorus as an example.
  • the present disclosure sets the doping concentration of phosphorus ions (P+) to 1E11 to 1E12, and the doping concentration may be 3E11, 7E11, 9E11, etc., since the P ions are Donor impurity, providing electron carriers, increasing the doping concentration of P ions, that is, increasing the concentration of electrons in the channel region and lowering the potential of the channel region, in which the channel potential increases with the doping concentration. Decreasing, increasing the potential difference between the channel region and the source and drain regions.
  • the thin film transistor further includes: a substrate 60, a buffer layer 50, and a gate insulating layer 20, the buffer layer is on one side of the substrate, the source region 31, the drain region 30, and the trench
  • An active layer formed by the track region 40 is formed on a side of the buffer layer away from the substrate, the gate insulating layer is formed on a side of the active layer away from the substrate, and the gate is formed on the gate insulating layer away from One side of the substrate and corresponding to the location of the channel region.
  • the substrate includes a base substrate and a polyimide resin (PI) formed on the base substrate, the substrate material being not limited, and may be glass, quartz or a flexible substrate.
  • PI polyimide resin
  • the buffer layer includes a two-layer structure, a SiN layer 502 in direct contact with the buffer layer, and an SiO 2 layer 501 formed on the SiN layer.
  • the SiN layer directly in contact with the PI has a thickness of 30 to 100 nm, and the SiO 2 layer has a thickness of 20 to 40 nm.
  • the buffer layer of appropriate thickness can effectively block the diffusion effect of metal ions caused by the subsequent high temperature process.
  • the SiN layer with a thickness of about 50 nm has a significant effect on blocking the contaminants from the glass substrate, and the polysilicon can be improved by adjusting the thickness of the buffer layer or the deposition conditions.
  • the quality of the back interface prevents the formation of leakage at the backside of the polysilicon.
  • the double buffer layer reduces heat transfer and slows down the rate at which the laser heated by the laser cools, helping to form larger crystalline grains.
  • the source region and the drain region of the thin film transistor are polysilicon doped with boron ions (B+), and the doping concentration of the boron ions (B+) in the drain region of the source region provided by the present disclosure is 1E15 to 5E15. . Adding the concentration of boron ions increases the concentration of hole carriers in the source and drain regions, thereby increasing the potential of the source region and the drain region, increasing the potential barrier between the source and drain regions and the channel region, and reducing The leakage current generated between the two.
  • the present disclosure also provides a method of fabricating a thin film transistor including forming an active layer of the thin film transistor; the active layer includes a channel region, and the channel region is polysilicon doped with a fifth group element.
  • the step of forming an active layer of the thin film transistor includes: forming an amorphous silicon layer doped with a fifth group element by a film forming process, and crystallizing the amorphous silicon to form a doped fifth group element Polysilicon layer.
  • the present disclosure provides a schematic flowchart of a method for fabricating a thin film transistor, the method comprising:
  • the base substrate may be a glass, quartz or plastic flexible substrate.
  • the substrate is first pre-cleaned.
  • a buffer layer is deposited on the substrate by a vapor deposition method, the buffer layer comprising two layers, wherein a SiN layer of 30-100 nm thickness is in contact with the PI, and then deposited on the SiN by vapor deposition. 40 nm thick SiO 2 layer.
  • Depositing a buffer layer on the substrate can improve the degree of adhesion between the amorphous silicon to be formed and the substrate on the one hand, and prevent metal ions in the deposition substrate from diffusing to the source region and the drain region, and reduce the defect center. Reduce the generation of leakage current, thereby reducing the off-state current.
  • the phosphorus in the fifth group element is taken as an example to illustrate the solution of the present disclosure.
  • an amorphous silicon layer doped with phosphorus ions (P+) is formed on the buffer layer by vapor deposition, and then the amorphous silicon layer is formed.
  • a crystallization process is performed to form a polysilicon layer doped with phosphorus ions (P+).
  • the source region and the drain region of the active layer may also be formed by depositing a channel region.
  • the vapor deposition method Compared with other deposition methods, the vapor deposition method has a simple process flow and greatly improved material utilization.
  • the reaction apparatus using a vapor deposition method the reaction gases are H 2 , PH 3 and SiH 4 , the gas ratio is 1:0.15 to 0.35:0.1 to 0.3, and the reaction temperature is between 250 ° C and 450 ° C to deposit the above.
  • the buffered substrate is placed in the reaction chamber, and the reaction chamber may be a furnace tube reaction chamber or a single wafer reaction furnace, and a reaction gas is introduced into the reaction chamber to perform a vapor deposition process step to form an N-type doped amorphous silicon.
  • Membrane layer the reaction gases are H 2 , PH 3 and SiH 4 , the gas ratio is 1:0.15 to 0.35:0.1 to 0.3, and the reaction temperature is between 250 ° C and 450 ° C to deposit the above.
  • the buffered substrate is placed in the reaction chamber, and the reaction chamber may be a furnace tube reaction chamber or a single wafer reaction furnace, and a reaction gas is introduced into the reaction chamber to perform a vapor deposition process step to
  • the vapor deposition method is to ionize a reaction gas by means of microwave or radio frequency or the like to form a plasma locally, and the plasma chemical activity is strong, and a reaction easily occurs, and an amorphous silicon film is deposited on the substrate.
  • the activity of the plasma is utilized to promote the reaction, and therefore, the chemical reaction can be carried out at a lower temperature.
  • the vapor deposition method has the advantages of high deposition rate, good film formation quality, less vacuum, and avoiding ionic contamination caused by high temperature.
  • P ions are doped to form an N-type channel.
  • the present disclosure is doped with phosphorus ions in polysilicon. Since P ions are donor impurities, electron carriers are provided to improve the doping of P ions.
  • the concentration, that is, the concentration of electrons in the channel region is increased, the potential in the channel region is lowered, and the potential difference of the PN junction is increased.
  • the doping of P in the process of depositing the amorphous silicon layer is uniform, the fabrication process is simple, the related defects and undesirable phenomena of the thin film transistor caused by ion implantation are avoided, and the performance of the thin film transistor is improved.
  • an amorphous silicon layer is deposited on the buffer layer by a vapor deposition method, and the reactive gas of the amorphous silicon is SiH 4 and H 2 , and the amorphous silicon layer is crystallized.
  • the amorphous silicon film layer is subjected to a thermal annealing process, that is, an excimer laser annealing process is performed to form a polysilicon layer.
  • a thermal annealing process that is, an excimer laser annealing process is performed to form a polysilicon layer.
  • P ion doping by means of ion implantation can accurately control the doping concentration, doping profile and doping depth of P ions, and the injection temperature is low, avoiding the adverse effects caused by high temperature processes, such as the transition of the junction. , thermal defects, deformation of silicon wafers, etc.
  • the crystallization treatment of the amorphous silicon layer is not limited to the thermal annealing process of the amorphous silicon layer, and other methods such as metal induced lateral crystallization, etc., crystallization means well known to those skilled in the art. It is also included within the scope of the present disclosure.
  • a catalyst when depositing the above amorphous silicon film layer, a catalyst may be added to accelerate the deposition speed of amorphous silicon or polycrystalline silicon, and also reduce the probability of temperature change to the polycrystalline silicon structure, such as B 2 H 6 or the like.
  • ion implantation is performed on the source region and the drain region to set the doping concentration of boron ions to 1E15 to 5E15.
  • the method further includes: forming a gate of the thin film transistor on the polysilicon layer, and performing boron on the active layer by using the gate as a mask
  • the ions are doped to form a source region and a drain region of the active layer, and the doping concentration of the boron ions is 1E15 to 5E15.
  • the doping concentration of the boron ions may be 1E15, 2E15, 3E15, 4E15, and 5E15. Since the boron ions belong to the acceptor impurity, the hole carriers are provided, which is equivalent to increasing the concentration of holes in the source region and the drain region. The potential of the source and drain regions is increased, and within this concentration range, the potential of the source and drain regions increases as the concentration of boron ions increases, the potential difference of the PN junction is increased, and the leakage current is reduced, thereby having a better Device performance.
  • the channel potential of the channel region P+ is 1E11 to 1E12
  • the doping concentration of boron ions in the source and drain regions is 5E11 to 5E12
  • the channel potential is decreased by 0.1V to 3V compared with the prior art, and the trench is increased.
  • the potential difference between the channel region and the source and drain regions reduces the leakage current and thus the off-state current.
  • the thin film transistor and the manufacturing method thereof in some embodiments of the present disclosure have the following advantages:
  • the present disclosure proposes to add a Group V element when depositing an N-type channel of a thin film transistor. Since the Group 5 element is a donor impurity, electron carriers are provided, that is, the concentration of electron carriers in the channel region is increased, thereby reducing the concentration. The potential of the channel region increases the potential difference between the source and drain regions and the channel region, and accordingly the potential barrier between the two increases, thereby reducing the leakage current of the PN junction formed between the source and drain polysilicon and the channel region. .
  • the concentration of holes in the source and drain regions is increased correspondingly, thereby increasing the potential of the source and drain regions, and increasing the potential difference between the source and drain regions and the channel region, also achieving
  • the purpose of reducing the leakage current of the PN junction is to solve the problem that the leakage current of the low-temperature polysilicon thin film transistor is relatively large, improve the electrical performance of the thin film transistor, and improve the display quality of the display device including the low-temperature polysilicon thin film transistor.
  • the present disclosure further provides an array substrate.
  • the structure of the array substrate is as shown in FIG. 4 .
  • the array substrate includes the thin film transistor, and the thin film transistor adopts the thin film transistor described in the above embodiments.
  • a channel region protective layer 41 and a gate insulating layer 20 are sequentially deposited, and a gate electrode 10 is formed on the gate insulating layer, and a gate electrode 10 is deposited thereon.
  • the interlayer insulating layer 70 and the source 310, the drain 300, the source 310 and the drain 310 are respectively connected to the source region and the drain region of the active layer through a via, and a layer is sequentially deposited on the gate.
  • the present disclosure further provides a display device, which includes the above array substrate, and the display device can be an electronic paper, a display panel, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • the display device can be an electronic paper, a display panel, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, Any product or part that has a display function, such as a navigator.
  • the array substrate and the display device are improved on the basis of the thin film transistor, the array substrate and the display device naturally inherit all the advantages of the thin film transistor.
  • the method for changing the ion doping is to dope the fifth group element in the amorphous silicon layer or directly implant the ions of the fifth group element in the polysilicon layer by ion implantation to form the fifth group element.
  • Doped N-type channel reduce the channel potential, or increase the doping concentration of boron ions by ion doping in the drain region of the source region, so as to increase the potential of the source and drain regions, both of which are
  • the potential difference between the source and drain regions and the channel region can be increased, the leakage current can be reduced, thereby reducing the off-state current and improving the pixel quality in the display device.

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Abstract

一种薄膜晶体管及其制作方法、阵列基板及显示装置，其中，薄膜晶体管的有源层包括沟道区(40)、源极区(31)和漏极区(30)，所述源极区(31)和漏极区(30)分别设置在所述沟道区(40)的两侧，所述沟道区(40)包括掺杂有第五族元素的多晶硅。通过掺杂第五族元素增大源漏区与沟道区之间的电势差，从而有效降低源漏极多晶硅与沟道区之间形成的PN结漏电流，提高晶体管的电学性能。

Description

薄膜晶体管及其制作方法、阵列基板及显示装置
本公开要求申请日为2017年6月30日、申请号为CN201710527541.3、发明创造名称为《薄膜晶体管及其制作方法、阵列基板及显示装置》的发明专利申请的优先权。
技术领域
本公开涉及薄膜晶体管制作工艺及显示技术领域，尤其涉及一种薄膜晶体管及其制作方法、阵列基板及显示装置。
背景技术
近年来，随着多晶硅薄膜晶体管(polycrystalline silion thin-film transistor)技术的不断发展，其应用也越来越广泛，尤其是其中的低温多晶硅薄膜晶体管(low temperature poly-silicon thin film transistor，简称LTPS TFT)，由于其具有较高的反应速度、高开口率、高亮度等优点，越来越受到市场的青睐，而且它还能被应用于柔性显示领域及有机发光二极管显示器上。然而，低温多晶硅膜由于在膜中大量存在缺陷因此漏电流一般显示出很高的值，限制了低温多晶硅膜在显示领域的应用。
发明内容
解决本发明技术问题所采用的一种技术方案是：提供一种薄膜晶体管，所述薄膜晶体管的有源层包括沟道区、源极区和漏极区，所述源极区和漏极区分别设置在所述沟道区的两侧，所述沟道区包括掺杂有第五族元素的多晶硅。
在一个实施例中的方式，所述第五族元素的掺杂浓度为1E11～1E12。
在一个实施例中的方式，所述第五族元素为磷或砷。
在一个实施例中的方式，所述薄膜晶体管为N型薄膜晶体管。
在一个实施例中的方式，所述源极区、漏极区为掺杂硼离子的多晶硅，所述硼离子的掺杂浓度为1E15～5E15。
在一个实施例中的方式，薄膜晶体管还包括：基板、缓冲层、栅绝缘层，所述缓冲层位于所述基板的一侧，在所述缓冲层远离基板的一侧依次层叠有源层、栅绝缘层、栅极，所述栅极对应于所述沟道区的位置。
在一个实施例中的方式，所述基板包括衬底基板和形成在衬底基板之上的聚酰亚胺树脂，该衬底基板为玻璃衬底基板或柔性衬底基板。
在一个实施例中的方式，所述缓冲层为两层结构。
在一个实施例中的方式，所述缓冲层包括SiN层及形成在该SiN层之上的SiO 2层。
相应地，本公开还提供了一种薄膜晶体管的制作方法，包括如下步骤：
形成所述薄膜晶体管的有源层；所述有源层包含沟道区，所述沟道区为掺杂有第五族元素的多晶硅。
在一个实施例中的方式，形成所述薄膜晶体管的有源层的步骤包括：通过成膜工艺形成有第五族元素掺杂的非晶硅层，对所述非晶硅进行晶化处理，形成掺杂有第五族元素的多晶硅层。
在一个实施例中的方式，形成有第五族元素掺杂的非晶硅层的步骤中采用的反应气体为H2、PH3和SiH4，气体比例为1：0.15～0.35：0.1～0.3，反应温度在250℃～450℃之间。
在一个实施例中的方式，形成所述薄膜晶体管的有源层的步骤包括：通过成膜工艺制作多晶硅层，对所述多晶硅层进行离子掺杂，所述离子为第五族元素的离子，从而形成有第五族元素掺杂的多晶硅层。
在一个实施例中的方式，形成所述掺杂有第五族元素的多晶硅层之后，还包括：在所述多晶硅层上形成所述薄膜晶体管的栅极，以所述栅极为掩膜，对有源层进行硼离子掺杂以形成所述有源层的源极区、漏极区，所述硼离子的掺杂浓度为1E15～5E15。
相应地，本公开还提供了一种阵列基板，所述阵列基板包括上述任一项方案中的薄膜晶体管。
相应地，本公开还提供了一种显示装置，所述显示装置包括上述阵列基板。
附图说明
图1为本公开提供的薄膜晶体管的局部结构示意图。
图2为本公开提供的薄膜晶体管制作方法的流程示意图。
图3示出了本公开所提供的薄膜晶体管的整体结构示意图。
图4示出了本公开所提供的阵列基板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和有点更加清楚，下面结合附图和示例性实施例对本公开作进一步地描述，显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。要说明的是，附图中相同的标号全部指的是相同的部件。此外，如果已知技术的详细描述对于示出本公开的特征是不必要的，则将其省略。
本公开提供一种薄膜晶体管及其制作方法、阵列基板及显示装置，以通过离子掺杂的方法增大PN结电势差，从而可以降低关态电流。
本公开提供的一种薄膜晶体管的局部结构示意图如图1所示，所述薄膜晶体管的有源层包括沟道区40、源极区31和漏极区30，所述源极区31和漏极区30分贝设置 在所述沟道区40的两侧，所述沟道区40包括掺杂有第五族元素的多晶硅。
其中，第五族元素的掺杂浓度为1E11～1E12。
在沟道区添加第五族元素，形成N型薄膜晶体管，其中，所述的第五族元素优选为磷或砷。
本实施例以磷为例阐述本公开方案。在沟道区掺杂磷离子形成N沟道，本公开将磷离子(P+)的掺杂浓度设定为到1E11～1E12，如掺杂浓度可以为3E11、7E11、9E11等，由于P离子是施主杂质，提供电子载流子，提高P离子的掺杂浓度，即提高了沟道区电子的浓度，降低沟道区电势，在该浓度范围内，沟道电势随着掺杂浓度的提高而降低，增大沟道区与源漏区之间的电势差。
如图3所述，所述薄膜晶体管还包括：基板60、缓冲层50、栅绝缘层20，所述缓冲层在所述基板的一侧，所述源极区31、漏极区30和沟道区40构成的有源层形成于所述缓冲层远离基板的一侧，所述栅绝缘层形成在所述有源层远离基板的一侧，所述栅极形成于所述栅绝缘层远离基板的一侧，且对应于所述沟道区的位置。
所述基板包括衬底基板和形成在衬底基板之上的聚酰亚胺树脂(PI)，该衬底基板材质不限，可以为玻璃、石英或柔性衬底基板。
所述缓冲层包括两层结构，与缓冲层直接接触的SiN层502及形成在该SiN层之上的SiO 2层501。
具体地，与PI直接接触的SiN层的厚度为30-100nm，SiO 2层的厚度为20-40nm。
适当厚度的缓冲层可以有效阻隔金属离子因后续高温工艺造成的扩散效应，如50nm左右厚度的SiN层对阻挡来自玻璃基板的污染物效果显著，通过缓冲层厚度或沉积条件的调整可以改善对多晶硅背面界面的质量，防止在多晶硅背面界面形成漏电的途径。
在晶化工艺中，上述双层缓冲层降低了热传导，并减缓被激光加热的硅冷却的速率，有助于形成较大的结晶晶粒。
所述薄膜晶体管的源极区、漏极区为掺杂硼离子(B+)的多晶硅，且本公开提供的源极区漏极区中所述硼离子(B+)的掺杂浓度为1E15～5E15。添加所述浓度的硼离子提高了源漏区空穴载流子的浓度，从而提高源极区、漏极区区域的电势，增大源漏极区与沟道区之间的势垒，降低两者之间产生的漏电流。
本公开还提供了一种薄膜晶体管的制作方法，包括形成所述薄膜晶体管的有源层；所述有源层包含沟道区，所述沟道区为掺杂有第五族元素的多晶硅。
形成所述薄膜晶体管的有源层的步骤包括：通过成膜工艺形成有第五族元素掺杂的非晶硅层，对所述非晶硅进行晶化处理，形成掺杂有第五族元素的多晶硅层。
请参见附图2所示，本公开提供了一种薄膜晶体管制作方法的流程示意图，该方法包括：
S20，在基板上沉积缓冲层；
具体地，在提供的衬底基板上，涂覆PI，形成基板。所述衬底基板可以是玻璃、石英或塑料柔性衬底。当沉积基板的洁净度不满足要求时，首先对衬底基板进行预清洗。
具体地，通过气相沉积法在上述基板上沉积缓冲层，所述缓冲层包括两层，其中与PI接触的为30-100nm厚的SiN层，然后再SiN之上同样利用气相沉积法沉积20-40nm厚的SiO 2层。
在基板上沉积缓冲层，一方面可以提高待形成的非晶硅与基板之间的附着程度，另一方面可以防止沉积基板中的金属离子扩散至源极区和漏极区，降低缺陷中心，减少漏电流的产生，从而减小关态电流。
S21，在所述缓冲层上采用气相沉积法沉积有源层的沟道区，所述沟道区为掺杂有第五族元素的多晶硅。
本实施例中，以第五族元素中的磷为例阐述本公开方案，先通过气相沉积法在缓冲层上形成掺杂有磷离子(P+)的非晶硅层，再对非晶硅层进行晶化工艺处理，形成掺杂有磷离子(P+)的多晶硅层。所述有源层的源极区和漏极区也可以通过沉积沟道区的同时形成。
利用气相沉积法，与其他沉积方法相比，工艺流程简单，材料的利用率也大大提高。
具体地，采用气相沉积法的反应设备，反应气体为H 2、PH 3和SiH 4，气体比例为1：0.15～0.35：0.1～0.3，反应温度在250℃～450℃之间，把上述沉积有缓冲层的基板放在反应室中，反应室可以是炉管式反应室或单一晶片反应炉，向反应室中通入反应气体，进行气相沉积工艺步骤，形成N型掺杂的非晶硅膜层。
具体地，气相沉积法是借助微波或射频等使反应气体电离，在局部形成等离子体，而等离子化学活性很强，很容易发生反应，在所述基底上沉积出非晶硅薄膜。利用等离子体的活性来促进反应，因此，该化学反应能在较低温度下进行。利用气相沉积法具有沉积速率快、成膜质量好、真空较少，避免高温带来的离子污染等优点。
在非晶硅膜层的沉积过程中掺杂P离子，形成N型沟道，本公开在多晶硅中掺杂磷离子，由于P离子是施主杂质，提供电子载流子，提高P离子的掺杂浓度，即提高了沟道区电子的浓度，降低沟道区电势，增大PN结电势差。
在沉积非晶硅层过程中进行P的掺杂，离子分布均匀，制作工艺简单，避免了通过离子注入引起薄膜晶体管的相关缺陷和不良现象，提高了薄膜晶体管的性能。
在另一种实施例中，通过气相沉积法在所述缓冲层上沉积非晶硅层，所述非晶硅的反应气体为SiH 4和H 2，对所述非晶硅层进行结晶化处理，如：对所述非晶硅膜层进行热退火工艺，即进行准分子激光退火工艺以形成多晶硅层。在所述多晶硅层之上沉积栅极及栅极绝缘层，在栅极绝缘层形成之后，对沟道区进行磷离子注入，形成N型掺杂的多晶硅层，其中磷离子的浓度为1E11～1E12。
利用离子注入的方式进行P离子掺杂，能够精确地控制P离子的掺杂浓度、掺杂分布及掺杂深度，而且注入温度较低，避免了高温过程带来的不利影响，如结的推移、热缺陷、硅片的变形等。
需要说明的是，对非晶硅层进行晶化处理，方法不仅限于对所述非晶硅层进行热退火工艺，其他方法如金属诱导横向晶化等，本领域技术人员所熟知的晶化手段同样包含在本公开所保护的范围之内。
进一步地，在沉积上述非晶硅膜层时，可以添加催化剂来加快非晶硅或多晶硅的沉积速度，同时也降低温度对多晶硅结构改变的概率，催化剂如B 2H 6等。
在另一种实施例中，在刻蚀形成源极区和漏极区之后，对源极区和漏极区进行离子注入，将硼离子的掺杂浓度设定为1E15～5E15。
具体的，形成所述掺杂有第五族元素的多晶硅层之后，还包括：在所述多晶硅层上形成所述薄膜晶体管的栅极，以所述栅极为掩膜，对有源层进行硼离子掺杂以形成所述有源层的源极区、漏极区，所述硼离子的掺杂浓度为1E15～5E15。
具体地，硼离子的掺杂浓度可以是1E15、2E15、3E15、4E15、5E15，由于硼离子属于受主杂质，提供空穴载流子，相当于提高源极区和漏极区中空穴的浓度，提高了源漏区的电势，且在该浓度范围内，源漏区电势随着硼离子浓度的增大而增大，增大了PN结电势差，减小了漏电流，从而具有更好的器件性能。
当沟道区P+的掺杂浓度为1E11～1E12，源漏区中硼离子的掺杂浓度为5E11～5E12时，与现有技术相比，沟道电势下降0.1V～3V，增大了沟道区与源漏区的电势差，从而降低漏电流，进而降低关态电流。
本领域技术人员应知晓，虽然上述实施例中以磷为例，但其他第五族元素仍能实现上述效果，涉及到磷之外的第五族元素，如砷、锑等，仍处于本公开所保护的范围。
与现有技术相比，本公开某些实施例中的薄膜晶体管及其制作方法具备如下优点：
本公开提出在沉积薄膜晶体管的N型沟道时添加第五族元素，由于第五族元素是施主杂质，提供电子载流子，即增加了沟道区电子载流子的浓度，从而降低了沟道区电势，增大源漏区与沟道区之间的电势差，相应地两者之间的电势势垒增大，从而降低源漏极多晶硅与沟道区之间形成的PN结漏电流。
通过上述方式，或/和在源漏区掺杂硼离子，相应增加了源漏区空穴的浓度，从而提高源漏区电势，增大源漏区与沟道区之间的电势差，同样达到降低PN结漏电流的目的，解决了低温多晶硅薄膜晶体管漏电流比较大的问题，提高薄膜晶体管的电学性能，提高包括所述低温多晶硅薄膜晶体管的显示装置的显示质量。
相应地，本公开还提供了一种阵列基板，阵列基板的结构示意图如图4所示，该阵列基板包含上述薄膜晶体管，所述薄膜晶体管采用上述实施例所述的薄膜晶体管。
如图4所示，在沉积了上述有源区的基板上，依次沉积沟道区保护层41、栅极绝缘层20，并在栅极绝缘层上形成栅极10，栅极10之上沉积层间绝缘层70及源极310、 漏极300，源极310和漏极310分别通过一过孔与所述有源层的源极区和漏极区连接，在栅极之上依次沉积层间绝缘层70(ILD层)、PLN层80及引线90。
相应地，本公开还提供了显示装置，该显示装置包括上述的阵列基板，该显示装置可以为电子纸、显示面板、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
由于所述阵列基板、显示装置是在所述薄膜晶体管的基础上进行改进的，因此，所述阵列基板及显示装置自然继承了所述薄膜晶体管的全部优点。
综上，本公开提供的通过改变离子掺杂的方法，在非晶硅层掺杂第五族元素或通过离子注入方式在多晶硅层直接注入第五族元素的离子，以形成有第五族元素掺杂的N型沟道，降低沟道电势，或者通过在源极区漏极区进行离子掺杂时，提高硼离子的掺杂浓度，以达到提高源漏极区电势，以上两种方式都能增大源漏区与沟道区之间的电势差，降低漏电流，从而降低关态电流，提高显示装置中像素质量。
虽然上面已经示出了本公开的一些示例性实施例，但是本领域的技术人员将理解，在不脱离本公开的原理或精神的情况下，可以对这些示例性实施例进行修改或等同替换，本公开的范围由权利要求及其等同物限定。

Claims (16)

  1. 一种薄膜晶体管，所述薄膜晶体管的有源层包括沟道区、源极区和漏极区，所述源极区和漏极区分别设置在所述沟道区的两侧，所述沟道区包括掺杂有第五族元素的多晶硅。
  2. 根据权利要求1所述的薄膜晶体管，其中，所述第五族元素的掺杂浓度为1E11～1E12。
  3. 根据权利要求1所述的薄膜晶体管，其中，所述第五族元素为磷或砷。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述薄膜晶体管为N型薄膜晶体管。
  5. 根据权利要求1所述的薄膜晶体管，其中，所述源极区、漏极区为掺杂硼离子的多晶硅，所述硼离子的掺杂浓度为1E15～5E15。
  6. 根据权利要求1所述的薄膜晶体管，其中，还包括：基板、缓冲层、栅绝缘层，所述缓冲层位于所述基板的一侧，在所述缓冲层远离基板的一侧依次层叠有源层、栅绝缘层、栅极，所述栅极对应于所述沟道区的位置。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述基板包括衬底基板和形成在衬底基板之上的聚酰亚胺树脂，该衬底基板为玻璃衬底基板或柔性衬底基板。
  8. 根据权利要求6所述的薄膜晶体管，其中，所述缓冲层为两层结构。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述缓冲层包括SiN层及形成在该SiN层之上的SiO 2层。
  10. 一种薄膜晶体管的制作方法，包括：
    形成所述薄膜晶体管的有源层；所述有源层包含沟道区，所述沟道区为掺杂有第五族元素的多晶硅。
  11. 根据权利要求10所述的薄膜晶体管的制作方法，其中，形成所述薄膜晶体管的有源层的步骤包括：通过成膜工艺形成有第五族元素掺杂的非晶硅层，对所述非晶硅进行晶化处理，形成掺杂有第五族元素的多晶硅层。
  12. 根据权利要求11所述的薄膜晶体管的制作方法，其中，形成有第五族元素掺杂的非晶硅层的步骤中采用的反应气体为H 2、PH 3和SiH 4，气体比例为1：0.15～0.35：0.1～0.3，反应温度在250℃～450℃之间。
  13. 根据权利要求10所述的薄膜晶体管的制作方法，其中，形成所述薄膜晶体管的有源层的步骤包括：通过成膜工艺制作多晶硅层，对所述多晶硅层进行离子掺杂，所述离子为第五族元素的离子，从而形成有第五族元素掺杂的多晶硅层。
  14. 根据权利要求10～13任一项所述的薄膜晶体管的制作方法，其中，形成所述掺杂有 第五族元素的多晶硅层之后，还包括：在所述多晶硅层上形成所述薄膜晶体管的栅极，以所述栅极为掩膜，对有源层进行硼离子掺杂以形成所述有源层的源极区、漏极区，所述硼离子的掺杂浓度为1E15～5E15。
  15. 一种阵列基板，所述阵列基板包括如权利要求1-9任一项所述的薄膜晶体管。
  16. 一种显示装置，所述显示装置包括如权利要求15所述的阵列基板。
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