CN103199116A - 悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路 - Google Patents

悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路 Download PDF

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CN103199116A
CN103199116A CN2013101081514A CN201310108151A CN103199116A CN 103199116 A CN103199116 A CN 103199116A CN 2013101081514 A CN2013101081514 A CN 2013101081514A CN 201310108151 A CN201310108151 A CN 201310108151A CN 103199116 A CN103199116 A CN 103199116A
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layer
film
polysilicon membrane
gate transistor
grid
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CN103199116B (zh
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陈宁
郭炜
王路
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201310108151.4A priority Critical patent/CN103199116B/zh
Priority to PCT/CN2013/075310 priority patent/WO2014153810A1/zh
Priority to US14/368,145 priority patent/US9620532B2/en
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Abstract

本发明涉及悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路，其中悬浮栅晶体管包括基板，设置在基板上的悬浮栅极、源极、漏极和控制栅极，还包括：所述基板上依次设有第一层绝缘薄膜、多晶硅薄膜，所述多晶硅薄膜中部形成有沟道区域，所述沟道区域的位置与所述悬浮栅极的位置相对应。本发明的有益效果是：采用本发明悬浮栅晶体管能够调节TFT阈值电压，消除了在背板生产过程中，由于TFT阈值电压不准使得整个电路不工作的可能。

Description

悬浮栅晶体管及其制作方法、应用方法、显示器驱动电路
技术领域
本发明涉及TFT（薄膜晶体管）技术领域，尤其涉及一种基于TFT制作工艺的一种悬浮栅晶体管及其制作方法、应用方法、显示驱动电路。
背景技术
悬浮栅技术早在20世纪60年代已经提出，但是由于受到当时制造技术的限制，一直到80年代才被应用到存储领域。如今的EPROM，EEPROM，Flash存储器等都应用了悬浮栅技术。
“悬浮栅”一词源于一种特殊的MOS晶体管。这种晶体管有源极104、漏极105，两个栅极，其中一个有电气连接，叫控制栅100，也就是一般意义上的栅极。还有一个没有外引线,它被完全包裹在两层SiO2薄膜102层里面,是浮空的,所以称之为悬浮栅103，如图1所示。
悬浮栅MOS晶体管的工作原理是利用悬浮栅上是否储存有电荷或储存电荷的多少来改变MOS管的阈值电压,从而改变MOS管的外部特性。这个过程可描述如下：当在MOS管的漏、栅极加上足够高的电压(如25V)，源极及衬底接地时，漏极及衬底之间的PN结反向击穿,产生大量的高能电子。这些电子穿过很薄的SiOx薄膜层堆积在悬浮栅上，从而使悬浮栅带有负电荷。如这一过程维持足够长，悬浮栅将积累足够的电子。当移去外加电压后，悬浮栅上的电子由于没有放电回路，所以能够长期保存。当悬浮栅上带有负电荷时,衬底表面感应的是正电荷,这就使得MOS管的开启电压变高。这时，原来能使MOS管导通的阈值电压加在此时的MOS管栅极上，MOS管将仍旧处于截止状态。存储单元就是利用这一原理来存储二进制数据的。悬浮栅上的电荷可通过以下两种方法得以修改：
(1)通过紫外线长时间的照射。当紫外线照射时,浮栅上的电子形成光电流而泄放。
(2)通过在漏、栅之间加一大电压(漏接电源正端,栅接负端)。这一大电压将在SiOx薄膜层中产生一强电场,将电子从悬浮栅拉回到衬底中,从而实现悬浮栅电荷的修改。
以上介绍悬浮栅技术，都是基于半导体制造工艺，在TFT制造领域目前还没有相应的制造技术。
悬浮栅技术目前广泛应用在EPROM，EEPROM，Flash存储器等器件中。在TFT行业，同样需要有存储功能的器件，但是受到制造工艺，需求度等因素的影响，一直没有在玻璃基板上制造出具有存储功能的器件。
发明内容
为了解决上述技术问题，本发明提供一种基于TFT制造技术的悬浮栅晶体管及其制作方法、应用方法、显示驱动电路，悬浮栅极能够存储一定的电荷，从而能够起到存储数据的作用。
为了达到上述目的，本发明采用的技术方案是：一种悬浮栅晶体管，包括基板，设置在基板上的悬浮栅极、源极、漏极和控制栅极，还包括：
所述基板上依次设有第一层绝缘薄膜、多晶硅薄膜，所述多晶硅薄膜形成有沟道区域，所述沟道区域的位置与所述悬浮栅极的位置相对应。
进一步的，所述多晶硅薄膜上依次设置第二层绝缘薄膜和第三层绝缘薄膜，所述第二层绝缘薄膜和第三层绝缘薄膜之间设有所述悬浮栅极。
进一步的，所述第三层绝缘薄膜位于所述悬浮栅极的两侧分别设有第一开口和第二开口，所述第一开口和第二开口分别向内延伸至所述多晶硅薄膜形成源极过孔和漏极过孔，所述源极过孔和所述漏极过孔的内壁设有金属薄膜分别形成源极和漏极。
进一步的，所述第三层绝缘薄膜的与所述悬浮栅极相对应的部位沉积一层金属薄膜形成控制栅极。
进一步的，所述第一层绝缘薄膜、第二层绝缘薄膜、第三层绝缘薄膜均采用SiOx、SiNx中的一种或两种制作。
本发明还提供一种显示器驱动电路，包括上述的悬浮栅晶体管。
本发明还提供一种悬浮栅晶体管制作方法，包括以下步骤：
在基板上依次形成第一层绝缘薄膜和多晶硅薄膜；
在所述多晶硅薄膜上形成沟道区域；
在所述多晶硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜，以及设置在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极；
在所述多晶硅薄膜上形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成控制栅极。
进一步的，在基板上依次形成第一层绝缘薄膜和多晶硅薄膜，包括：
在基板上依次沉积所述第一层绝缘薄膜和非晶硅薄膜；
进行退火处理，使得所述非晶硅薄膜形成所述多晶硅薄膜。
进一步的，在所述多晶硅薄膜上形成沟道区域，包括：
在所述多晶硅薄膜表面涂覆第一层光刻胶，光刻曝光，所述多晶硅薄膜上与所述第一层光刻胶的未保留区域相对应的区域为沟道区域；
在所述沟道区域注入硼烷离子或磷烷离子，使得所述位于所述沟道区域的所述多晶硅薄膜形成P型多晶硅或N型多晶硅；
采用剥离工艺去除所述第一层光刻胶；
进行退火处理。
进一步的，在所述多晶硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜，以及设置在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极包括：
采用气相沉积法在所述多晶硅薄膜上依次沉积第二层绝缘薄膜、第二层非晶硅薄膜；
在所述第二层非晶硅薄膜表面涂覆第二层光刻胶、光刻曝光，使得该第二层光刻胶的保留区域与所述沟道区域相对应；
采用刻蚀工艺，保留所述第二层非晶硅薄膜上与所述沟道区域相对应的区域，形成悬浮栅极；
剥离所述第二层光刻胶；
采用气相沉积法在所述第二层绝缘薄膜表面、所述悬浮栅极表面沉积第三层绝缘薄膜。
进一步的，在所述多晶硅薄膜上形成源极区域和漏极区域包括：
在所述第三层绝缘薄膜上涂覆第三层光刻胶、曝光，显影；
对所述第二层绝缘薄膜、所述第三层绝缘薄膜进行刻蚀，去除所述第二层绝缘薄膜、所述第三层绝缘薄膜上与所述第三层光刻胶的未保留区域相对应的区域，在所述多晶硅薄膜上形成源极区域和漏极区域。
进一步的，在所述第三层绝缘薄膜上形成控制栅极包括：
在所述源极区域和所述漏极区域重掺杂硼烷离子或磷烷离子，形成良好的导电层；
剥离所述第三层光刻胶；
采用气相沉积法在所述第二层绝缘薄膜、所述第三层绝缘薄膜的未刻蚀区域以及所述多晶硅薄膜上形成源极区域和漏极区域沉积一层金属薄膜；
在所述金属薄膜上沉积第四层光刻胶、曝光，显影；
进行刻蚀，在所述金属薄膜上形成源极、漏极、控制栅极；
剥离所述第四层光刻胶。
本发明还提供一种采用所述的悬浮栅晶体管制作方法制成的悬浮栅晶体管的应用方法，包括以下步骤：
将控制栅极和源极连接具有预设电压的电源，沟道区域和漏极接地；
经过一预设时间后断开电源，所述悬浮栅极上累积预定数量的负电荷，所述悬浮栅晶体管的阈值电压达到设定数值。。
进一步的，还包括：
测试薄膜晶体管的电压，在所述薄膜晶体管的电压超过预设调整电压时，将控制栅极和源极接地，沟道区域和漏极连接具有所述预设电压的电源；当所述薄膜晶体管的电压小于预设调整电压时，返回步骤将控制栅极和源极连接具有预设电压的电源，多晶硅薄膜的沟道区域和漏极接地。
本发明的有益效果是：采用本发明悬浮栅晶体管能够调节TFT阈值电压，消除了在背板生产过程中，由于TFT阈值电压不准使得整个电路不工作的可能。
附图说明
图1表示现有技术中悬浮栅MOS晶体管结构示意图；
图2表示本发明悬浮栅结构示意图；
图3表示本发明悬浮栅截面结构示意图；
图4表示本发明悬浮栅晶体管制作方法第一步骤结构示意图；
图5表示本发明悬浮栅晶体管制作方法第二步骤结构示意图；
图6表示本发明悬浮栅晶体管制作方法第三步骤结构示意图；
图7表示本发明悬浮栅晶体管制作方法第四步骤结构示意图；
图8表示本发明悬浮栅晶体管制作方法第五步骤结构示意图；
图9表示本发明悬浮栅晶体管制作方法第六步骤结构示意图；
图10表示本发明悬浮栅晶体管制作方法第七步骤结构示意图；
图11表示本发明悬浮栅晶体管制作方法第八步骤结构示意图；
图12表示本发明悬浮栅晶体管制作方法第九步骤结构示意图；
图13表示本发明悬浮栅晶体管制作方法第十步骤结构示意图；
图14表示本发明悬浮栅晶体管制作方法第十一步骤结构示意图；
图15表示本发明悬浮栅晶体管制作方法第十二步骤结构示意图；
图16表示本发明悬浮栅晶体管制作方法第十三步骤结构示意图；
图17表示本发明悬浮栅晶体管制作方法第十四步骤结构示意图；
图18表示本发明悬浮栅晶体管制作方法第十五步骤结构示意图；
图19表示本发明悬浮栅晶体管制作方法第十六步骤结构示意图；
图20表示本发明悬浮栅晶体管制作方法第十七步骤结构示意图；
图21表示本发明悬浮栅晶体管制作方法第十八步骤结构示意图；
图22表示本发明悬浮栅晶体管应用方法电源连接结构示意图；
图23表示本发明悬浮栅晶体管应用方法电源连接结构示意图。
具体实施方式
以下结合附图对本发明结构和原理进行详细说明，所举实施例仅用于解释本发明，并非以此限定本发明的保护范围。
如图2和图3所示，本实施例提供一种悬浮栅晶体管，包括基板1，设置在基板1上的悬浮栅极3、源极4、漏极5和控制栅极6，还包括，
所述基板1上依次设有第一层绝缘薄膜7、多晶硅薄膜8，多晶硅薄膜8上形成沟道区域2，所述沟道区域2的位置与所述悬浮栅极3的位置相对应。
所述多晶硅薄膜8上依次设置第二层绝缘薄膜9和第三层绝缘薄膜10，所述第二层绝缘薄膜9和第三层绝缘薄膜10之间设有所述悬浮栅极3。
所述第三层绝缘薄膜10位于所述悬浮栅极3的两侧分别设有第一开口和第二开口，所述第一开口和第二开口分别向内延伸至所述多晶硅薄膜8形成源极过孔41和漏极过孔51，所述源极过孔41和所述漏极过孔51内设有金属薄膜分别形成源极4和漏极5。
所述第三层绝缘薄膜10与所述悬浮栅极3相对应的部位设置一层金属薄膜形成控制栅极6。
实际应用中，所述第三层绝缘薄膜10上沉积一层金属薄膜，所述金属薄膜同时覆盖所述多晶硅薄膜8的外露的部分，然后经过光刻曝光在所述第三层绝缘薄膜10的相应位置形成所述控制栅极6，在所述多晶硅薄膜8的外露的部分分别形成源极4和漏极5。
本实施例中，第一层绝缘薄膜、第二层绝缘薄膜、第三层绝缘薄膜均可以采用SiOx、SiNx中的一种或几种组合而制成。
本实施例中，将悬浮栅技术应用到TFT领域，所述基板为玻璃基板，使得应用于显示器驱动电路的悬浮栅晶体管可以存储电荷，进一步的可用于调整TFT阈值电压。
本实施例悬浮栅晶体管能够调节TFT阈值电压，消除了在背板生产过程中，由于TFT阈值电压不准使得整个电路不工作的可能。在低温多晶硅技术，GOA（Gate On Array），COA（Color Filter on Array）等技术中，一个像素使用几个MOS管，用来补偿，驱动等功能。如果使用此技术，可以大大减少MOS管的个数，增加像素的个数和显示器的分辨率。上述GOA是TFT-LCD中一种高技术水平设计，基本概念是将液晶面板的栅极驱动集成在玻璃基板上，形成对面板的扫描驱动；COA是将彩色滤光片与阵列基板集成在一起的其中一种集成技术。
本发明还提供一种悬浮栅晶体管制作方法，包括以下步骤：
在基板上依次形成第一层绝缘薄膜7和多晶硅薄膜8；
在所述多晶硅薄膜8上形成沟道区域2；
在所述多晶硅薄膜8上形成第二层绝缘薄膜9和第三层绝缘薄膜10，以及设置在第二层绝缘薄膜9和第三层绝缘薄膜10之间的悬浮栅极3；
在所述多晶硅薄膜8上形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成源极4、漏极5、控制栅极6。
在基板上依次形成第一层绝缘薄膜7和多晶硅薄膜8，具体包括：
在基板1上依次沉积所述第一层绝缘薄膜7和第一层非晶硅薄膜81；
进行退火处理，使得所述第一层非晶硅薄膜81形成所述多晶硅薄膜8。
在所述多晶硅薄膜8上形成沟道区域，包括：
在所述多晶硅薄膜8表面涂覆第一层光刻胶11，曝光，显影，所述多晶硅薄膜8上与所述第一层光刻胶11的未保留区域相对应的区域为沟道区域；
在所述沟道区域注入硼烷离子或磷烷离子，使得所述位于所述沟道区域的所述多晶硅薄膜8形成P型多晶硅或N型多晶硅；
采用剥离工艺去除所述第一层光刻胶11；
进行退火处理。
在所述多晶硅薄膜8上形成第二层绝缘薄膜9和第三层绝缘薄膜10，以及设置在第二层绝缘薄膜9和第三层绝缘薄膜10之间的悬浮栅极3包括：
采用气相沉积法在所述多晶硅薄膜8上依次沉积第二层绝缘薄膜9、第二层非晶硅薄膜12；
在所述第二层非晶硅薄膜12表面涂覆第二层光刻胶13、曝光，显影，使得该第二层光刻胶13的保留区域与所述沟道区域相对应；
采用刻蚀工艺，保留所述第二层非晶硅薄膜12上与所述沟道区域相对应的区域，形成悬浮栅极3；
剥离所述第二层光刻胶13；
采用气相沉积法在所述第二层绝缘薄膜9表面、所述悬浮栅极3表面沉积第三层绝缘薄膜10。
在所述多晶硅薄膜上形成源极区域和漏极区域包括：
在所述第三层绝缘薄膜10上涂覆第三层光刻胶14、光刻曝光；
对所述第二层绝缘薄膜9、所述第三层绝缘薄膜10进行刻蚀，去除所述第二层绝缘薄膜9、所述第三层绝缘薄膜10上与所述第三层光刻胶14的未保留区域相对应的区域，在所述多晶硅薄膜8上形成源极区域82和漏极区域83。
在所述第三层绝缘薄膜10上形成控制栅极6包括：
在所述源极区域82和所述漏极区域83重掺杂硼烷离子或磷烷离子，以便所述源极区域82和所述漏极区域83与后续步骤中沉积的金属薄膜接触良好；
剥离所述第三层光刻胶14；
采用气相沉积法在所述第二层绝缘薄膜9、所述第三层绝缘薄膜10的未刻蚀区域以及所述多晶硅薄膜8上形成源极区域82和漏极区域83沉积一层金属薄膜15；
在所述金属薄膜15上沉积第四层光刻胶16、光刻曝光；
进行刻蚀，在所述金属薄膜15上形成控制栅极6；
剥离所述第四层光刻胶16。
一具体实施例中，悬浮栅晶体管制作方法如下：
使用PECVD（气相沉积法）生长第一层绝缘薄膜7和第一层非晶硅薄膜81，如图4所示；
使用ELA（准分子激光退火）工艺，使得非晶硅变成多晶硅，如图5所示，
使用掩膜（光刻）工艺，漏出沟道区域，如图6所示，光刻工艺一般包括涂胶、曝光、显影等处理，此为现有技术，再次不再详述。
使用Doping（掺杂工艺，掺杂B2H6（硼烷）或PH3（磷烷），使得沟道区域变成P+多晶硅（P型多晶硅）或N+多晶硅（N型多晶硅），如图7所示；
使用剥离工艺，剥去表面的第一层光刻胶11，如图8所示；
使用退火设备，活化P+多晶硅，如图9所示；
使用PECVD生长第二层绝缘薄膜9和第二层非晶硅薄膜12，如图10所示；
使用掩膜工艺，第二层光刻胶13挡住沟道区域上面部分，如图11所示；
使用刻蚀工艺，刻蚀出悬浮栅部分，如图12所示；
使用剥离工艺，剥去表面第二层光刻胶13，如图13所示；
使用PECVD生长第三层层绝缘薄膜10，如图14所示；
使用掩膜工艺，漏出MOS管源极过孔和漏极过孔，如图15所示；
使用刻蚀工艺，刻蚀出源极过孔41和漏极过孔51，如图16所示；
使用掺杂工艺，重掺杂源极区域82和漏极区域83（在源极过孔41和漏极过孔51相对应的区域注入硼烷离子或磷烷离子），如图17所示；
使用剥离工艺，剥去表面第三层光刻胶14，如图18所示；
使用Sputter（喷涂）设备，沉积一层金属薄膜，如图19所示；
使用掩膜工艺，漏出源极、漏极、控制栅极所对应的区域，如图20所示；
使用剥离工艺，剥去表面第四层光刻胶16，如图21所示。
本发明还提供一种采用所述的悬浮栅晶体管制作方法制成的悬浮栅晶体管的应用方法，包括以下步骤：
将控制栅极和源极连接具有预设电压的电源，沟道区域和漏极接地；
经过一预设时间后断开电源，所述悬浮栅极上累积预定数量的负电荷，所述悬浮栅晶体管的阈值电压达到设定数值。。
利用悬浮栅上是否储存有电荷或储存电荷的多少来改变MOS管的阈值电压,经过预设时间，悬浮栅极可以存储足够的电荷。
本实施例中所述预设电压为25V，但并不限于此。
测试悬浮栅晶体管的电压，在所述悬浮栅晶体管的电压超过预设调整电压时，将控制栅极和源极接地，沟道区域和漏极连接具有所述预设电压的电源；当所述悬浮栅晶体管的电压小于预设调整电压时，返回步骤将控制栅极和源极连接具有预设电压的电源，多晶硅薄膜的沟道区域和漏极接地。
当所述悬浮栅晶体管的电压超过预设调整电压时，还可以通过紫外线照射的方式进行电压释放。
以具体实施例中，调整TFT阈值电压的具体过程如下：
在控制栅极和源极连接编程电源VCC，沟道区域和漏极接地，如图22所示；
编程电源施加25V的电源，根据需要调整的悬浮栅极电荷量的多少控制编程时间，如图23所示；
编程电源施加完毕，源极，漏极，沟道区域极都和编程电源断开。
测试TFT阈值电压（悬浮栅晶体管正常启动所需的电压），判断TFT阈值电压是否符合电路正常工作的条件，不符合则继续按照上述步骤调整。
悬浮栅晶体管的悬浮栅极能够储存一定量的电荷，控制栅极在正常驱动电压的基础上需要再加上悬浮栅极的电压才能正常驱动晶体管。悬浮栅就是通过这个原理调整了TFT的阈值电压。这种方法避免了因TFT阈值电压不符，使得整个电路不能正常工作，导致成本的大量增加。悬浮栅晶体管调整TFT阈值电压可以在最终工艺完成后，根据TFT阈值电压测试情况，对于那些阈值电压不在正常范围内的TFT进行悬浮栅电荷的编程，使得能够重复利用，大大提高了产品的良率。
本发明还提供一种显示器驱动电路，包括悬浮栅晶体管，该悬浮栅晶体管包括基板1，设置在基板1上的悬浮栅极3、源极4、漏极5和控制栅极6，还包括，
所述基板1上依次设有第一层绝缘薄膜7、多晶硅薄膜8，多晶硅薄膜8中部形成沟道区域2，所述沟道区域2的位置与所述悬浮栅极3的位置相对应。
所述沟道区域2的设置利于在悬浮栅晶体管制作过程中，悬浮栅的制作。
所述多晶硅薄膜8上依次设置第二层绝缘薄膜9和第三层绝缘薄膜10，所述第二层绝缘薄膜9和第三层绝缘薄膜10之间设有所述悬浮栅极3。
所述第三层绝缘薄膜10位于所述悬浮栅极3的两侧分别设有第一开口和第二开口，所述第一开口和第二开口分别向内延伸至所述多晶硅薄膜8形成源极过孔41和漏极过孔51，所述源极过孔41和所述漏极过孔51内设有金属薄膜分别形成源极4和漏极5。
所述第三层绝缘薄膜10上与所述悬浮栅极3相对应的部位沉积一层金属薄膜形成控制栅极6。
实际应用中，所述第三层绝缘薄膜10上沉积一层金属薄膜，所述金属薄膜同时覆盖所述多晶硅薄膜8的外露的部分，然后经过光刻曝光在所述第三层绝缘薄膜10的相应位置形成所述控制栅极6，在所述多晶硅薄膜8的外露的部分分别形成源极4和漏极5。
本实施例中，第一层绝缘薄膜、第二层绝缘薄膜、第三层绝缘薄膜均可以采用SiOx、SiNx中的一种或几种组合而制成。（图2中只显示出了悬浮栅晶体管部分结构）
经悬浮栅晶体管代替了现有技术中的薄膜晶体管，该悬浮栅晶体管的阈值电压可调，避免了因TFT电压不符而导致整个驱动电路不能正常工作的情况的发生。
本发明还提供一种显示器驱动电路制作方法，包括以下步骤：
在PCB板上制作显示器驱动电路的各个电子元件，其中悬浮栅晶体管的制作工艺包括：
在基板上依次形成第一层绝缘薄膜7和多晶硅薄膜8；
在所述多晶硅薄膜8上形成沟道区域2；
在所述多晶硅薄膜8上形成第二层绝缘薄膜9和第三层绝缘薄膜10，以及设置在第二层绝缘薄膜9和第三层绝缘薄膜10之间的悬浮栅极3；
在所述多晶硅薄膜8上形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成源极4、漏极5、控制栅极6。
在基板上依次形成第一层绝缘薄膜7和多晶硅薄膜8，具体包括：
在基板1上依次沉积所述第一层绝缘薄膜7和第一层非晶硅薄膜81；
进行退火处理，使得所述第一层非晶硅薄膜81形成所述多晶硅薄膜8。
在所述多晶硅薄膜8上形成沟道区域，包括：
在所述多晶硅薄膜8表面涂覆第一层光刻胶11，曝光，显影，所述多晶硅薄膜8上与所述第一层光刻胶11的未保留区域相对应的区域为沟道区域；
在所述沟道区域注入硼烷离子或磷烷离子，使得所述位于所述沟道区域的所述多晶硅薄膜8形成P型多晶硅或N型多晶硅；
采用剥离工艺去除所述第一层光刻胶11；
进行退火处理。
在所述多晶硅薄膜8上形成第二层绝缘薄膜9和第三层绝缘薄膜10，以及设置在第二层绝缘薄膜9和第三层绝缘薄膜10之间的悬浮栅极3包括：
采用气相沉积法在所述多晶硅薄膜8上依次沉积第二层绝缘薄膜9、第二层非晶硅薄膜12；
在所述第二层非晶硅薄膜12表面涂覆第二层光刻胶13、曝光，显影，使得该第二层光刻胶13的保留区域与所述沟道区域相对应；
采用刻蚀工艺，保留所述第二层非晶硅薄膜12上与所述沟道区域相对应的区域，形成悬浮栅极3；
剥离所述第二层光刻胶13；
采用气相沉积法在所述第二层绝缘薄膜9表面、所述悬浮栅极3表面沉积第三层绝缘薄膜10。
在所述多晶硅薄膜上形成源极区域和漏极区域包括：
在所述第三层绝缘薄膜10上涂覆第三层光刻胶14、光刻曝光；
对所述第二层绝缘薄膜9、所述第三层绝缘薄膜10进行刻蚀，去除所述第二层绝缘薄膜9、所述第三层绝缘薄膜10上与所述第三层光刻胶14的未保留区域相对应的区域，在所述多晶硅薄膜8上形成源极区域82和漏极区域83。
在所述第三层绝缘薄膜10上形成控制栅极6包括：
在所述源极区域82和所述漏极区域83重掺杂硼烷离子或磷烷离子，以便所述源极区域82和所述漏极区域83与后续步骤中沉积的金属薄膜接触良好；
剥离所述第三层光刻胶14；
采用气相沉积法在所述第二层绝缘薄膜9、所述第三层绝缘薄膜10的未刻蚀区域以及所述多晶硅薄膜8上形成源极区域82和漏极区域83沉积一层金属薄膜15；
在所述金属薄膜15上沉积第四层光刻胶16、光刻曝光；
进行刻蚀，在所述金属薄膜15上形成控制栅极6；
剥离所述第四层光刻胶16。
本发明还提供一种显示器驱动电路的应用方法，在实际应用中，可通过调整显示器驱动电路中的悬浮栅晶体管的阈值电压来进行较准，使得显示器驱动电路可正常工作，其中，悬浮栅晶体管阈值电压调整过程包括：
将控制栅极和源极连接具有预设电压的电源，沟道区域和漏极接地；
经过一预设时间后断开电源，所述悬浮栅极上累积预定数量的负电荷，所述悬浮栅晶体管的阈值电压达到设定数值。
利用悬浮栅上是否储存有电荷或储存电荷的多少来改变MOS管的阈值电压,经过预设时间，悬浮栅极可以存储足够的电荷。
本实施例中所述预设电压为25V，但并不限于此。
测试薄膜晶体管的电压，在所述薄膜晶体管的电压超过预设调整电压时，将控制栅极和源极接地，沟道区域和漏极连接具有所述预设电压的电源；当所述薄膜晶体管的电压小于预设调整电压时，返回步骤将控制栅极和源极连接具有预设电压的电源，多晶硅薄膜的沟道区域和漏极接地。
当所述薄膜晶体管的电压超过预设调整电压时，还可以通过紫外线照射的方式进行电压释放。
以具体实施例中，调整TFT阈值电压的具体过程如下：
在控制栅极和源极连接编程电源VCC，沟道区域和漏极接地，如图22所示；
编程电源施加25V的电源，根据需要调整的悬浮栅极电荷量的多少控制编程时间，如图23所示；
编程电源施加完毕，源极，漏极，沟道区域极都和编程电源断开。
测试TFT阈值电压，判断TFT阈值电压是否符合电路正常工作的条件，不符合则继续按照上述步骤调整。
悬浮栅晶体管的悬浮栅极能够储存一定量的电荷，控制栅极在正常驱动电压的基础上需要再加上悬浮栅极的电压才能正常驱动晶体管。悬浮栅就是通过这个原理调整了TFT的阈值电压。这种方法避免了因TFT阈值电压不符，使得整个电路不能正常工作，导致成本的大量增加。悬浮栅晶体管调整TFT阈值电压可以在最终工艺完成后，根据TFT阈值电压测试情况，对于那些阈值电压不在正常范围内的TFT进行悬浮栅电荷的编程，使得能够重复利用，大大提高了产品的良率。
以上所述为本发明较佳实施例，应当指出，对于本领域技术人员来说，在不脱离本发明所述原理的前提下，还可以作出如下改进和润饰，这些改进和润饰也应视为本发明保护范围。

Claims (14)

1.一种悬浮栅晶体管，其特征在于，包括基板，设置在基板上的悬浮栅极、源极、漏极和控制栅极，还包括：
所述基板上依次设有第一层绝缘薄膜、多晶硅薄膜，所述多晶硅薄膜形成有沟道区域，所述沟道区域的位置与所述悬浮栅极的位置相对应。
2.根据权利要求1所述的悬浮栅晶体管，其特征在于，所述多晶硅薄膜上依次设置第二层绝缘薄膜和第三层绝缘薄膜，所述第二层绝缘薄膜和第三层绝缘薄膜之间设有所述悬浮栅极。
3.根据权利要求2所述的悬浮栅晶体管，其特征在于，所述第三层绝缘薄膜位于所述悬浮栅极的两侧分别设有第一开口和第二开口，所述第一开口和第二开口分别向内延伸至所述多晶硅薄膜形成源极过孔和漏极过孔，所述源极过孔和所述漏极过孔的内壁设有金属薄膜分别形成源极和漏极。
4.根据权利要求3所述的悬浮栅晶体管，其特征在于，所述第三层绝缘薄膜上与所述悬浮栅极相对应的部位设置一层金属薄膜形成所述控制栅极。
5.根据权利要求3所述的悬浮栅晶体管，其特征在于，所述第一层绝缘薄膜、第二层绝缘薄膜、第三层绝缘薄膜均采用SiOx、SiNx中的一种或两种制作。
6.一种显示器驱动电路，其特征在于，包括权利要求1-5任一项所述的悬浮栅晶体管。
7.一种悬浮栅晶体管制作方法，其特征在于，包括以下步骤：
在基板上依次形成第一层绝缘薄膜和多晶硅薄膜；
在所述多晶硅薄膜上形成沟道区域；
在所述多晶硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜，以及设置在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极；
在所述多晶硅薄膜上形成源极区域和漏极区域；
在所述第三层绝缘薄膜上形成源极、漏极、控制栅极。
8.根据权利要求7所述的悬浮栅晶体管制作方法，其特征在于，在基板上依次形成第一层绝缘薄膜和多晶硅薄膜，包括：
在基板上依次沉积所述第一层绝缘薄膜和非晶硅薄膜；
进行退火处理，使得所述非晶硅薄膜形成所述多晶硅薄膜。
9.根据权利要求7或8所述的悬浮栅晶体管制作方法，其特征在于，在所述多晶硅薄膜上形成沟道区域，包括：
在所述多晶硅薄膜表面涂覆第一层光刻胶，曝光，显影，所述多晶硅薄膜上与所述第一层光刻胶的未保留区域相对应的区域为沟道区域；
在所述沟道区域注入硼烷离子或磷烷离子，使得所述位于所述沟道区域的所述多晶硅薄膜形成P型多晶硅或N型多晶硅；
采用剥离工艺去除所述第一层光刻胶；
进行退火处理。
10.根据权利要求7所述的悬浮栅晶体管制作方法，其特征在于，在所述多晶硅薄膜上形成第二层绝缘薄膜和第三层绝缘薄膜，以及设置在第二层绝缘薄膜和第三层绝缘薄膜之间的悬浮栅极包括：
采用气相沉积法在所述多晶硅薄膜上依次沉积第二层绝缘薄膜、第二层非晶硅薄膜；
在所述第二层非晶硅薄膜表面涂覆第二层光刻胶、曝光，显影，使得该第二层光刻胶的保留区域与所述沟道区域相对应；
采用刻蚀工艺，保留所述第二层非晶硅薄膜上与所述沟道区域相对应的区域，形成悬浮栅极；
剥离所述第二层光刻胶；
采用气相沉积法在所述第二层绝缘薄膜表面、所述悬浮栅极表面沉积第三层绝缘薄膜。
11.根据权利要求7或10所述的悬浮栅晶体管制作方法，其特征在于，在所述多晶硅薄膜上形成源极区域和漏极区域包括：
在所述第三层绝缘薄膜上涂覆第三层光刻胶、曝光，显影；
对所述第二层绝缘薄膜、所述第三层绝缘薄膜进行刻蚀，去除所述第二层绝缘薄膜、所述第三层绝缘薄膜上与所述第三层光刻胶的未保留区域相对应的区域，在所述多晶硅薄膜上形成源极区域和漏极区域。
12.根据权利要求7所述的悬浮栅晶体管制作方法，其特征在于，在所述第三层绝缘薄膜上形成控制栅极包括：
在所述源极区域和所述漏极区域重掺杂硼烷离子或磷烷离子，形成导电层；
剥离所述第三层光刻胶；
采用气相沉积法在所述第二层绝缘薄膜、所述第三层绝缘薄膜的未刻蚀区域以及所述多晶硅薄膜上形成源极区域和漏极区域沉积一层金属薄膜；
在所述金属薄膜上沉积第四层光刻胶、曝光，显影；
进行刻蚀，在所述金属薄膜上形成控制栅极；
剥离所述第四层光刻胶。
13.一种采用权利要求1-5任一项所述的悬浮栅晶体管的应用方法，其特征在于，包括以下步骤：
将控制栅极和源极连接具有预设电压的电源，多晶硅薄膜的沟道区域和漏极接地；
经过一预设时间后断开电源，所述悬浮栅极上累积预定数量的负电荷，所述悬浮栅晶体管的阈值电压达到设定数值。
14.根据权利要求13所述的悬浮栅晶体管的应用方法，其特征在于，还包括：
测试薄膜晶体管的电压，在所述薄膜晶体管的电压超过预设调整电压时，将控制栅极和源极接地，沟道区域和漏极连接具有所述预设电压的电源；当所述薄膜晶体管的电压小于预设调整电压时，返回步骤将控制栅极和源极连接具有预设电压的电源，多晶硅薄膜的沟道区域和漏极接地。
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