CN204391121U - 一种显示装置、阵列基板及薄膜晶体管 - Google Patents

一种显示装置、阵列基板及薄膜晶体管 Download PDF

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CN204391121U
CN204391121U CN201520054037.2U CN201520054037U CN204391121U CN 204391121 U CN204391121 U CN 204391121U CN 201520054037 U CN201520054037 U CN 201520054037U CN 204391121 U CN204391121 U CN 204391121U
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grid
source
doped region
lightly doped
drain electrode
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石磊
许晓伟
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BOE Technology Group Co Ltd
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Abstract

本实用新型涉及显示工艺技术领域，特别涉及一种显示装置、阵列基板及薄膜晶体管。该薄膜晶体管依次包括第一栅极、第一栅绝缘层、有源层、第二栅绝缘层、第二栅极、第三栅绝缘层和源漏电极，有源层与第二栅极相对应的区域的外侧分别为源漏轻掺杂区域和源漏重掺杂区域，源、漏电极与源、漏重掺杂区域电连接；第一栅极设置于漏电极所对应区域的漏轻掺杂区域下方或第一栅极分为两个部分，分别设置于源、漏电极对应区域的轻掺杂区域下方。本实用新型提供一种显示装置、阵列基板、薄膜晶体管，通过LDD结构降低TFT关态漏电流，同时通过底栅结构提高TFT开态电流的效果，提高产品良品率。

Description

一种显示装置、阵列基板及薄膜晶体管
技术领域
本实用新型涉及显示工艺技术领域，特别涉及一种显示装置、阵列基板、薄膜晶体管。
背景技术
在LCD(液晶显示器)或OLED(有机发光二极管)显示器中，每个像素点都是由集成在像素点后面的TFT(Thin Film Transistor，薄膜场效应晶体管)来驱动，从而可以做到高速度、高亮度、高对比度的显示屏幕信息。在现在的生产技术中，多采用多晶硅或非晶硅来制造TFT。多晶硅的载流子迁移率为10-200cm2/V，明显高于非晶硅的载流子迁移率(1cm2/V)，所以多晶硅相对于非晶硅具有更高的电容性和存储性。
对于LCD和OLED，TFT一般形成于玻璃基板上，由于玻璃的热力学限制，多晶硅TFT的结晶特性及离子注入后退火的过程往往不能得到有效的恢复，则在反偏电压的情况下会出现较大的漏电流，影响TFT的正常使用。
为了抑制TFT的漏电流，一般采用在TFT的栅极和源、漏极间进行轻掺杂的方式，尤其是在一些短沟道的情况下，轻掺杂漏区(LightlyDoped Drain，LDD)的宽度范围仅为0.3-1μm。在TFT正常工作时，往往开态电流会受到影响，导致正常工作的TFT电阻过大，功耗增大。
实用新型内容
(一)所要解决的技术问题
本实用新型所要解决的技术问题是提供一种显示装置、阵列基板、薄膜晶体管，以克服现有技术中TFT关态电流较强，导致TFT工作时由于LDD结构而导致开态电流降低的TFT结构。
(二)技术内容
为了解决上述技术问题，本实用新型一方面提供一种薄膜晶体管，依次包括第一栅极、第一栅绝缘层，所述第一栅绝缘层上设有有源层，所述有源层上依次设有第二栅绝缘层、第二栅极、第三栅绝缘层和源漏电极，所述源漏电极在第三栅绝缘层上；
所述有源层与第二栅极相对应的区域的外侧分别为源漏轻掺杂区域和源漏重掺杂区域，其中，源轻掺杂区域和漏轻掺杂区域紧挨第二栅极，源重掺杂区域紧挨所述源轻掺杂区域并且所述漏重掺杂区域紧挨所述漏轻掺杂区域，所述源、漏电极与所述源、漏重掺杂区域电连接；
其中，所述第一栅极设置于所述漏电极所对应区域的漏轻掺杂区域下方或所述第一栅极分为两个部分，分别设置于所述源、漏电极对应区域的轻掺杂区域下方。
优选地，所述有源层为低温多晶硅。
优选地，所述有源层为由非晶化的氧化物通过晶化处理后的结晶状态有源层。
优选地，所述第三栅绝缘层和第二栅绝缘层上设有过孔，所述源、漏电极通过过孔与源、漏重掺杂区域接触连接。
优选地，所述第一栅极的底部还设有缓冲层。
另一方面，本实用新型还提供一种阵列基板，包括上述的薄膜晶体管。
再一方面，本实用新型还提供一种显示装置，包括上述的阵列基板。
(三)有益效果
本实用新型提供一种显示装置、阵列基板、薄膜晶体管，采用顶栅和底栅双栅结构即第二栅极和第一栅极，并且对有源层进行源漏轻掺杂区域和源漏重掺杂区域处理，通过在漏电极所对应区域的漏轻掺杂区域下方设置第一栅极或者在源、漏电极对应区域的轻掺杂区域下方分别设置第一栅极的两个部分，从而降低了TFT关态漏电流，同时通过底栅结构提高TFT开态电流的效果，提高产品良品率。
附图说明
图1～图6为本实用新型实施例一阵列基板制作流程步骤示意图；
图7为本实用新型实施例二阵列基板结构示意图；
图8为本实用新型实施例一阵列基板制作方法流程图。
其中：
1：基板；2：缓冲层；3：第一栅极；4：第一栅绝缘层；5：有源层；6：第二栅绝缘层；7：第二栅极；8：光刻胶；91：源轻掺杂区域；92：源重掺杂区域；101：漏轻掺杂区域；102：漏重掺杂区域；11：第三栅绝缘层；12：源电极；13：漏电极；14：CD偏差。
具体实施方式
下面结合附图和实施例，对本实用新型的具体实施方式作进一步详细描述。以下实施例用于说明本实用新型，但不是用来限制本实用新型的范围。
实施例1如图6所示，本实用新型实施例提供一种阵列基板，包括基板1，所述基板1上设有缓冲层2、第一栅极3(即底栅)和第一栅绝缘层4，所述第一栅绝缘层4上设有有源层5，所述有源层5上依次设有第二栅绝缘层6、第二栅极7(即顶栅)、第三栅绝缘层11和源漏电极12，该源漏电极12在第三栅绝缘层11上。该有源层5与第二栅极7相对应的区域的外侧分别为源、漏轻掺杂区域91和101以及源、漏重掺杂区域92和102，其中，该源轻掺杂区域91和漏轻掺杂区域101紧挨第二栅极7，源重掺杂区域92紧挨所述源轻掺杂区域91并且所述漏重掺杂区域102紧挨所述漏轻掺杂区域101。该源、漏电极12和13与所述源、漏重掺杂区域92和102电连接。
需要说明的是，该第一栅极3分为两个部分，分别设置于所述源、漏电极12和13对应区域的轻掺杂区域(即分别位于源轻掺杂区域91和漏轻掺杂区域101)下方。
本实施例中将第一栅极3设置为两部分，可加大第一栅极的区域面积，当顶栅加有栅压时，底栅进而打开，令LDD区域感生出更多的载流子，在较多底栅电场的作用下，加上轻掺杂产生的载流子，可最大程度地避免开态电流Ion降低的不利后果。本实施例中，同时设置第一栅极3(底栅)和第二栅极7(顶栅)采用LDD降低关态电流的优点，结合底栅结构的工作原理，在TFT工作时，即顶栅加有栅压时，底栅也同时打开，令LDD区域也感生出载流子，这样LDD区域在底栅电场的作用下，加上轻掺杂的产生的载流子，即可避免由于轻掺杂而导致的开态电流Ion降低的不利后果；同样的，当TFT的顶栅电场去除后，其处于关闭状态，此时底栅也撤去其电场，此时正好利用了LDD的优势降低了关态漏电流Ioff。
其中，所述有源层5为由非晶化的氧化物通过晶化处理后的结晶状态有源层，
其中，该有源层5还可以为低温多晶硅。
其中，所述第三栅绝缘层11和第二栅绝缘层6上设有过孔，所述源漏电极12通过过孔与源、漏重掺杂区域92和102接触连接。其中，所述源、漏重掺杂区域92和102位于源、漏轻掺杂区域91和101外侧，远离所述有源层5。
本实用新型提供的阵列基板，通过LDD结构降低TFT关态漏电流，同时通过底栅结构提高TFT开态电流的效果，提高产品良品率。
实施例2如图7所示，本实施例与实施例1存在的区别在于，本实施例中的第一栅极3只有一部分，其设置于所述漏电极所对应区域的漏轻掺杂区域101下方即可。
该第一栅极3同样和第二栅极7一起，采用LDD降低关态电流的优点，结合底栅结构的工作原理，在TFT工作时，即顶栅加有栅压时，底栅也同时打开，令LDD区域也感生出载流子，这样LDD区域在底栅电场的作用下，加上轻掺杂的产生的载流子，即可避免由于轻掺杂而导致的开态电流Ion降低的不利后果；同样的，当TFT的顶栅电场去除后，其处于关闭状态，此时底栅也撤去其电场，此时正好利用了LDD的优势降低了关态漏电流Ioff。
另外，本实用新型实施例还提供一种显示装置，包括实施例1或实施例2中的阵列基板。该阵列基板包括但不限于液晶显示器、液晶电视、液晶显示屏等设备，还可以为数码相框、电子纸、手机等需要显示模组的显示装置。
实施例3
如图8所示，本实用新型实施例还提供一种基于实施例1中的阵列基板的制作方法，具体步骤包括：
步骤S31、在基板上形成第一栅极的图形；
步骤S32、在完成上述步骤的基板上形成第一栅绝缘层；
步骤S33、在完成上述步骤的基板上形成有源层，
步骤S34、在完成上述步骤的基板上形成第二栅绝缘层；
步骤S35、在完成上述步骤的基板上形成第二栅极的图形；
步骤S36、对有源层与第二栅极相对应的区域的外侧进行源漏重掺杂和源漏轻掺杂；源轻掺杂区域和漏轻掺杂区域紧挨与第二栅极相对应的有源层，源重掺杂区域紧挨所述源轻掺杂区域并且所述漏重掺杂区域紧挨所述漏轻掺杂区域；
步骤S37、在完成上述步骤的基板上形成第三栅绝缘层，形成过孔，
步骤S38、在完成上述步骤的基板上形成源、漏电极图形，所述源、漏电极与所述源、漏重掺杂区域通过过孔电连接；
其中，所述第一栅极设置于所述漏电极所对应区域的漏轻掺杂区域下方或所述第一栅极分为两个部分，分别设置于所述源、漏电极对应区域的轻掺杂区域下方。
其中，所述有源层为由非晶化的氧化物通过晶化处理工艺形成的结晶状态有源层。
该有源层还为低温多晶硅，且所述晶化处理工艺为准分子激光退火，利于各膜层之间的贴附。
其中，对有源层与第二栅极相对应的区域的外侧进行源漏重掺杂和源漏轻掺杂具体包括：
涂覆光刻胶，对第二栅极进行曝光、显影及刻蚀处理，待第二栅极刻蚀完成后，保留光刻胶，所述光刻胶与第二栅极之间存在CD(CriticalDimension Bias，关键尺寸偏差)偏差，对未被光刻胶阻挡的有源层区域进行重掺杂处理；
剥离光刻胶，对未被第二栅极阻挡的有源层区域再次进行轻掺杂处理。
本实用新型提供的阵列基板制作方法，通过LDD结构降低TFT关态漏电流，同时通过底栅结构提高TFT开态电流的效果，提高产品良品率。
下面具体描述一下基于实施例1中的阵列基板制作方法的操作步骤：
步骤S1、在玻璃基板1上利用PECVD沉积缓冲层2，该缓冲层2的材料可以选用SiNx、SiOx或两者的混合配比；
步骤S2、在完成步骤S1的基础上采用溅射方法制作第一栅极3(即底栅)，并进行光刻、刻蚀工艺，形成底栅图形，如图1所示。该第一栅极3分为两个部分，分别设置于后续源、漏电极对应区域的轻掺杂区域下方。
步骤S3、利用PECVD的方法制作第一栅绝缘层4，再利用PECVD制作有源层5，之后再通过晶化技术，如ELA技术，使非晶化的有源层形成多晶状态，如图2所示。
步骤S4、在完成上述步骤的基板上利用PECVD方法制作第二栅绝缘层6，再利用溅射技术制作第二栅极7(即顶栅)，之后利用光刻、刻蚀工艺形成顶栅图形，且在湿刻完顶栅结构后不进行去除光刻胶8工艺，机保留光刻胶8，该光刻胶8与第二栅极7之间存在CD偏差14如图3所示。
步骤S5、在完成上述步骤的基板上，在未被光刻胶8阻挡的有源层上进行源漏重掺杂，形成源漏重掺杂区域，其目的是实现和金属电极的良好接触，在进行完重掺杂工艺后进行去除光刻胶8，之后对未被第二栅极7阻挡的有源层部分进行轻掺杂，形成LDD结构，其中，源漏重掺杂区域不会被轻掺杂工艺所影响，如图4所示。其中，源轻掺杂区域91和漏轻掺杂区域101紧挨第二栅极7，源重掺杂区域92紧挨所述源轻掺杂区域91并且所述漏重掺杂区域102紧挨所述漏轻掺杂区域101。
需要说明的是，本步骤中进行的源漏重掺杂和轻掺杂处理，采用现有工艺方法即可，本专利申请中的改进点为源漏重掺杂和轻掺杂处理的位置关系，而不在工艺本身。
步骤S6、在完成上述步骤的基板上，利用PECVD工艺制做第三栅绝缘层11，之后进行源漏金属电极过孔的光刻、刻蚀工艺，形成过孔，如图5所示。
步骤S7、在完成上述步骤的基板上，沉积源漏金属薄膜，利用溅射工艺制作源漏金属电极层形成源电极12和漏电极13，并利用光刻、刻蚀工艺形成电极图形，如图6所示。
本实用新型实施例采用LDD降低关态电流的优点，结合底栅结构的工作原理，在TFT工作时，即顶栅加有栅压时，底栅也同时打开，令LDD区域也感生出载流子，这样LDD区域在底栅电场的作用下，加上轻掺杂的产生的载流子，即可避免由于轻掺杂而导致的开态电流Ion降低的不利后果；同样的，当TFT的顶栅电场去除后，其处于关闭状态，此时底栅也撤去其电场，此时正好利用了LDD的优势降低了关态漏电流Ioff。
本实用新型提供一种显示装置、阵列基板及其制作方法，通过LDD结构降低TFT关态漏电流，同时通过底栅结构提高TFT开态电流的效果，提高产品良品率。
以上所述仅是本实用新型的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本实用新型技术原理的前提下，还可以做出若干改进和变型，这些改进和变型也应视为本实用新型的保护范围。

Claims (7)

1.一种薄膜晶体管，其特征在于，依次包括第一栅极、第一栅绝缘层，所述第一栅绝缘层上设有有源层，所述有源层上依次设有第二栅绝缘层、第二栅极、第三栅绝缘层和源漏电极，所述源漏电极在第三栅绝缘层上；
所述有源层与第二栅极相对应的区域的外侧分别为源漏轻掺杂区域和源漏重掺杂区域，其中，源轻掺杂区域和漏轻掺杂区域紧挨第二栅极，源重掺杂区域紧挨所述源轻掺杂区域并且所述漏重掺杂区域紧挨所述漏轻掺杂区域，所述源、漏电极与所述源、漏重掺杂区域电连接；
其中，所述第一栅极设置于所述漏电极所对应区域的漏轻掺杂区域下方或所述第一栅极分为两个部分，分别设置于所述源、漏电极对应区域的轻掺杂区域下方。
2.根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层为低温多晶硅。
3.根据权利要求1所述的薄膜晶体管，其特征在于，所述有源层为由非晶化的氧化物通过晶化处理后的结晶状态有源层。
4.根据权利要求1所述的薄膜晶体管，其特征在于，所述第三栅绝缘层和第二栅绝缘层上设有过孔，所述源、漏电极通过过孔与源、漏重掺杂区域接触连接。
5.如权利要求1所述的薄膜晶体管，其特征在于，所述第一栅极的底部还设有缓冲层。
6.一种阵列基板，其特征在于，包括权利要求1-5任一项所述的薄膜晶体管。
7.一种显示装置，其特征在于，包括权利要求6所述的阵列基板。
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