CN103489828B - 薄膜晶体管阵列基板的制造方法 - Google Patents

薄膜晶体管阵列基板的制造方法 Download PDF

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CN103489828B
CN103489828B CN201310462524.8A CN201310462524A CN103489828B CN 103489828 B CN103489828 B CN 103489828B CN 201310462524 A CN201310462524 A CN 201310462524A CN 103489828 B CN103489828 B CN 103489828B
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film transistor
thin
transistor array
photoresistance pattern
array base
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CN103489828A (zh
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王俊
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明提供一种薄膜晶体管阵列基板的制造方法，该薄膜晶体管阵列基板采用顶栅结构，该薄膜晶体管阵列基板的制造方法通过3次掩模来制造TFT阵列基板，其中以铟镓锌氧化物来制造薄膜晶体管阵列基板中的薄膜晶体管，可以大大提高薄膜晶体管对像素电极的充电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在薄膜晶体管液晶显示器中成为可能；同时，该制造方法仅采用了3次掩模工艺，能显著的减少制程步骤，缩短制程时间，有效地降低生产成本，提高生产效率，增加产能。

Description

薄膜晶体管阵列基板的制造方法
技术领域
本发明涉及液晶显示器制造领域，尤其涉及一种采用3次掩模的薄膜晶体管阵列基板的制造方法。
背景技术
现今科技蓬勃发展，信息商品种类推陈出新，满足了大众不同的需求。早期显示器多半为阴极射线管（Cathode Ray Tube，CRT）显示器，由于其体积庞大与耗电量大，而且所产生的辐射对于长时间使用显示器的使用者而言，有危害身体的问题。因此，现今市面上的显示器渐渐将由液晶显示器（LiquidCrystal Display，LCD）取代旧有的CRT显示器。
液晶显示器具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。现有市场上的液晶显示器大部分为背光型液晶显示器，其包括液晶面板及背光模组（backlight module）。液晶面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，并在两片玻璃基板上施加驱动电压来控制液晶分子的旋转方向，以将背光模组的光线折射出来产生画面。由于液晶面板本身不发光，需要借由背光模组提供的光源来正常显示影像，因此，背光模组成为液晶显示器的关键零组件之一。
其中，液晶面板中两片平行的玻璃基板分别为薄膜晶体管阵列基板与彩色滤光片基板。该薄膜晶体管阵列基板包括：基板；形成于所述基板上的栅极线、栅极、栅绝缘层、半导体有源层、数据线、源极、漏极，及形成于所述数据线、源极、漏极上的保护层，和形成于所述保护层上的像素电极，其中，所述栅极、源极、漏极和半导体有源层构成薄膜晶体管（TFT）。在现有技术中，该薄膜晶体管为非晶硅薄膜晶体管或低温多晶硅薄膜晶体管，通常非晶硅薄膜晶体管显示矩阵只需3—5次光刻掩模板，其成本较低，竞争力强，而低温多晶硅薄膜晶体管显示矩阵通常需要8—9次光刻掩模板，相对成本较高。
氧化物半导体IGZO（Indium Gallium Zinc Oxide，铟镓锌氧化物）由于其载流子迁移率是非晶硅的20～30倍，可以大大提高薄膜晶体管对像素电极的充放电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在薄膜晶体管液晶显示器（ThinFilm Transistor Liquid Crystal Display，TFT-LCD）中成为可能。另外，由于薄膜晶体管数量减少和提高了每个像素的透光率，IGZO液晶显示器具有更高的能效水平，而且效率更高。氧化物半导体IGZO可以利用现有的非晶硅生产线生产，只需稍加改动，因此在成本方面比低温多晶硅更有竞争力。
但，目前，以氧化物半导体IGZO制造的薄膜晶体管主要是采用6次掩模（6masks）工艺制造，生产效率较底，生产成本较高。
发明内容
本发明的目的在于提供一种薄膜晶体管阵列基板的制造方法，通过3次掩模（3masks）来制造薄膜晶体管阵列基板，能显著的减少制程步骤，缩短制程时间，有效地降低生产成本，增加产能，且，该薄膜晶体管阵列基板采用铟镓锌氧化物制造而成，可以大大提高薄膜晶体管对像素电极的充电速率，提高像素的响应速度，实现更快的刷新率。
为实现上述目的，本发明提供一种薄膜晶体管阵列基板的制造方法，该薄膜晶体管阵列基板采用顶栅结构，所述薄膜晶体管阵列基板的制造方法包括以下步骤：
步骤1、提供一基板；
步骤2、在所述基板上依次沉积形成缓冲层、氧化物半导体薄膜及第一金属层；
步骤3、在所述第一金属层上形成第一光阻层，图案化该第一光阻层以在预定位置形成第一光阻图案，其包括对应氧化物半导体薄膜的一沟道区的第一部分、及第二部分，该第一光阻图案在第二部分的厚度厚于第一部分的厚度；
步骤4、蚀刻掉没有第一光阻图案覆盖的区域的第一金属层及氧化物半导体薄膜，去掉第一光阻图案的第一部分以露出第一金属层，以第一光阻图案的第二部分为掩模蚀刻掉第一金属层以露出氧化物半导体薄膜，剥离第一光阻图案，以在第一金属层形成源极及漏极；
步骤5、在基板上依次沉积绝缘层及第二金属层，图案化第二金属层以形成栅极。
所述薄膜晶体管阵列基板的制造方法还包括：
在步骤5之后的步骤6，在所述基板上沉积保护层，在所述保护层上形成第二光阻层，图案化该第二光阻层以在预定位置形成第二光阻图案，其包括位于漏极一侧及部分漏极上方的第三部分、以及位于漏极另一侧及部分漏极上方的第四部分，第二光阻图案的第三部分与第四部分之间形成一凹部；
在步骤6之后的步骤7，蚀刻掉没有第二光阻图案覆盖的保护层及该部分保护层对应的绝缘层以露出漏极，进而形成接触孔，去掉第二光阻图案的第三部分；
在步骤7之后的步骤8，在所述基板上沉积一透明导电层，通过光阻剥离将第二光阻图案的第四部分及其上的透明导电层剥离掉。
所述薄膜晶体管阵列基板的制造方法还包括在步骤8之后的步骤9，对所述基板进行退火处理，完成薄膜晶体管阵列基板的制造。
所述基板为玻璃基板；所述缓冲层采用二氧化硅沉积而形成；所述氧化物半导体薄膜为铟镓锌氧化物薄膜。
所述步骤3中的第一光阻图案通过灰阶、掩模、曝光、显影而形成。
所述步骤4中采用干法蚀刻方式以第一光阻图案的第二部分为掩模蚀刻掉第一金属层；所述步骤4中的剥离第一光阻图案为将第一光阻图案的第二部分剥离掉。
所述步骤5中的绝缘层采用二氧化硅沉积而形成；所述步骤5中的第二金属层通过曝光、显影、蚀刻及光阻剥离制程形成栅极。
所述蚀刻为湿法蚀刻。
所述步骤6中的保护层采用二氧化硅或硅氮化合物沉积而形成；所述第二光阻图案通过灰阶、掩模、曝光、显影而形成。
所述步骤7中采用干法蚀刻方式蚀刻掉没有第二光阻图案覆盖的保护层及该部分保护层对应的绝缘层，进而形成接触孔。
本发明的有益效果：本发明的薄膜晶体管阵列基板的制造方法，该薄膜晶体管阵列基板采用顶栅结构，该薄膜晶体管阵列基板的制造方法通过3次掩模来制造TFT阵列基板，其中以铟镓锌氧化物来制造薄膜晶体管阵列基板中的薄膜晶体管，可以大大提高薄膜晶体管对像素电极的充电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在薄膜晶体管液晶显示器中成为可能；同时，该制造方法仅采用了3次掩模工艺，能显著的减少制程步骤，缩短制程时间，有效地降低生产成本，提高生产效率，增加产能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明薄膜晶体管阵列基板的制造方法的流程图；
图2为本发明中缓冲层、铟镓锌氧化物薄膜及第一金属层形成于基板上的结构示意图；
图3为本发明中第一光阻层形成于基板上的结构示意图；
图4为本发明中基板曝光后蚀刻掉没有第一光阻层覆盖的铟镓锌氧化物薄膜及第一金属层的结构示意图；
图5为本发明中基板灰化掉第一灰阶曝光区域的第一光阻层的结构示意图；
图6为本发明中基板蚀刻掉第一灰阶曝光区域的第一金属层的结构示意图；
图7为本发明中基板剥离掉第一光阻层的结构示意图；
图8为本发明中节点层及第二金属层沉积形成于基板上的结构示意图；
图9为本发明中基板上形成栅极的结构示意图；
图10为本发明中保护层形成于基板上的结构示意图；
图11为本发明中第二阻光层形成于基板上的结构示意图；
图12为本发明中基板形成接触孔的结构示意图；
图13为本发明中基板灰化掉第二灰阶曝光区域的第二光阻层的结构示意图；
图14为本发明中透明导电层形成于基板上的结构示意图；
图15为本发明中基本剥离掉第二正常曝光区域的第二光阻层及该部分第二光阻层上的透明导电层后的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1至图15，本发明提供一种薄膜晶体管阵列基板的制造方法，该薄膜晶体管阵列基板采用顶栅结构，该方法仅采用了3次掩模工艺，有效地降低生产成本，提高生产效率，增加产能。
该薄膜晶体管阵列基板的制造方法具体包括以下步骤：
步骤1、提供一基板21。
在本实施例中，所述基板21优选采用玻璃基板，然不限于此，也可以采用其它材质的基板，如塑料等。
步骤2、在所述基板21上依次沉积形成缓冲层22、氧化物半导体薄膜23及第一金属层24。
如图2所示，在本实施例中，所述缓冲层22采用二氧化硅沉积而形成，所述氧化物半导体薄膜23为铟镓锌氧化物薄膜。
步骤3、在所述第一金属层24上形成第一光阻层，图案化该第一光阻层以在预定位置形成第一光阻图案25，其包括对应氧化物半导体薄膜23的一沟道区的第一部分26、及第二部分27，该第一光阻图案25在第二部分27的厚度厚于第一部分26的厚度。
如图3所示，所述步骤3中的第一光阻图案25通过灰阶、掩模、曝光、显影而形成，且采用灰阶曝光形成第一光阻图案25的第一部分26。在该步骤中进行本发明中3次掩模工艺的第1次掩模工艺。
步骤4、蚀刻掉没有第一光阻图案25覆盖的区域的第一金属层24及氧化物半导体薄膜23，去掉第一光阻图案25的第一部分26以露出第一金属层24，以第一光阻图案25的第二部分27为掩模蚀刻掉第一金属层24以露出氧化物半导体薄膜23，剥离第一光阻图案25，以在第一金属层24形成源极27及漏极28。
在该步骤中，采用干法蚀刻方式以第一光阻图案25的第二部分27为掩模蚀刻掉第一金属层24，如图6所示，且，所述剥离第一光阻图案25为将第一光阻图案25的第二部分27剥离掉，如图7所示。
步骤5、在基板上依次沉积绝缘层31及第二金属层32，图案化第二金属层32以形成栅极33。
在本实施例中，所述绝缘层31优选采用二氧化硅沉积而形成。
请参阅图8及图9，该步骤中第二金属层32通过曝光、显影、蚀刻及光阻剥离制程形成栅极33。该步骤中对第二金属层32的曝光为一次普通的曝光，操作简单，方便快捷，有利于提高产能；该步骤中对第二金属层32的蚀刻为湿法蚀刻。在该步骤中进行本发明中3次掩模工艺的第2次掩模工艺。
步骤6、在所述基板上沉积保护层34，在所述保护层34上形成第二光阻层，图案化该第二光阻层以在预定位置形成第二光阻图案35，其包括位于漏极28一侧及部分漏极28上方的第三部分36、以及位于漏极28另一侧及部分漏极28上方的第四部分37，第二光阻图案35的第三部分36与第四部分37之间形成一凹部，如图10及图11所示。
在本实施例中，所述保护层34采用二氧化硅或硅氮化合物（SiNx）沉积而形成。所述第二光阻图案35通过灰阶、掩模、曝光、显影而形成，且采用灰阶曝光形成第二光阻图案35的第三部分36。所述第二光阻图案35相对漏极28形成一凹部，该凹部用于进行蚀刻，从而形成接触孔41。在该步骤中进行本发明中3次掩模工艺的第3次掩模工艺。
步骤7、蚀刻掉没有第二光阻图案35覆盖的保护层34及该部分保护层34对应的绝缘层31以露出漏极28，进而形成接触孔41，去掉第二光阻图案35的第三部分36，如图12及图13所示。
该步骤中采用干法蚀刻方式蚀刻掉没有第二光阻图案35覆盖的保护层34及该部分保护层34对应的绝缘层31，进而形成接触孔41，所述接触孔41位于第二光阻图案35的第三部分36与第四部分37之间，用于连接薄膜晶体管的漏极。
步骤8、在所述基板上沉积一透明导电层42，通过光阻剥离将第二光阻图案35的第四部分37及其上的透明导电层42剥离掉，如图14及图15所示。
所述透明导电层42用于耦接至所述薄膜晶体管的漏极，用来作为阵列基板中的存储电容的一电极。
步骤9、对所述基板进行退火处理，完成薄膜晶体管阵列基板的制造。
值得说明的是，本发明的技术方案不仅仅适用于TFT液晶显示器阵列基板的制作，同时也适用于其他涉及光学薄膜、电子薄膜等沉积的相关领域。
综上所述，本发明的薄膜晶体管阵列基板的制造方法，该薄膜晶体管阵列基板采用顶栅结构，该薄膜晶体管阵列基板的制造方法通过3次掩模来制造TFT阵列基板，其中以铟镓锌氧化物来制造薄膜晶体管阵列基板中的薄膜晶体管，可以大大提高薄膜晶体管对像素电极的充电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也大大提高了像素的行扫描速率，使得超高分辨率在薄膜晶体管液晶显示器中成为可能；同时，该制造方法仅采用了3次掩模工艺，能显著的减少制程步骤，缩短制程时间，有效地降低生产成本，提高生产效率，增加产能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (9)

1.一种薄膜晶体管阵列基板的制造方法，其特征在于，该薄膜晶体管阵列基板采用顶栅结构，所述薄膜晶体管阵列基板的制造方法包括以下步骤：
步骤1、提供一基板(21)；
步骤2、在所述基板(21)上依次沉积形成缓冲层(22)、氧化物半导体薄膜(23)及第一金属层(24)；
步骤3、在所述第一金属层(24)上形成第一光阻层，图案化该第一光阻层以在预定位置形成第一光阻图案(25)，其包括对应氧化物半导体薄膜(23)的一沟道区的第一部分(26)、及第二部分(27)，该第一光阻图案(25)在第二部分(27)的厚度厚于第一部分(26)的厚度；
步骤4、蚀刻掉没有第一光阻图案(25)覆盖的区域的第一金属层(24)及氧化物半导体薄膜(23)，去掉第一光阻图案(25)的第一部分(26)以露出第一金属层(24)，以第一光阻图案(25)的第二部分(27)为掩模蚀刻掉第一金属层(24)以露出氧化物半导体薄膜(23)，剥离第一光阻图案(25)，以在第一金属层(24)形成源极(27)及漏极(28)；
步骤5、在基板上依次沉积绝缘层(31)及第二金属层(32)，图案化第二金属层(32)以形成栅极(33)；
在步骤5之后的步骤6，在所述基板上沉积保护层(34)，在所述保护层(34)上形成第二光阻层，图案化该第二光阻层以在预定位置形成第二光阻图案(35)，其包括位于漏极(28)一侧及部分漏极(28)上方的第三部分(36)、以及位于漏极(28)另一侧及部分漏极(28)上方的第四部分(37)，第二光阻图案(35)的第三部分(36)与第四部分(37)之间形成一凹部；
在步骤6之后的步骤7，蚀刻掉没有第二光阻图案(35)覆盖的保护层(34)及该部分保护层(34)对应的绝缘层(31)以露出漏极(28)，进而形成接触孔(41)，去掉第二光阻图案(35)的第三部分(36)；
在步骤7之后的步骤8，在所述基板上沉积一透明导电层(42)，通过光阻剥离将第二光阻图案(35)的第四部分(37)及其上的透明导电层(42)剥离掉；
所述透明导电层(42)用于耦接至所述薄膜晶体管的漏极，用来作为阵列基板中的存储电容的一电极。
2.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，还包括在步骤8之后的步骤9，对所述基板进行退火处理，完成薄膜晶体管阵列基板的制造。
3.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述基板(21)为玻璃基板；所述缓冲层(22)采用二氧化硅沉积而形成；所述氧化物半导体薄膜(23)为铟镓锌氧化物薄膜。
4.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述步骤3中的第一光阻图案(25)通过灰阶、掩模、曝光、显影而形成。
5.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述步骤4中采用干法蚀刻方式以第一光阻图案(25)的第二部分(27)为掩模蚀刻掉第一金属层(24)；所述步骤4中的剥离第一光阻图案(25)为将第一光阻图案(25)的第二部分(27)剥离掉。
6.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述步骤5中的绝缘层(31)采用二氧化硅沉积而形成；所述步骤5中的第二金属层(32)通过曝光、显影、蚀刻及光阻剥离制程形成栅极(33)。
7.如权利要求6所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述蚀刻为湿法蚀刻。
8.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述步骤6中的保护层(34)采用二氧化硅或硅氮化合物沉积而形成；所述第二光阻图案(35)通过灰阶、掩模、曝光、显影而形成。
9.如权利要求1所述的薄膜晶体管阵列基板的制造方法，其特征在于，所述步骤7中采用干法蚀刻方式蚀刻掉没有第二光阻图案(35)覆盖的保护层(34)及该部分保护层对应的绝缘层(31)，进而形成接触孔(41)。
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