CN105097675A - 阵列基板及其制备方法 - Google Patents

阵列基板及其制备方法 Download PDF

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CN105097675A
CN105097675A CN201510609449.2A CN201510609449A CN105097675A CN 105097675 A CN105097675 A CN 105097675A CN 201510609449 A CN201510609449 A CN 201510609449A CN 105097675 A CN105097675 A CN 105097675A
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electrode
layer
doped region
grid
via hole
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CN105097675B (zh
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贺超
唐国强
郭远
李娟�
陈玉霞
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Wuhan China Star Optoelectronics Technology Co Ltd
TCL Huaxing Photoelectric Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201510609449.2A priority Critical patent/CN105097675B/zh
Priority to PCT/CN2015/091807 priority patent/WO2017049676A1/zh
Priority to US14/787,773 priority patent/US9728403B2/en
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Abstract

本发明提供一种阵列基板及其制备方法。本发明的阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本；本发明的阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了阵列基板的工艺制作成本。

Description

阵列基板及其制备方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
背景技术
在显示技术领域，平板显示技术已经逐步取代阴极射线管(CathodeRayTube，简称CRT)显示器。平板显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
薄膜晶体管(ThinFilmTransistor，简称TFT)是目前液晶显示装置(LiquidCrystalDisplay，简称LCD)和有源矩阵驱动式有机电致发光显示装置(ActiveMatrix/OrganicLight-EmittingDiode，简称AMOLED)中的主要驱动元件，直接关系到高性能平板显示装置的发展方向。薄膜晶体管具有多种结构，制备相应结构的薄膜晶体管有源层的材料也具有多种，其中，低温多晶硅(LowTemperaturePoly-silicon，简称LTPS)材料是其中较为优选的一种，由于低温多晶硅的原子规则排列，载流子迁移率高，对电压驱动式的液晶显示装置而言，低温多晶硅薄膜晶体管由于其具有较高的迁移率，可以使用体积较小的薄膜晶体管实现对液晶分子的偏转驱动，在很大程度上缩小了薄膜晶体管所占的体积，增加透光面积，得到更高的亮度和解析度；对于电流驱动式的有源矩阵驱动式有机电致发光显示装置而言，低温多晶硅薄膜晶体管可以更好的满足驱动电流要求。
因此，基于LTPSTFT的显示面板以其优越的高画质、高分辨率、超轻薄及低功耗等性能备受广大消费者喜爱，LTPS技术正在逐渐取代传统非晶硅(a-Si)TFT技术，成为新一代显示技术主流。但是现有的LTPS阵列基板制作制程复杂，生产制作成本高。
如图1所示，传统的互补金属氧化物半导体(ComplementaryMetalOxideSemiconductor，CMOS)LTPSTFT阵列基板，包括基板110、设于所述基板110上的遮光层120、设于所述基板110及遮光层120上的缓冲层130、设于所述缓冲层130上的有源层140、设于所述缓冲层140上的栅极绝缘层150、设于所述栅极绝缘层150上的栅极160、设于所述栅极160上的层间绝缘层170、设于所述层间绝缘层170上的源/漏极180、设于所述源/漏极180上的成平坦层190、设于平坦层190上的公共电极层200、设于公共电极层200上的绝缘层210、以及设于所属绝缘层210上的像素电极220；图2为图1的CMOS型LTPS阵列基板的俯视图，其中，公共电极层200为整面型电极；因此，传统的CMOS型LTPSTFT阵列基板的制作工艺，在栅极160形成后需要制作一层间绝缘层170用作栅极160与源/漏极180之间的绝缘层，制作制程复杂，生产成本高。
发明内容
本发明的目的在于提供一种阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本。
本发明的目的还在于提供一种阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了工艺制作成本。
为实现上述目的，本发明提供一种阵列基板的制备方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次形成遮光层、缓冲层，在所述缓冲层上形成多晶硅层，对所述多晶硅层的两端进行N型离子注入，得到位于所述多晶硅层两端的N型重掺杂区、及位于两N型重掺杂区之间的未掺杂区，在所述多晶硅层上沉积栅极绝缘层；
步骤2、在所述栅极绝缘层上涂布光刻胶，利用半灰阶掩模板对该光刻胶进行曝光、显影，得到光阻层，所述光阻层上对应所述N型重掺杂区上方设有通孔，并且所述光阻层上对应于所述未掺杂区上方的厚度大于其它区域的厚度；
步骤3、以光阻层为遮蔽层，对所述栅极绝缘层进行干法刻蚀，从而得到位于所述N型重掺杂区上方的第一过孔，对所述光阻层进行氧气灰化处理，经氧气灰化处理后，剩余的光阻层位于所述多晶硅层的未掺杂区的上方，且尺寸小于该未掺杂区的尺寸；
步骤4、以剩余的光阻层为遮蔽层，对所述未掺杂区的两端进行N型离子注入，在所述未掺杂区的两端形成N型轻掺杂区，定义两N型轻掺杂区之间的未掺杂区域为沟道区；去除光阻层，在所述栅极绝缘层上沉积形成金属层，图案化该金属层，得到栅极、源极、及漏极，所述栅极、源极、及漏极不相连，所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接；
步骤5、在所述栅极、源极、及漏极上形成平坦层，通过光刻制程在所述平坦层上形成对应于所述栅极上方的第二过孔、以及对应于所述漏极上方的第三过孔；
步骤6、在所述平坦层上形成一ITO薄膜，图案化该ITO薄膜，得到公共电极、及透明电极，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上。
所述步骤2中，所述半灰阶掩模板包括透光区、半透光区、及遮光区，在曝光过程中，所述透光区对应于所述N型重掺杂区上方，所述遮光区对应于所述未掺杂区上方。
所述步骤4中，进行沉积金属层之前，还包括对所述基板进行快速热退火处理。
所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
还包括步骤7、在所述公共电极、及透明电极上形成绝缘层，在所述绝缘层上形成像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
本发明还提供一种阵列基板，包括基板、设于所述基板上的遮光层、设于所述基板及遮光层上的缓冲层、设于所述缓冲层上的多晶硅层、设于所述多晶硅层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、源极、及漏极、设于所述栅极绝缘层、栅极、源极、及漏极上的平坦层、以及设于所述平坦层上的公共电极与透明电极；
所述多晶硅层包括位于中间的沟道区、及位于两端的N型重掺杂区；
所述栅极绝缘层上设有对应于所述N型重掺杂区上方的第一过孔，所述平坦层上设有对应于所述栅极上方的第二过孔、及对应于所述漏极上方的第三过孔，所述透明电极通过第二过孔与所述栅极相连接，从而栅极扫描信号可以通过该透明电极输入到栅极上。
所述多晶硅层还包括位于沟道区与N型重掺杂区之间的N型轻掺杂区；所述源极、及漏极分别通过第一过孔与所述N型重掺杂区相连接。
所述栅极、源极、及漏极通过同一金属层经光刻制程制得，所述公共电极与所述透明电极通过同一ITO薄膜经光刻制程制得。
所述缓冲层为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层的材料为低温多晶硅。
所述阵列基板还包括设于公共电极与透明电极上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层上的第三过孔与漏极相连接。
本发明的有益效果：本发明提供一种阵列基板及其制备方法，本发明的阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本；本发明的阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了阵列基板的工艺制作成本。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有CMOS型低温多晶硅薄膜晶体管阵列基板的结构示意图；
图2为图1的CMOS型低温多晶硅薄膜晶体管阵列基板的俯视图；
图3为本发明的阵列基板的制备方法步骤1的示意图；
图4为本发明的阵列基板的制备方法步骤2的示意图；
图5为本发明的阵列基板的制备方法步骤3的示意图；
图6为本发明的阵列基板的制备方法步骤4的示意图；
图7为本发明的阵列基板的制备方法步骤4的俯视示意图；
图8为本发明的阵列基板的制备方法步骤5的示意图；
图9为本发明的阵列基板的制备方法步骤6的示意图；
图10为本发明的阵列基板的制备方法步骤6的俯视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3-10，本发明提供一种阵列基板的制备方法，包括如下步骤：
步骤1、如图3所示，提供一基板11，在所述基板11上依次形成遮光层12、缓冲层13，在所述缓冲层13上形成多晶硅层14，对所述多晶硅层14的两端进行N型离子注入，得到位于所述多晶硅层14两端的N型重掺杂区141、及位于两N型重掺杂区141之间的未掺杂区145，在所述多晶硅层14上沉积栅极绝缘层15。
具体的，所述缓冲层12为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构。
具体的，所述多晶硅层14的材料为低温多晶硅。
步骤2、如图4所示，在所述栅极绝缘层15上涂布光刻胶，利用半灰阶掩模板对该光刻胶进行曝光、显影，得到光阻层50，所述光阻层50上对应所述N型重掺杂区141上方设有通孔51，并且所述光阻层50上对应于所述未掺杂区145上方的厚度大于其它区域的厚度。
具体的，所述半灰阶掩模板包括透光区、半透光区、及遮光区，在曝光过程中，所述透光区对应于所述N型重掺杂区141上方，用于在所述N型重掺杂区142上方的栅极绝缘层15上形成过孔，所述遮光区对应于所述未掺杂区145上方。
步骤3、如图5所示，以光阻层50为遮蔽层，对所述栅极绝缘层15进行干法刻蚀，从而得到位于所述N型重掺杂区141上方的第一过孔151，对所述光阻层50进行氧气灰化处理，经氧气灰化处理后，剩余的光阻层50位于所述多晶硅层14的未掺杂区145的上方，且尺寸小于该未掺杂区145的尺寸。
步骤4、如图6所示，以剩余的光阻层50为遮蔽层，对所述未掺杂区145的两端进行N型离子注入，在所述未掺杂区145的两端形成N型轻掺杂区142，定义两N型轻掺杂区142之间的未掺杂区域为沟道区143；去除光阻层50，在所述栅极绝缘层15上通过物理气相沉积法沉积形成金属层，图案化该金属层，得到栅极16、源极17、及漏极18，所述栅极16、源极17、及漏极18不相连，所述源极17、及漏极18分别通过第一过孔151与所述N型重掺杂区141相连接；此时，基板的俯视图如图7所示。
具体的，所述步骤4中，进行沉积金属层之前，还需要对所述基板11进行快速热退火(RTA,RapidThermalAnnealing)处理，以对多晶硅层14进行补氢和活化。
步骤5、如图8所示，在所述栅极16、源极17、及漏极18上形成平坦层19，通过光刻制程在所述平坦层19上形成对应于所述栅极16上方的第二过孔191、及对应于所述漏极18上方的第三过孔192。
步骤6、如图9所示，在所述平坦层19上形成一ITO薄膜，图案化该ITO薄膜，得到公共电极201、及透明电极202，所述透明电极202通过第二过孔191与所述栅极16相连接，从而栅极扫描信号可以通过该透明电极202输入到栅极16上，使得源极17与漏极18之间导通；此时，基板的俯视图如图10所示，具体的，透明电极202通过同一行内的第二过孔191将该行的栅极16进行连接，从而实现栅极扫描信号线的输入，并形成与所述源极17、及漏极18之间的垂直电路。
具体的，所述阵列基板的制作方法还包括步骤7、在所述公共电极201、及透明电极202上形成绝缘层，在所述绝缘层上形成像素电极，所述像素电极通过所述平坦层19上的第三过孔192与漏极18相连接。
请参阅图9-10，本发明还提供一种阵列基板，包括基板11、设于所述基板11上的遮光层12、设于所述基板11及遮光层12上的缓冲层13、设于所述缓冲层13上的多晶硅层14、设于所述多晶硅层14上的栅极绝缘层15、设于所述栅极绝缘层15上的栅极16、源极17、及漏极18、设于所述栅极绝缘层15、栅极16、源极17、及漏极18上的平坦层19、以及设于所述平坦层19上的公共电极201与透明电极202；
所述多晶硅层14包括位于中间的沟道区143、位于两端的N型重掺杂区141、以及位于沟道区143与N型重掺杂区141之间的N型轻掺杂区142；
所述栅极绝缘层15上设有对应于所述N型重掺杂区141上方的第一过孔151，所述平坦层19上设有对应于所述栅极16上方的第二过孔191、及对应于所述漏极18上方的第三过孔192，所述透明电极202通过第二过孔191与所述栅极16相连接，从而栅极扫描信号可以通过该透明电极202输入到栅极16上，使得源极17与漏极18之间导通。
具体的，所述源极17、及漏极18分别通过第一过孔151与所述N型重掺杂区141相连接。
具体的，所述阵列基板还包括设于公共电极201与透明电极202上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层19上的第三过孔192与漏极18相连接。
具体的，所述栅极16、源极17、及漏极18通过同一金属层经光刻制程制得，所述公共电极201与所述透明电极202通过同一ITO薄膜经光刻制程制得；
具体的，本发明的阵列基板为CMOS型低温多晶硅薄膜晶体管阵列基板；本发明的阵列基板可用于IPS(In-PlaneSwitching，平面转换)型液晶显示装置、或者FFS(FringeFieldSwitching，边缘场开关)型液晶显示装置。
具体的，所述缓冲层12为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构。
具体的，所述多晶硅层14的材料为低温多晶硅。
综上所述，本发明提供一种阵列基板及其制备方法，本发明的阵列基板的制备方法，将栅极与源漏极制作在同一金属层内，并将传统的整面型的公共电极层分割为两部分，其中一部分用作公共电极，另一部分用于实现栅极扫描信号输入，从而减少一道层间绝缘层制程，节省工艺制作成本；本发明的阵列基板，栅极与源漏极位于同一金属层内，栅极与源漏极之间不存在层间绝缘层，结构简化，从而降低了阵列基板的工艺制作成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

1.一种阵列基板的制备方法，其特征在于，包括如下步骤：
步骤1、提供一基板(11)，在所述基板(11)上依次形成遮光层(12)、缓冲层(13)，在所述缓冲层(13)上形成多晶硅层(14)，对所述多晶硅层(14)的两端进行N型离子注入，得到位于所述多晶硅层(14)两端的N型重掺杂区(141)、及位于两N型重掺杂区(141)之间的未掺杂区(145)，在所述多晶硅层(14)上沉积栅极绝缘层(15)；
步骤2、在所述栅极绝缘层(15)上涂布光刻胶，利用半灰阶掩模板对该光刻胶进行曝光、显影，得到光阻层(50)，所述光阻层(50)上对应所述N型重掺杂区(141)上方设有通孔(51)，并且所述光阻层(50)上对应于所述未掺杂区(145)上方的厚度大于其它区域的厚度；
步骤3、以光阻层(50)为遮蔽层，对所述栅极绝缘层(15)进行干法刻蚀，从而得到位于所述N型重掺杂区(141)上方的第一过孔(151)，对所述光阻层(50)进行氧气灰化处理，经氧气灰化处理后，剩余的光阻层(50)位于所述多晶硅层(14)的未掺杂区(145)的上方，且尺寸小于该未掺杂区(145)的尺寸；
步骤4、以剩余的光阻层(50)为遮蔽层，对所述未掺杂区(145)的两端进行N型离子注入，在所述未掺杂区(145)的两端形成N型轻掺杂区(142)，定义两N型轻掺杂区(142)之间的未掺杂区域为沟道区(143)；去除光阻层(50)，在所述栅极绝缘层(15)上沉积形成金属层，图案化该金属层，得到栅极(16)、源极(17)、及漏极(18)，所述栅极(16)、源极(17)、及漏极(18)不相连，所述源极(17)、及漏极(18)分别通过第一过孔(151)与所述N型重掺杂区(141)相连接；
步骤5、在所述栅极(16)、源极(17)、及漏极(18)上形成平坦层(19)，通过光刻制程在所述平坦层(19)上形成对应于所述栅极(16)上方的第二过孔(191)、以及对应于所述漏极(18)上方的第三过孔(192)；
步骤6、在所述平坦层(19)上形成一ITO薄膜，图案化该ITO薄膜，得到公共电极(201)、及透明电极(202)，所述透明电极(202)通过第二过孔(191)与所述栅极(16)相连接，从而栅极扫描信号可以通过该透明电极(202)输入到栅极(16)上。
2.如权利要求1所述的阵列基板的制备方法，其特征在于，所述步骤2中，所述半灰阶掩模板包括透光区、半透光区、及遮光区，在曝光过程中，所述透光区对应于所述N型重掺杂区(141)上方，所述遮光区对应于所述未掺杂区(145)上方。
3.如权利要求1所述的阵列基板的制备方法，其特征在于，所述步骤4中，进行沉积金属层之前，还需要对所述基板(11)进行快速热退火处理。
4.如权利要求1所述的阵列基板的制备方法，其特征在于，所述缓冲层(12)为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层(14)的材料为低温多晶硅。
5.如权利要求1所述的阵列基板的制备方法，其特征在于，还包括步骤7、在所述公共电极(201)、及透明电极(202)上形成绝缘层，在所述绝缘层上形成像素电极，所述像素电极通过所述平坦层(19)上的第三过孔(192)与漏极(18)相连接。
6.一种阵列基板，其特征在于，包括基板(11)、设于所述基板(11)上的遮光层(12)、设于所述基板(11)及遮光层(12)上的缓冲层(13)、设于所述缓冲层(13)上的多晶硅层(14)、设于所述多晶硅层(14)上的栅极绝缘层(15)、设于所述栅极绝缘层(15)上的栅极(16)、源极(17)、及漏极(18)、设于所述栅极绝缘层(15)、栅极(16)、源极(17)、及漏极(18)上的平坦层(19)、以及设于所述平坦层(19)上的公共电极(201)与透明电极(202)；
所述多晶硅层(14)包括位于所述多晶硅层(14)两端的N型重掺杂区(141)、及位于两N型重掺杂区(141)之间的沟道区(143)；
所述栅极绝缘层(15)上设有对应于所述N型重掺杂区(141)上方的第一过孔(151)，所述平坦层(19)上设有对应于所述栅极(16)上方的第二过孔(191)、及对应于所述漏极(18)上方的第三过孔(192)，所述透明电极(202)通过第二过孔(191)与所述栅极(16)相连接，从而栅极扫描信号可以通过该透明电极(202)输入到栅极(16)上。
7.如权利要求6所述的阵列基板，其特征在于，所述多晶硅层(14)还包括位于沟道区(143)与N型重掺杂区(141)之间的N型轻掺杂区(142)；所述源极(17)、及漏极(18)分别通过第一过孔(151)与所述N型重掺杂区(141)相连接。
8.如权利要求6所述的阵列基板，其特征在于，所述栅极(16)、源极(17)、及漏极(18)通过同一金属层经光刻制程制得，所述公共电极(201)与所述透明电极(202)通过同一ITO薄膜经光刻制程制得。
9.如权利要求8所述的阵列基板，其特征在于，所述缓冲层(12)为由氮化硅薄膜和氧化硅薄膜所组成的叠层结构；所述多晶硅层(14)的材料为低温多晶硅。
10.如权利要求6所述的阵列基板，其特征在于，所述阵列基板还包括设于公共电极(201)与透明电极(202)上的绝缘层、以及设于所述绝缘层上的像素电极，所述像素电极通过所述平坦层(19)上的第三过孔(192)与漏极(18)相连接。
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