CN105552027A - 阵列基板的制作方法及阵列基板 - Google Patents

阵列基板的制作方法及阵列基板 Download PDF

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Publication number
CN105552027A
CN105552027A CN201610084686.6A CN201610084686A CN105552027A CN 105552027 A CN105552027 A CN 105552027A CN 201610084686 A CN201610084686 A CN 201610084686A CN 105552027 A CN105552027 A CN 105552027A
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China
Prior art keywords
layer
via hole
grid
drain electrode
polysilicon section
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CN201610084686.6A
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CN105552027B (zh
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邓思
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to CN201610084686.6A priority Critical patent/CN105552027B/zh
Priority to PCT/CN2016/074791 priority patent/WO2017136967A1/zh
Priority to US15/031,279 priority patent/US10068933B2/en
Publication of CN105552027A publication Critical patent/CN105552027A/zh
Priority to US16/101,534 priority patent/US10504946B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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Abstract

本发明提供一种阵列基板的制作方法及阵列基板。本发明的阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层(90)来代替现有的氮化硅材料的钝化保护层，利用一道光罩对钝化保护层(90)和平坦层(70)进行曝光、显影处理，得到位于第一漏极(62)上方的第三过孔(91)、及位于第二漏极(64)上方的第四过孔(92)，与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。本发明的阵列基板，结构简单，制作成本低，且具有良好的电学性能。

Description

阵列基板的制作方法及阵列基板
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及阵列基板。
背景技术
随着显示技术的发展，液晶显示器(LiquidCrystalDisplay，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlightmodule)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，ColorFilter)基板、薄膜晶体管(TFT，ThinFilmTransistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，LiquidCrystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
低温多晶硅(LowTemperaturePolySilicon，LTPS)是广泛用于中小电子产品中的一种液晶显示技术。传统的非晶硅材料的电子迁移率约0.5-1.0cm2/V.S，而低温多晶硅的电子迁移率可达30-300cm2/V.S。因此，低温多晶硅液晶显示器具有高解析度、反应速度快、高开口率等诸多优点。但是另一方面，由于LTPS半导体器件的体积小、集成度高，所以整个LTPS阵列基板的制备工艺复杂，生产成本较高。
目前，业界主流的显示面板的阵列基板的钝化保护层(PV)通常采用氮化硅(分子式：SiNx)单层结构组成。氮化硅是一种良好的绝缘材料，其透光度较好，介电常数大约是6～9。
目前流行的LTPS阵列基板的制作流程中，对平坦层和钝化保护层进行图形化处理以形成像素电极与漏极的接触孔的方法如下：步骤1、如图1所示，首先形成平坦层(PLN)700，并利用光罩对平坦层700进行曝光显影处理，形成位于漏极620上方的第一通孔710；步骤2、如图2所示，在平坦层700上形成图形化的公共电极层(BITO)810，在公共电极层810上沉积氮化硅材料，形成钝化保护层900，利用曝光和蚀刻工艺对钝化保护层900进行图形化处理，在所述钝化保护层900上形成位于第一通孔710内的第二通孔910；所述第二通孔910用于实现像素电极与漏极620的接触。
然而上述制程需要使用两道光罩并进行一次蚀刻制程，生产成本较高，且工艺流程复杂。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，与现有技术相比，既节省一道光罩，又减少一道蚀刻制程，从而简化工艺流程、节约生产成本。
本发明的目的还在于提供一种阵列基板，结构简单，制作成本低，且具有良好的电学性能。
为实现上述目的，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层；
步骤2、在所述遮光层、及基板形成缓冲层，在所述缓冲层上形成非晶硅层，并对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层上方的第一多晶硅段、及与第一多晶硅段间隔设置的第二多晶硅段；
步骤3、利用光罩对所述第一多晶硅段的中间区域进行P型轻掺杂，得到第一沟道区，之后利用光罩对所述第一多晶硅段的两端进行N型重掺杂，得到位于两端的N型重掺杂区；
步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层，在栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在栅极绝缘层上得到分别对应于所述第一多晶硅段与第二多晶硅段中间区域的第一栅极绝缘层与第二栅极绝缘层，在第二金属层上得到分别位于所述第一、第二栅极绝缘层上方且与所述第一、第二栅极绝缘层对齐的第一栅极与第二栅极；
步骤5、利用第一栅极作为光罩对所述第一多晶硅段上位于第一沟道区与N型重掺杂区之间的区域进行N型轻掺杂，得到N型轻掺杂区，之后利用光罩对所述第二多晶硅段的两端进行P型重掺杂，得到位于两端的P型重掺杂区、及位于两P型重掺杂区之间的第二沟道区；
步骤6、在所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上沉积层间绝缘层，通过光刻制程对所述层间绝缘层进行图形化处理，在所述层间绝缘层上形成对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；
步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层；在所述平坦层上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共电极；
步骤9、在所述公共电极、及平坦层上沉积有机光阻材料，形成钝化保护层；
步骤10、利用光罩对所述钝化保护层、及平坦层进行曝光、显影，得到对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔；
步骤11、在所述钝化保护层上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触。
所述步骤2中，利用激光退火方法对非晶硅层进行结晶化处理。
所述步骤6还包括：对所述层间绝缘层进行去氢和活化处理。
通过快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
所述步骤9中，采用蒸镀或喷印的方法沉积有机光阻材料。
所述步骤9还包括：对所述钝化保护层进行紫外光照射处理，使所述钝化保护层薄化，以增加其透光性。
所述平坦层的材料为有机光阻，所述钝化保护层的介电常数为3～4。
所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
本发明还提供一种阵列基板，包括基板，位于基板上的遮光层，位于遮光层、及基板上的缓冲层，位于所述缓冲层上的第一多晶硅段与第二多晶硅段，分别位于第一多晶硅段与第二多晶硅段中间区域上方的第一栅极绝缘层与第二栅极绝缘层，分别位于所述第一栅极绝缘层与第二栅极绝缘层上方且与所述第一、第二栅极绝缘层对齐的第一栅极与第二栅极，位于所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上的层间绝缘层，位于层间绝缘层上的第一源极、第一漏极、第二源极、第二漏极，位于所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上的平坦层，位于平坦层上的公共电极，位于公共电极、及平坦层上的钝化保护层，以及位于钝化保护层上的像素电极；
所述第一多晶硅段包括对应所述第一栅极绝缘层下方的第一沟道区、位于两端的N型重掺杂区、及位于N型重掺杂区与第一沟道区之间的N型轻掺杂区；所述第二多晶硅段包括对应所述第二栅极绝缘层下方的第一沟道区、及位于两端的P型重掺杂区；
所述层间绝缘层上设有对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
所述平坦层与钝化保护层的材料均为有机光阻，所述钝化保护层及平坦层上设有对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触。
所述钝化保护层的介电常数为3～4；所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
本发明的有益效果：本发明的阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层来代替现有的氮化硅材料的钝化保护层，利用一道光罩对钝化保护层和平坦层进行曝光、显影处理，得到位于第一漏极上方的第三过孔、及位于第二漏极上方的第四过孔，与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。本发明的阵列基板，结构简单，制作成本低，且具有良好的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1-2为现有的阵列基板的制作方法中对平坦层和钝化保护层进行图形化处理的示意图；
图3为本发明的阵列基板的制作方法步骤1的示意图；
图4为本发明的阵列基板的制作方法步骤2的示意图；
图5为本发明的阵列基板的制作方法步骤3的示意图；
图6为本发明的阵列基板的制作方法步骤4的示意图；
图7为本发明的阵列基板的制作方法步骤5的示意图；
图8为本发明的阵列基板的制作方法步骤6的示意图；
图9为本发明的阵列基板的制作方法步骤7的示意图；
图10为本发明的阵列基板的制作方法步骤8的示意图；
图11为本发明的阵列基板的制作方法步骤9的示意图；
图12为本发明的阵列基板的制作方法步骤10的示意图；
图13为本发明的阵列基板的制作方法步骤11的示意图暨本发明的阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3-13，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供一基板10，在所述基板10上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层20。
具体的，所述基板10为透明基板，优选为玻璃基板。
步骤2、如图4所示，在所述遮光层20、及基板10形成缓冲层23，在所述缓冲层23上形成非晶硅层，利用激光退火方法对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层20上方的第一多晶硅段30、及与第一多晶硅段30间隔设置的第二多晶硅段40。
通过将第一多晶硅段30设置于遮光层20上方，从而有效防止光线进入第一多晶硅段30的沟道区中，可以起到降低漏电流、提高TFT器件电学性能的作用。所述第二多晶硅段40的沟道区在阵列基板完成后采用其它遮光材料在阵列基板外侧进行覆盖。
步骤3、如图5所示，利用光罩对所述第一多晶硅段30的中间区域进行P型轻掺杂，得到第一沟道区32，之后利用光罩对所述第一多晶硅段30的两端进行N型重掺杂，得到位于两端的N型重掺杂区31。
步骤4、如图6所示，在所述第一多晶硅段30、第二多晶硅段40、及缓冲层23上沉积栅极绝缘层，在所述栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在所述栅极绝缘层上得到分别对应于所述第一多晶硅段30与第二多晶硅段40中间区域的第一栅极绝缘层53与第二栅极绝缘层54，在第二金属层上得到分别位于所述第一、第二栅极绝缘层53、54上方且与所述第一、第二栅极绝缘层53、54对齐的第一栅极51与第二栅极52。
步骤5、如图7所示，利用第一栅极51为光罩对所述第一多晶硅段30上位于第一沟道区32与N型重掺杂区31之间的区域进行N型轻掺杂，得到N型轻掺杂区33，之后利用光罩对所述第二多晶硅段40的两端进行P型重掺杂，得到位于两端的P型重掺杂区41、及位于两P型重掺杂区41之间的第二沟道区42。
步骤6、如图8所示，在所述第一栅极51、第二栅极52、第一多晶硅段30、第二多晶硅段40、及缓冲层23上沉积层间绝缘层60，通过光刻制程对所述层间绝缘层60进行图形化处理，在所述层间绝缘层60上形成对应于N型重掺杂区31上方的第一过孔67、及对应于P型重掺杂区41上方的第二过孔68；之后对所述层间绝缘层60进行去氢和活化处理。
具体的，通过快速热退火工艺(RTA，RapidThermalAnnealing)对所述层间绝缘层60进行去氢和活化处理。
步骤7、如图9所示，在所述层间绝缘层60上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极61、第一漏极62、第二源极63、及第二漏极64；所述第一源极61、第一漏极62分别通过第一过孔67与N型重掺杂区31相接触，所述第二源极63、第二漏极64分别通过第二过孔68与P型重掺杂区41相接触。
步骤8、如图10所示，在所述第一源极61、第一漏极62、第二源极63、第二漏极64、及层间绝缘层60上涂布有机光阻材料，形成平坦层70；在所述平坦层70上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共(COM)电极81。
步骤9、如图11所示，在所述公共电极81、及平坦层70上采用蒸镀或喷印的方法沉积有机光阻材料，形成钝化保护层90。
进一步的，所述步骤10还可以包括：对所述钝化保护层90进行紫外光照射处理，使所述钝化保护层90薄化，以增加其透光性。
具体的，所述钝化保护层90的介电常数大约是3～4，与现有的介电常数大约是6～9的氮化硅材料的钝化保护层相比，可以通过降低所述钝化保护层90的膜厚来满足阵列基板的电容需求。
步骤10、如图12所示，利用光罩对所述钝化保护层90、及平坦层70进行曝光、显影，得到对应于第一漏极62上方的第三过孔91、及对应于第二漏极64上方的第四过孔92。
步骤11、如图13所示，在所述钝化保护层90上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极95，所述像素电极95分别通过第三过孔91、第四过孔92与第一漏极62、及第二漏极64相接触。
具体的，所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
具体的，所述缓冲层23、第一、第二栅极绝缘层53、54、层间绝缘层60为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述第一透明导电层、第二透明导电层的材料为金属氧化物，所述金属氧化物可以为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
所述P型轻掺杂与P型重掺杂掺入的离子可以为硼(B)离子或镓(Ga)离子；所述N型轻掺杂与N型重掺杂掺入的离子可以为磷(P)离子或砷(As)离子。
所述第一源极61、第一漏极62、第一栅极51与第一多晶硅段30构成NMOS(Negativechannel-Metal-Oxide-Semiconductor，N型金属氧化物半导体)晶体管；所述第二源极63、第二漏极64、第二栅极52与第二多晶硅段40构成PMOS(Positivechannel-Metal-Oxide-Semiconductor，P型金属氧化物半导体)晶体管。
上述阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层90来代替现有的氮化硅材料的钝化保护层，之后利用一道光罩对钝化保护层90和平坦层70进行曝光、显影处理，得到位于第一漏极62上方的第三过孔91、及位于第二漏极64上方的第四过孔92，与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到了简化工艺流程、以及节约生产成本的目的。
请参阅图13，同时参阅图3-12，本发明还提供一种阵列基板，包括基板10，位于基板10上的遮光层20，位于遮光层20、及基板10上的缓冲层23，位于所述缓冲层23上的第一多晶硅段30与第二多晶硅段40，分别位于第一多晶硅段30与第二多晶硅段40中间区域上方的第一栅极绝缘层53与第二栅极绝缘层54，分别位于所述第一栅极绝缘层53与第二栅极绝缘层54上方且与所述第一、第二栅极绝缘层53、54对齐的第一栅极51与第二栅极52，位于所述第一栅极51、第二栅极52、第一多晶硅段30、第二多晶硅段40、及缓冲层23上的层间绝缘层60，位于层间绝缘层60上的第一源极61、第一漏极62、第二源极63、第二漏极64，位于所述第一源极61、第一漏极62、第二源极63、第二漏极64、及层间绝缘层60上的平坦层70，位于平坦层70上的公共电极81，位于公共电极81、及平坦层70上的钝化保护层90，以及位于钝化保护层90上的像素电极95。
具体的，所述第一多晶硅段30包括对应所述第一栅极绝缘层53下方的第一沟道区32、位于两端的N型重掺杂区31、及位于N型重掺杂区31与第一沟道区32之间的N型轻掺杂区33；所述第二多晶硅段40包括对应所述第二栅极绝缘层54下方的第一沟道区41、及位于两端的P型重掺杂区42；所述N型重掺杂区31与N型轻掺杂区33中掺入的离子可以为磷(P)离子或砷(As)离子；所述P型重掺杂区41及第一沟道区32中掺入的离子可以为硼(B)离子或镓(Ga)离子。
具体的，所述层间绝缘层60上设有对应于N型重掺杂区31上方的第一过孔67、及对应于P型重掺杂区41上方的第二过孔68；所述第一源极61、第一漏极62分别通过第一过孔67与N型重掺杂区31相接触，所述第二源极63、第二漏极64分别通过第二过孔68与P型重掺杂区41相接触；
所述平坦层70与钝化保护层90的材料均为有机光阻，所述钝化保护层90及平坦层70上设有对应于第一漏极62上方的第三过孔91、及对应于第二漏极64上方的第四过孔92，所述像素电极95分别通过第三过孔91、第四过孔92与第一漏极62、及第二漏极64相接触。
具体的，所述第一源极61、第一漏极62、第一栅极51与第一多晶硅段30构成NMOS晶体管；所述第二源极63、第二漏极64、第二栅极52与第二多晶硅段40构成PMOS晶体管。
具体的，所述第一多晶硅段30对应于遮光层20上方设置，由于遮光层20的覆盖，可以有效防止光线进入第一多晶硅段30的第一沟道区32中，可以起到降低漏电流、提高TFT器件电学性能的作用。所述第二多晶硅段40的第二沟道区42在后续制程中采用其它遮光材料在阵列基板外侧进行覆盖。
具体的，所述基板10为透明基板，优选为玻璃基板。
所述遮光层20、第一栅极51、第二栅极52、、第一源极61、第一漏极62、第二源极63、第二漏极64的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
所述缓冲层23、第一、第二栅极绝缘层53、54、层间绝缘层60为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
所述公共电极81、及像素电极95的材料为金属氧化物，所述金属氧化物可以为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
具体的，所述钝化保护层90的介电常数大约是3～4，可以通过调节所述钝化保护层90的膜厚，从而达成阵列基板的电容需求。
上述阵列基板，通过采用由有机光阻材料制作的钝化保护层90来代替现有的氮化硅材料的钝化保护层，使得钝化保护层90和平坦层70上对应于第一漏极62上方的第三过孔91及对应于第二漏极64上方的第四过孔92可以利用一道光罩进行曝光形成，从而与现有的阵列基板的制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。
综上所述，本发明提供的一种阵列基板的制作方法及阵列基板。本发明的阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层90来代替现有的氮化硅材料的钝化保护层，利用一道光罩对钝化保护层90和平坦层70进行曝光、显影处理，得到位于第一漏极62上方的第三过孔91、及位于第二漏极64上方的第四过孔92，与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。本发明的阵列基板，结构简单，制作成本低，且具有良好的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种阵列基板的制作方法，其特征在于，包括如下步骤：
步骤1、提供一基板(10)，在所述基板(10)上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层(20)；
步骤2、在所述遮光层(20)、及基板(10)形成缓冲层(23)，在所述缓冲层(23)上形成非晶硅层，并对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层(20)上方的第一多晶硅段(30)、及与第一多晶硅段(30)间隔设置的第二多晶硅段(40)；
步骤3、利用光罩对所述第一多晶硅段(30)的中间区域进行P型轻掺杂，得到第一沟道区(32)，之后利用光罩对所述第一多晶硅段(30)的两端进行N型重掺杂，得到位于两端的N型重掺杂区(31)；
步骤4、在所述第一多晶硅段(30)、第二多晶硅段(40)、及缓冲层(23)上沉积栅极绝缘层，在栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在栅极绝缘层上得到分别对应于所述第一多晶硅段(30)与第二多晶硅段(40)中间区域的第一栅极绝缘层(53)与第二栅极绝缘层(54)，在第二金属层上得到分别位于所述第一、第二栅极绝缘层(53、54)上方且与所述第一、第二栅极绝缘层(53、54)对齐的第一栅极(51)与第二栅极(52)；
步骤5、利用第一栅极(51)作为光罩对所述第一多晶硅段(30)上位于第一沟道区(32)与N型重掺杂区(31)之间的区域进行N型轻掺杂，得到N型轻掺杂区(33)，之后利用光罩对所述第二多晶硅段(40)的两端进行P型重掺杂，得到位于两端的P型重掺杂区(41)、及位于两P型重掺杂区(41)之间的第二沟道区(42)；
步骤6、在所述第一栅极(51)、第二栅极(52)、第一多晶硅段(30)、第二多晶硅段(40)、及缓冲层(23)上沉积层间绝缘层(60)，通过光刻制程对所述层间绝缘层(60)进行图形化处理，在所述层间绝缘层(60)上形成对应于N型重掺杂区(31)上方的第一过孔(67)、及对应于P型重掺杂区(41)上方的第二过孔(68)；
步骤7、在所述层间绝缘层(60)上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极(61)、第一漏极(62)、第二源极(63)、及第二漏极(64)；所述第一源极(61)、第一漏极(62)分别通过第一过孔(67)与N型重掺杂区(31)相接触，所述第二源极(63)、第二漏极(64)分别通过第二过孔(68)与P型重掺杂区(41)相接触；
步骤8、在所述第一源极(61)、第一漏极(62)、第二源极(63)、第二漏极(64)、及层间绝缘层(60)上形成平坦层(70)；在所述平坦层(70)上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共电极(81)；
步骤9、在所述公共电极(81)、及平坦层(70)上沉积有机光阻材料，形成钝化保护层(90)；
步骤10、利用光罩对所述钝化保护层(90)、及平坦层(70)进行曝光、显影，得到对应于第一漏极(62)上方的第三过孔(91)、及对应于第二漏极(64)上方的第四过孔(92)；
步骤11、在所述钝化保护层(90)上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极(95)，所述像素电极(95)分别通过第三过孔(91)、第四过孔(92)与第一漏极(62)、及第二漏极(64)相接触。
2.如权利要求1所述的阵列基板的制作方法，其特征在于，所述步骤2中，利用激光退火方法对非晶硅层进行结晶化处理。
3.如权利要求1所述的阵列基板的制作方法，其特征在于，所述步骤6还包括：对所述层间绝缘层(60)进行去氢和活化处理。
4.如权利要求3所述的阵列基板的制作方法，其特征在于，通过快速热退火工艺对所述层间绝缘层(60)进行去氢和活化处理。
5.如权利要求1所述的阵列基板的制作方法，其特征在于，所述步骤9中，采用蒸镀或喷印的方法沉积有机光阻材料。
6.如权利要求1所述的阵列基板的制作方法，其特征在于，所述步骤9还包括：对所述钝化保护层(90)进行紫外光照射处理，使所述钝化保护层(90)薄化，以增加其透光性。
7.如权利要求1所述的阵列基板的制作方法，其特征在于，所述平坦层(70)的材料为有机光阻，所述钝化保护层(90)的介电常数为3～4。
8.如权利要求1所述的阵列基板的制作方法，其特征在于，所述基板(10)为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层(23)、第一、第二栅极绝缘层(53、54)、层间绝缘层(60)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
9.一种阵列基板，其特征在于，包括基板(10)，位于基板(10)上的遮光层(20)，位于遮光层(20)、及基板(10)上的缓冲层(23)，位于所述缓冲层(23)上的第一多晶硅段(30)与第二多晶硅段(40)，分别位于第一多晶硅段(30)与第二多晶硅段(40)中间区域上方的第一栅极绝缘层(53)与第二栅极绝缘层(54)，分别位于所述第一栅极绝缘层(53)与第二栅极绝缘层(54)上方且与所述第一、第二栅极绝缘层(53、54)对齐的第一栅极(51)与第二栅极(52)，位于所述第一栅极(51)、第二栅极(52)、第一多晶硅段(30)、第二多晶硅段(40)、及缓冲层(23)上的层间绝缘层(60)，位于层间绝缘层(60)上的第一源极(61)、第一漏极(62)、第二源极(63)、第二漏极(64)，位于所述第一源极(61)、第一漏极(62)、第二源极(63)、第二漏极(64)、及层间绝缘层(60)上的平坦层(70)，位于平坦层(70)上的公共电极(81)，位于公共电极(81)、及平坦层(70)上的钝化保护层(90)，以及位于钝化保护层(90)上的像素电极(95)；
所述第一多晶硅段(30)包括对应所述第一栅极绝缘层(53)下方的第一沟道区(32)、位于两端的N型重掺杂区(31)、及位于N型重掺杂区(31)与第一沟道区(32)之间的N型轻掺杂区(33)；所述第二多晶硅段(40)包括对应所述第二栅极绝缘层(54)下方的第一沟道区(41)、及位于两端的P型重掺杂区(42)；
所述层间绝缘层(60)上设有对应于N型重掺杂区(31)上方的第一过孔(67)、及对应于P型重掺杂区(41)上方的第二过孔(68)；所述第一源极(61)、第一漏极(62)分别通过第一过孔(67)与N型重掺杂区(31)相接触，所述第二源极(63)、第二漏极(64)分别通过第二过孔(68)与P型重掺杂区(41)相接触；
所述平坦层(70)与钝化保护层(90)的材料均为有机光阻，所述钝化保护层(90)及平坦层(70)上设有对应于第一漏极(62)上方的第三过孔(91)、及对应于第二漏极(64)上方的第四过孔(92)，所述像素电极(95)分别通过第三过孔(91)、第四过孔(92)与第一漏极(62)、及第二漏极(64)相接触。
10.如权利要求9所述的阵列基板，其特征在于，所述钝化保护层(90)的介电常数为3～4；所述基板(10)为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层(23)、第一、第二栅极绝缘层(53、54)、层间绝缘层(60)为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895581A (zh) * 2016-06-22 2016-08-24 武汉华星光电技术有限公司 Tft基板的制作方法
CN106653611A (zh) * 2016-12-27 2017-05-10 武汉华星光电技术有限公司 用于量测轻掺杂漏区长度的测试样本的制作方法及使用方法
CN106842685A (zh) * 2017-03-16 2017-06-13 惠科股份有限公司 一种显示面板及制造方法和显示装置
CN106910750A (zh) * 2017-04-24 2017-06-30 京东方科技集团股份有限公司 一种阵列基板、显示面板以及阵列基板的制作方法
CN107195562A (zh) * 2016-12-27 2017-09-22 武汉华星光电技术有限公司 量测阵列基板内轻掺杂漏区长度的方法
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法
CN108649036A (zh) * 2018-04-28 2018-10-12 武汉华星光电技术有限公司 一种阵列基板及其制作方法
CN109427874A (zh) * 2017-08-31 2019-03-05 株式会社日本显示器 显示装置及其制造方法
CN110690232A (zh) * 2019-10-23 2020-01-14 成都中电熊猫显示科技有限公司 阵列基板的制造方法、阵列基板及显示面板
CN111261644A (zh) * 2020-03-10 2020-06-09 Tcl华星光电技术有限公司 阵列基板及其制备方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017224676A (ja) * 2016-06-14 2017-12-21 株式会社ジャパンディスプレイ 半導体装置及び表示装置
CN106169473A (zh) * 2016-08-31 2016-11-30 深圳市华星光电技术有限公司 一种基于ltps的coms器件及其制作方法
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KR102599536B1 (ko) * 2017-01-26 2023-11-08 삼성전자 주식회사 생체 센서를 갖는 전자 장치
CN107046003B (zh) * 2017-06-02 2019-05-03 武汉华星光电技术有限公司 低温多晶硅tft基板及其制作方法
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CN112736094A (zh) * 2020-12-30 2021-04-30 武汉华星光电技术有限公司 显示面板及显示装置
CN113299674B (zh) * 2021-05-08 2022-09-09 武汉华星光电技术有限公司 阵列基板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040197967A1 (en) * 2003-04-04 2004-10-07 Kun-Hong Chen Method for forming a low temperature polysilicon CMOS thin film transistor
CN102109722A (zh) * 2009-12-28 2011-06-29 乐金显示有限公司 液晶显示器及其制造方法
US20130248870A1 (en) * 2011-06-30 2013-09-26 Lg Display Co., Ltd. Array substrate for fringe field switching mode liquid crystal display and method of manufacturing the same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3447535B2 (ja) * 1997-10-24 2003-09-16 シャープ株式会社 薄膜トランジスタおよびその製造方法
US6822264B2 (en) * 2001-11-16 2004-11-23 Semiconductor Energy Laboratory Co., Ltd. Light emitting device
JP4302347B2 (ja) * 2001-12-18 2009-07-22 シャープ株式会社 薄膜トランジスタ基板及びその製造方法
KR101084278B1 (ko) * 2009-11-05 2011-11-16 삼성모바일디스플레이주식회사 표시장치 및 표시장치의 제조방법
CN102522410B (zh) * 2011-12-22 2016-03-02 深圳莱宝高科技股份有限公司 一种薄膜晶体管阵列基板及其制作方法
CN102683354B (zh) * 2012-03-22 2014-12-17 京东方科技集团股份有限公司 顶栅型n-tft、阵列基板及其制备方法和显示装置
CN104656333A (zh) * 2015-03-18 2015-05-27 深圳市华星光电技术有限公司 Coa型液晶面板的制作方法及coa型液晶面板
CN105259723B (zh) * 2015-11-24 2017-04-05 武汉华星光电技术有限公司 用于液晶面板的阵列基板及其制作方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040197967A1 (en) * 2003-04-04 2004-10-07 Kun-Hong Chen Method for forming a low temperature polysilicon CMOS thin film transistor
CN102109722A (zh) * 2009-12-28 2011-06-29 乐金显示有限公司 液晶显示器及其制造方法
US20130248870A1 (en) * 2011-06-30 2013-09-26 Lg Display Co., Ltd. Array substrate for fringe field switching mode liquid crystal display and method of manufacturing the same

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105895581A (zh) * 2016-06-22 2016-08-24 武汉华星光电技术有限公司 Tft基板的制作方法
CN105895581B (zh) * 2016-06-22 2019-01-01 武汉华星光电技术有限公司 Tft基板的制作方法
CN107195562A (zh) * 2016-12-27 2017-09-22 武汉华星光电技术有限公司 量测阵列基板内轻掺杂漏区长度的方法
CN107195562B (zh) * 2016-12-27 2019-11-05 武汉华星光电技术有限公司 量测阵列基板内轻掺杂漏区长度的方法
CN106653611A (zh) * 2016-12-27 2017-05-10 武汉华星光电技术有限公司 用于量测轻掺杂漏区长度的测试样本的制作方法及使用方法
CN106842685A (zh) * 2017-03-16 2017-06-13 惠科股份有限公司 一种显示面板及制造方法和显示装置
US10725357B2 (en) 2017-03-16 2020-07-28 HKC Corporation Limited Display panel, method for manufacturing the display panel and display apparatus
WO2018171022A1 (zh) * 2017-03-16 2018-09-27 惠科股份有限公司 一种显示面板及制造方法和显示装置
CN106910750A (zh) * 2017-04-24 2017-06-30 京东方科技集团股份有限公司 一种阵列基板、显示面板以及阵列基板的制作方法
CN109427874A (zh) * 2017-08-31 2019-03-05 株式会社日本显示器 显示装置及其制造方法
CN109427874B (zh) * 2017-08-31 2021-07-27 株式会社日本显示器 显示装置及其制造方法
CN108538860A (zh) * 2018-04-27 2018-09-14 武汉华星光电技术有限公司 顶栅型非晶硅tft基板的制作方法
CN108649036A (zh) * 2018-04-28 2018-10-12 武汉华星光电技术有限公司 一种阵列基板及其制作方法
CN108649036B (zh) * 2018-04-28 2021-02-02 武汉华星光电技术有限公司 一种阵列基板及其制作方法
US11152490B2 (en) 2018-04-28 2021-10-19 Wuhan China Star Optoelectronics Technology Co., Ltd. Array substrate and method for manufacturing same
CN110690232A (zh) * 2019-10-23 2020-01-14 成都中电熊猫显示科技有限公司 阵列基板的制造方法、阵列基板及显示面板
CN111261644A (zh) * 2020-03-10 2020-06-09 Tcl华星光电技术有限公司 阵列基板及其制备方法

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