WO2017136967A1 - 阵列基板的制作方法及阵列基板 - Google Patents

阵列基板的制作方法及阵列基板 Download PDF

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WO2017136967A1
WO2017136967A1 PCT/CN2016/074791 CN2016074791W WO2017136967A1 WO 2017136967 A1 WO2017136967 A1 WO 2017136967A1 CN 2016074791 W CN2016074791 W CN 2016074791W WO 2017136967 A1 WO2017136967 A1 WO 2017136967A1
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Prior art keywords
layer
drain
polysilicon segment
insulating layer
heavily doped
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PCT/CN2016/074791
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English (en)
French (fr)
Inventor
邓思
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武汉华星光电技术有限公司
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Application filed by 武汉华星光电技术有限公司 filed Critical 武汉华星光电技术有限公司
Priority to US15/031,279 priority Critical patent/US10068933B2/en
Publication of WO2017136967A1 publication Critical patent/WO2017136967A1/zh

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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134372—Electrodes characterised by their geometrical arrangement for fringe field switching [FFS] where the common electrode is not patterned
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G02F1/13685—Top gates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/104—Materials and properties semiconductor poly-Si

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate and an array substrate.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor substrate, and a sealant frame ( Sealant),
  • the molding process generally includes: front array (Array) process (film, yellow, etching and stripping), middle cell (Cell) process (TFT substrate and CF substrate bonding) and rear module assembly Process (drive IC and printed circuit board is pressed).
  • the front Array process mainly forms a TFT substrate to control the movement of liquid crystal molecules;
  • the middle Cell process mainly adds liquid crystal between the TFT substrate and the CF substrate;
  • the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate and display images.
  • Low Temperature Poly Silicon is a liquid crystal display technology widely used in small and medium-sized electronic products.
  • Conventional amorphous silicon materials have an electron mobility of about 0.5-1.0 cm 2 /VS, while low-temperature polysilicon has an electron mobility of 30-300 cm 2 /VS. Therefore, the low-temperature polycrystalline silicon liquid crystal display has many advantages such as high resolution, fast reaction speed, and high aperture ratio.
  • the preparation process of the entire LTPS array substrate is complicated and the production cost is high.
  • the passivation protective layer (PV) of the array substrate of the mainstream display panel of the industry is usually composed of a single layer structure of silicon nitride (molecular formula: SiN x ). Silicon nitride is a good insulating material with good transparency and a dielectric constant of about 6-9.
  • Step 1 First, as shown in FIG. (PLN) 700, and performing exposure and development processing on the flat layer 700 by using a photomask to form a first via hole 710 over the drain electrode 620; and step 2, forming a patterned common on the flat layer 700 as shown in FIG.
  • PPN photomask
  • a second via 910 is formed on the first via 710. The second via 910 is used to achieve contact between the pixel electrode and the drain 620.
  • An object of the present invention is to provide a method for fabricating an array substrate, which saves a mask and reduces an etching process compared with the prior art, thereby simplifying the process flow and saving production costs.
  • the present invention provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a light shielding layer;
  • Step 2 forming a buffer layer on the light shielding layer and the substrate, forming an amorphous silicon layer on the buffer layer, and performing crystallization treatment on the amorphous silicon layer to form a polysilicon layer, using a photolithography process
  • the polysilicon layer is patterned to obtain a first polysilicon segment corresponding to the upper portion of the light shielding layer and a second polysilicon segment spaced apart from the first polysilicon segment;
  • Step 3 performing P-type light doping on the intermediate portion of the first polysilicon segment by using a photomask to obtain a first channel region, and then performing N on both ends of the first polysilicon segment by using a photomask. Type heavily doped to obtain N-type heavily doped regions at both ends;
  • Step 4 depositing a gate insulating layer on the first polysilicon segment, the second polysilicon segment, and the buffer layer, depositing a second metal layer on the gate insulating layer, and performing the photolithography process on the gate
  • the first insulating layer and the second metal layer are patterned, and the first gate insulating layer and the second corresponding to the intermediate regions of the first polysilicon segment and the second polysilicon segment are respectively obtained on the gate insulating layer
  • a gate insulating layer on the second metal layer is respectively located above the first and second gate insulating layers and is opposite to the first a first gate and a second gate aligned with the second gate insulating layer;
  • Step 5 performing N-type light doping on the region between the first channel region and the N-type heavily doped region on the first polysilicon segment by using the first gate as a photomask to obtain N-type light doping. a hetero region, and then P-type heavily doping the two ends of the second polysilicon segment with a photomask to obtain a P-type heavily doped region at both ends and a P-type heavily doped region between the two P-type regions Two-channel region
  • Step 6 depositing an interlayer insulating layer on the first gate, the second gate, the first polysilicon segment, the second polysilicon segment, and the buffer layer, and insulating the interlayer by a photolithography process Forming a layer, forming a first via corresponding to the upper portion of the N-type heavily doped region on the interlayer insulating layer, and a second via corresponding to the upper portion of the P-type heavily doped region;
  • Step 7 depositing a third metal layer on the interlayer insulating layer, and patterning the third metal layer to obtain first spaced source, first drain, second source, and a second drain; the first source and the first drain are respectively in contact with the N-type heavily doped region through the first via, and the second source and the second drain respectively pass through the second via and P Type heavily doped regions are in contact;
  • Step 8 forming a planarization layer on the first source, the first drain, the second source, the second drain, and the interlayer insulating layer; depositing a first transparent conductive layer on the planar layer, The first transparent conductive layer is patterned to obtain a common electrode;
  • Step 9 depositing an organic photoresist material on the common electrode and the flat layer to form a passivation protective layer
  • Step 10 exposing and developing the passivation protective layer and the flat layer by using a photomask to obtain a third via corresponding to the first drain and a fourth via corresponding to the second drain;
  • Step 11 depositing a second transparent conductive layer on the passivation protective layer, and patterning the second transparent conductive layer to obtain a pixel electrode, wherein the pixel electrode passes through the third via hole and the fourth via hole respectively Contact with the first drain and the second drain.
  • the amorphous silicon layer is crystallized by a laser annealing method.
  • the step 6 further includes: performing dehydrogenation and activation treatment on the interlayer insulating layer.
  • the interlayer insulating layer is subjected to dehydrogenation and activation treatment by a rapid thermal annealing process.
  • the organic photoresist material is deposited by evaporation or printing.
  • the step 9 further includes: performing ultraviolet light irradiation treatment on the passivation protective layer to thin the passivation protective layer to increase light transmittance thereof.
  • the material of the flat layer is an organic photoresist, and the passivation protective layer has a dielectric constant of 3 to 4.
  • the substrate is a transparent substrate; the material of the first metal layer, the second metal layer and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, copper; the buffer layer, the first 1.
  • the second gate insulating layer and the interlayer insulating layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first transparent conductive layer and the second transparent layer Conductive layer
  • the material is a metal oxide.
  • the present invention also provides an array substrate, comprising a substrate, a light shielding layer on the substrate, a buffer layer on the light shielding layer and the substrate, and a first polysilicon segment and a second polysilicon segment on the buffer layer a first gate insulating layer and a second gate insulating layer respectively located above the intermediate portion of the first polysilicon segment and the second polysilicon segment, respectively located at the first gate insulating layer and the second gate insulating a first gate and a second gate above the layer and aligned with the first and second gate insulating layers, located at the first gate, the second gate, the first polysilicon segment, and the second plurality a crystalline silicon segment and an interlayer insulating layer on the buffer layer, a first source, a first drain, a second source, and a second drain on the interlayer insulating layer, located at the first source, a drain, a second source, a second drain, and a planar layer on the interlayer insulating layer, a common electrode on the planar
  • the first polysilicon segment includes a first channel region under the first gate insulating layer, an N-type heavily doped region at both ends, and an N-type heavily doped region and a first channel region.
  • the second polysilicon segment includes a first channel region corresponding to the second gate insulating layer, and a P-type heavily doped region at both ends;
  • the interlayer insulating layer is provided with a first via corresponding to the upper portion of the N-type heavily doped region and a second via corresponding to the upper portion of the P-type heavily doped region; the first source and the first drain The poles are respectively in contact with the N-type heavily doped region through the first via, and the second source and the second drain are respectively in contact with the P-type heavily doped region through the second via;
  • the material of the flat layer and the passivation protective layer are both organic photoresists, and the passivation protective layer and the flat layer are provided with a third via corresponding to the first drain and corresponding to the second drain
  • the fourth via hole, the pixel electrode is in contact with the first drain and the second drain through the third via and the fourth via, respectively.
  • the passivation protective layer has a dielectric constant of 3 to 4; the substrate is a transparent substrate; and the materials of the first metal layer, the second metal layer, and the third metal layer are molybdenum, titanium, aluminum, and copper.
  • the buffer layer, the first and second gate insulating layers, the interlayer insulating layer being a silicon oxide layer, a silicon nitride layer, or a silicon oxide layer and a silicon nitride layer
  • the composite layer of the first transparent conductive layer and the second transparent conductive layer is a metal oxide.
  • the invention also provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 Providing a substrate, depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a light shielding layer;
  • Step 2 forming a buffer layer on the light shielding layer and the substrate, forming an amorphous silicon layer on the buffer layer, and performing crystallization treatment on the amorphous silicon layer to form a polysilicon layer, using a photolithography process
  • the polysilicon layer is patterned to obtain a first polysilicon segment corresponding to the upper portion of the light shielding layer, And a second polysilicon segment spaced apart from the first polysilicon segment;
  • Step 3 performing P-type light doping on the intermediate portion of the first polysilicon segment by using a photomask to obtain a first channel region, and then performing N on both ends of the first polysilicon segment by using a photomask. Type heavily doped to obtain N-type heavily doped regions at both ends;
  • Step 4 depositing a gate insulating layer on the first polysilicon segment, the second polysilicon segment, and the buffer layer, depositing a second metal layer on the gate insulating layer, and performing the photolithography process on the gate
  • the first insulating layer and the second metal layer are patterned, and the first gate insulating layer and the second corresponding to the intermediate regions of the first polysilicon segment and the second polysilicon segment are respectively obtained on the gate insulating layer a gate insulating layer, on the second metal layer, first and second gates respectively located above the first and second gate insulating layers and aligned with the first and second gate insulating layers ;
  • Step 5 performing N-type light doping on the region between the first channel region and the N-type heavily doped region on the first polysilicon segment by using the first gate as a photomask to obtain N-type light doping. a hetero region, and then P-type heavily doping the two ends of the second polysilicon segment with a photomask to obtain a P-type heavily doped region at both ends and a P-type heavily doped region between the two P-type regions Two-channel region
  • Step 6 depositing an interlayer insulating layer on the first gate, the second gate, the first polysilicon segment, the second polysilicon segment, and the buffer layer, and insulating the interlayer by a photolithography process Forming a layer, forming a first via corresponding to the upper portion of the N-type heavily doped region on the interlayer insulating layer, and a second via corresponding to the upper portion of the P-type heavily doped region;
  • Step 7 depositing a third metal layer on the interlayer insulating layer, and patterning the third metal layer to obtain first spaced source, first drain, second source, and a second drain; the first source and the first drain are respectively in contact with the N-type heavily doped region through the first via, and the second source and the second drain respectively pass through the second via and P Type heavily doped regions are in contact;
  • Step 8 forming a planarization layer on the first source, the first drain, the second source, the second drain, and the interlayer insulating layer; depositing a first transparent conductive layer on the planar layer, The first transparent conductive layer is patterned to obtain a common electrode;
  • Step 9 depositing an organic photoresist material on the common electrode and the flat layer to form a passivation protective layer
  • Step 10 exposing and developing the passivation protective layer and the flat layer by using a photomask to obtain a third via corresponding to the first drain and a fourth via corresponding to the second drain;
  • Step 11 depositing a second transparent conductive layer on the passivation protective layer, and patterning the second transparent conductive layer to obtain a pixel electrode, wherein the pixel electrode passes through the third via hole and the fourth via hole respectively Contacting the first drain and the second drain;
  • the amorphous silicon layer is crystallized by a laser annealing method
  • the step 6 further includes: performing dehydrogenation and activation treatment on the interlayer insulating layer.
  • the method for fabricating the array substrate of the present invention replaces the passivation protective layer of the existing silicon nitride material by using a passivation protective layer made of an organic photoresist material, and is passivated by a mask.
  • the protective layer and the flat layer are exposed and developed to obtain a third via located above the first drain and a fourth via above the second drain, which saves compared to the corresponding processes of the prior art.
  • a reticle reduces the etching process to simplify the process and save production costs.
  • the array substrate of the invention has simple structure, low fabrication cost and good electrical properties.
  • 1-2 is a schematic diagram of patterning a flat layer and a passivation protective layer in a method for fabricating a conventional array substrate;
  • FIG. 3 is a schematic view showing the first step of the method for fabricating the array substrate of the present invention.
  • step 2 is a schematic diagram of step 2 of the method for fabricating an array substrate of the present invention.
  • step 3 is a schematic diagram of step 3 of the method for fabricating an array substrate of the present invention.
  • step 4 is a schematic diagram of step 4 of the method for fabricating an array substrate of the present invention.
  • step 5 is a schematic diagram of step 5 of the method for fabricating an array substrate of the present invention.
  • step 6 is a schematic diagram of step 6 of the method for fabricating an array substrate of the present invention.
  • step 7 of the method for fabricating an array substrate of the present invention is a schematic diagram of step 7 of the method for fabricating an array substrate of the present invention.
  • step 8 is a schematic diagram of step 8 of the method for fabricating an array substrate of the present invention.
  • FIG. 11 is a schematic view showing the step 9 of the method for fabricating the array substrate of the present invention.
  • FIG. 12 is a schematic view showing a step 10 of a method for fabricating an array substrate according to the present invention.
  • FIG. 13 is a schematic view showing the step 11 of the method for fabricating the array substrate of the present invention and a schematic structural view of the array substrate of the present invention.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step 1 as shown in FIG. 3, a substrate 10 is provided, a first metal layer is deposited on the substrate 10, and the first metal layer is patterned to obtain a light shielding layer 20.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • Step 2 as shown in FIG. 4, a buffer layer 23 is formed on the light shielding layer 20 and the substrate 10, an amorphous silicon layer is formed on the buffer layer 23, and the amorphous silicon layer is crystallized by a laser annealing method.
  • the first polysilicon segment 30 By disposing the first polysilicon segment 30 above the light shielding layer 20, the light is effectively prevented from entering the channel region of the first polysilicon segment 30, which can reduce the leakage current and improve the electrical performance of the TFT device.
  • the channel region of the second polysilicon segment 40 is covered on the outside of the array substrate by using other light shielding materials after the array substrate is completed.
  • Step 3 as shown in FIG. 5, P-type light doping of the intermediate portion of the first polysilicon segment 30 by using a photomask to obtain a first channel region 32, and then using the photomask to the first plurality Both ends of the crystalline silicon segment 30 are heavily doped with an N-type to obtain an N-type heavily doped region 31 at both ends.
  • Step 4 depositing a gate insulating layer on the first polysilicon segment 30, the second polysilicon segment 40, and the buffer layer 23, and depositing a second layer on the gate insulating layer a metal layer, wherein the gate insulating layer and the second metal layer are patterned by a photolithography process, and corresponding to the first polysilicon segment 30 and the second polycrystalline layer respectively on the gate insulating layer a first gate insulating layer 53 and a second gate insulating layer 54 in an intermediate portion of the silicon segment 40 are formed on the second metal layer above the first and second gate insulating layers 53, 54 respectively
  • the first and second gate insulating layers 53, 54 are aligned with the first gate 51 and the second gate 52.
  • Step 5 using the first gate 51 as a reticle to perform a region on the first polysilicon segment 30 between the first channel region 32 and the N-type heavily doped region 31.
  • Step 6 depositing an interlayer insulating layer on the first gate 51, the second gate 52, the first polysilicon segment 30, the second polysilicon segment 40, and the buffer layer 23.
  • the interlayer insulating layer 60 is patterned by a photolithography process, and a first via 67 corresponding to the upper portion of the N-type heavily doped region 31 is formed on the interlayer insulating layer 60, and corresponds to P A second via 68 above the heavily doped region 41; the inter-layer insulating layer 60 is then subjected to dehydrogenation and activation treatment.
  • the interlayer insulating layer 60 is subjected to dehydrogenation and activation treatment by a Rapid Thermal Annealing (RTA) process.
  • RTA Rapid Thermal Annealing
  • Step 7 depositing a third metal layer on the interlayer insulating layer 60, and patterning the third metal layer to obtain a first source 61 and a first drain which are spaced apart 62.
  • the second source 63 and the second drain 64 are respectively in contact with the N-type heavily doped region 31 through the first via 67, and the second The source 63 and the second drain 64 are in contact with the P-type heavily doped region 41 through the second via 68, respectively.
  • Step 8 an organic photoresist material is coated on the first source 61, the first drain 62, the second source 63, the second drain 64, and the interlayer insulating layer 60, A flat layer 70 is formed; a first transparent conductive layer is deposited on the flat layer 70, and the first transparent conductive layer is patterned to obtain a common (COM) electrode 81.
  • COM common
  • Step 9 an organic photoresist material is deposited on the common electrode 81 and the flat layer 70 by evaporation or printing to form a passivation protective layer 90.
  • the step 10 may further include: performing ultraviolet light irradiation treatment on the passivation protective layer 90 to thin the passivation protective layer 90 to increase its light transmittance.
  • the passivation protective layer 90 has a dielectric constant of about 3-4, which can be reduced by reducing the passivation protective layer of the silicon nitride material having a dielectric constant of about 6-9.
  • the film thickness of the passivation protective layer 90 is made to satisfy the capacitance requirement of the array substrate.
  • Step 10 the passivation protective layer 90 and the flat layer 70 are exposed and developed by a photomask to obtain a third via 91 corresponding to the upper portion of the first drain 62, and corresponding to the first A fourth via 92 above the second drain 64.
  • Step 11 As shown in FIG. 13, a second transparent conductive layer is deposited on the passivation protective layer 90, and the second transparent conductive layer is patterned to obtain a pixel electrode 95.
  • the pixel electrode 95 passes through
  • the third via 91 and the fourth via 92 are in contact with the first drain 62 and the second drain 64.
  • the material of the first metal layer, the second metal layer, and the third metal layer is a stack combination of one or more of molybdenum, titanium, aluminum, and copper.
  • the buffer layer 23, the first and second gate insulating layers 53, 54 and the interlayer insulating layer 60 are a silicon oxide layer, a silicon nitride layer, or a silicon oxide layer and a silicon nitride layer. Composite layer.
  • the material of the first transparent conductive layer and the second transparent conductive layer is a metal oxide
  • the metal oxide may be indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, One or more of indium antimony zinc oxide.
  • the P-type lightly doped and P-type heavily doped doped ions may be boron (B) ions or gallium (Ga) ions; the N-type lightly doped and N-type heavily doped ions may be Phosphorus (P) ions or arsenic (As) ions.
  • the first source 61, the first drain 62, the first gate 51 and the first polysilicon segment 30 constitute An NMOS (Negative channel-Metal-Oxide-Semiconductor) transistor; the second source 63, the second drain 64, the second gate 52, and the second polysilicon segment 40 form a PMOS ( Positive channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor) transistor.
  • NMOS Negative channel-Metal-Oxide-Semiconductor
  • PMOS Positive channel-Metal-Oxide-Semiconductor, P-type metal oxide semiconductor
  • the method for fabricating the above array substrate is to replace the passivation protective layer of the existing silicon nitride material by using a passivation protective layer 90 made of an organic photoresist material, and then passivating the protective layer 90 and the flat layer with a mask.
  • the exposure and development processes are performed to obtain a third via 91 above the first drain 62 and a fourth via 92 above the second drain 64, which saves compared to the corresponding processes of the prior art.
  • a mask reduces the etching process, which simplifies the process and saves production costs.
  • the present invention further provides an array substrate, including a substrate 10 , a light shielding layer 20 on the substrate 10 , a buffer layer 23 on the light shielding layer 20 , and the substrate 10 .
  • the first polysilicon segment 30 and the second polysilicon segment 40 on the buffer layer 23 are respectively located on the first gate insulating layer 53 above the intermediate region of the first polysilicon segment 30 and the second polysilicon segment 40.
  • a second gate insulating layer 54 respectively located above the first gate insulating layer 53 and the second gate insulating layer 54 and aligned with the first and second gate insulating layers 53 , 54 a pole 51 and a second gate 52, and an interlayer insulating layer on the first gate 51, the second gate 52, the first polysilicon segment 30, the second polysilicon segment 40, and the buffer layer 23 60, the first source 61, the first drain 62, the second source 63, and the second drain 64 on the interlayer insulating layer 60 are located at the first source 61, the first drain 62, and the first a second source 63, a second drain 64, and a flat layer 70 on the interlayer insulating layer 60, a common electrode 81 on the flat layer 70, a passivation protective layer 90 on the common electrode 81, and the flat layer 70, And a pixel electrode 95 on the passivation protective layer 90.
  • the first polysilicon segment 30 includes a first channel region 32 corresponding to the first gate insulating layer 53 , an N-type heavily doped region 31 at both ends, and an N-type heavily doped region.
  • the second polysilicon segment 40 includes a first channel region 41 corresponding to the lower portion of the second gate insulating layer 54, and a P-type heavily doped region 42 at both ends;
  • the ions doped in the N-type heavily doped region 31 and the N-type lightly doped region 33 may be phosphorus (P) ions or arsenic (As) ions;
  • the ions doped in the heavily doped region 41 and the first channel region 32 may be boron (B) ions or gallium (Ga) ions.
  • the interlayer insulating layer 60 is provided with a first via 67 corresponding to the upper portion of the N-type heavily doped region 31, and a second via 68 corresponding to the upper portion of the P-type heavily doped region 41;
  • the first source 61 and the first drain 62 are respectively in contact with the N-type heavily doped region 31 through the first via 67, and the second source 63 and the second drain 64 are respectively passed through the second via 68.
  • the P-type heavily doped region 41 is in contact;
  • the material of the flat layer 70 and the passivation protective layer 90 are both organic photoresists, and the passivation protection
  • the layer 90 and the flat layer 70 are provided with a third via 91 corresponding to the upper portion of the first drain 62 and a fourth via 92 corresponding to the second drain 64.
  • the pixel electrodes 95 pass through the third pass respectively.
  • the hole 91 and the fourth via 92 are in contact with the first drain 62 and the second drain 64.
  • the first source 61, the first drain 62, the first gate 51 and the first polysilicon segment 30 constitute an NMOS transistor; the second source 63, the second drain 64, and the second The gate 52 and the second polysilicon segment 40 form a PMOS transistor.
  • the first polysilicon segment 30 is disposed above the light shielding layer 20, and the light shielding layer 20 can effectively prevent light from entering the first channel region 32 of the first polysilicon segment 30.
  • the second channel region 42 of the second polysilicon segment 40 is covered on the outside of the array substrate by using other light shielding materials in a subsequent process.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the light shielding layer 20, the first gate 51, the second gate 52, the first source 61, the first drain 62, the second source 63, and the second drain 64 may be molybdenum (Mo)
  • Mo molybdenum
  • the buffer layer 23, the first and second gate insulating layers 53, 54 and the interlayer insulating layer 60 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a silicon oxide layer and nitride.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • the material of the common electrode 81 and the pixel electrode 95 is a metal oxide, and the metal oxide may be indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium antimony zinc oxide. One or more.
  • the passivation protective layer 90 has a dielectric constant of about 3-4, and the capacitance of the passivation protective layer 90 can be adjusted to achieve the capacitance requirement of the array substrate.
  • the above array substrate is replaced with a passivation protective layer of an existing silicon nitride material by using a passivation protective layer 90 made of an organic photoresist material, so that the passivation protective layer 90 and the flat layer 70 correspond to the first drain.
  • the third via 91 above the 62 and the fourth via 92 above the second drain 64 can be exposed by a photomask, thereby saving a mask compared to the existing array substrate process. Moreover, an etching process is reduced, thereby simplifying the process flow and saving production costs.
  • the present invention provides an array substrate manufacturing method and an array substrate.
  • the method for fabricating the array substrate of the present invention replaces the passivation protective layer of the existing silicon nitride material by using the passivation protective layer 90 made of an organic photoresist material, and uses a mask to passivate the protective layer 90 and flatten
  • the layer 70 is exposed and developed to obtain a third via 91 above the first drain 62 and a fourth via 92 above the second drain 64, compared to the corresponding process of the prior art.
  • a mask is saved, and an etching process is reduced, thereby simplifying the process and saving production costs.
  • the array substrate of the invention has simple structure, low fabrication cost and good electrical properties.

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Abstract

一种阵列基板的制作方法及阵列基板，该阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层（90）来代替现有的氮化硅材料的钝化保护层（90），利用一道光罩对钝化保护层（90）和平坦层（70）进行曝光、显影处理，得到位于第一漏极（62）上方的第三过孔（91）、及位于第二漏极（64）上方的第四过孔（92），与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。阵列基板，结构简单，制作成本低，且具有良好的电学性能。

Description

阵列基板的制作方法及阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及阵列基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、夹于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
低温多晶硅(Low Temperature Poly Silicon，LTPS)是广泛用于中小电子产品中的一种液晶显示技术。传统的非晶硅材料的电子迁移率约0.5-1.0cm2/V.S，而低温多晶硅的电子迁移率可达30-300cm2/V.S。因此，低温多晶硅液晶显示器具有高解析度、反应速度快、高开口率等诸多优点。但是另一方面，由于LTPS半导体器件的体积小、集成度高，所以整个LTPS阵列基板的制备工艺复杂，生产成本较高。
目前，业界主流的显示面板的阵列基板的钝化保护层(PV)通常采用氮化硅(分子式：SiNx)单层结构组成。氮化硅是一种良好的绝缘材料，其透 光度较好，介电常数大约是6～9。
目前流行的LTPS阵列基板的制作流程中，对平坦层和钝化保护层进行图形化处理以形成像素电极与漏极的接触孔的方法如下：步骤1、如图1所示，首先形成平坦层(PLN)700，并利用光罩对平坦层700进行曝光显影处理，形成位于漏极620上方的第一通孔710；步骤2、如图2所示，在平坦层700上形成图形化的公共电极层(BITO)810，在公共电极层810上沉积氮化硅材料，形成钝化保护层900，利用曝光和蚀刻工艺对钝化保护层900进行图形化处理，在所述钝化保护层900上形成位于第一通孔710内的第二通孔910；所述第二通孔910用于实现像素电极与漏极620的接触。
然而上述制程需要使用两道光罩并进行一次蚀刻制程，生产成本较高，且工艺流程复杂。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，与现有技术相比，既节省一道光罩，又减少一道蚀刻制程，从而简化工艺流程、节约生产成本。
本发明的目的还在于提供一种阵列基板，结构简单，制作成本低，且具有良好的电学性能。
为实现上述目的，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层；
步骤2、在所述遮光层、及基板形成缓冲层，在所述缓冲层上形成非晶硅层，并对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层上方的第一多晶硅段、及与第一多晶硅段间隔设置的第二多晶硅段；
步骤3、利用光罩对所述第一多晶硅段的中间区域进行P型轻掺杂，得到第一沟道区，之后利用光罩对所述第一多晶硅段的两端进行N型重掺杂，得到位于两端的N型重掺杂区；
步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层，在栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在栅极绝缘层上得到分别对应于所述第一多晶硅段与第二多晶硅段中间区域的第一栅极绝缘层与第二栅极绝缘层，在第二金属层上得到分别位于所述第一、第二栅极绝缘层上方且与所述第 一、第二栅极绝缘层对齐的第一栅极与第二栅极；
步骤5、利用第一栅极作为光罩对所述第一多晶硅段上位于第一沟道区与N型重掺杂区之间的区域进行N型轻掺杂，得到N型轻掺杂区，之后利用光罩对所述第二多晶硅段的两端进行P型重掺杂，得到位于两端的P型重掺杂区、及位于两P型重掺杂区之间的第二沟道区；
步骤6、在所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上沉积层间绝缘层，通过光刻制程对所述层间绝缘层进行图形化处理，在所述层间绝缘层上形成对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；
步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层；在所述平坦层上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共电极；
步骤9、在所述公共电极、及平坦层上沉积有机光阻材料，形成钝化保护层；
步骤10、利用光罩对所述钝化保护层、及平坦层进行曝光、显影，得到对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔；
步骤11、在所述钝化保护层上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触。
所述步骤2中，利用激光退火方法对非晶硅层进行结晶化处理。
所述步骤6还包括：对所述层间绝缘层进行去氢和活化处理。
通过快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
所述步骤9中，采用蒸镀或喷印的方法沉积有机光阻材料。
所述步骤9还包括：对所述钝化保护层进行紫外光照射处理，使所述钝化保护层薄化，以增加其透光性。
所述平坦层的材料为有机光阻，所述钝化保护层的介电常数为3～4。
所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材 料为金属氧化物。
本发明还提供一种阵列基板，包括基板，位于基板上的遮光层，位于遮光层、及基板上的缓冲层，位于所述缓冲层上的第一多晶硅段与第二多晶硅段，分别位于第一多晶硅段与第二多晶硅段中间区域上方的第一栅极绝缘层与第二栅极绝缘层，分别位于所述第一栅极绝缘层与第二栅极绝缘层上方且与所述第一、第二栅极绝缘层对齐的第一栅极与第二栅极，位于所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上的层间绝缘层，位于层间绝缘层上的第一源极、第一漏极、第二源极、第二漏极，位于所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上的平坦层，位于平坦层上的公共电极，位于公共电极、及平坦层上的钝化保护层，以及位于钝化保护层上的像素电极；
所述第一多晶硅段包括对应所述第一栅极绝缘层下方的第一沟道区、位于两端的N型重掺杂区、及位于N型重掺杂区与第一沟道区之间的N型轻掺杂区；所述第二多晶硅段包括对应所述第二栅极绝缘层下方的第一沟道区、及位于两端的P型重掺杂区；
所述层间绝缘层上设有对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
所述平坦层与钝化保护层的材料均为有机光阻，所述钝化保护层及平坦层上设有对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触。
所述钝化保护层的介电常数为3～4；所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
本发明还提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层；
步骤2、在所述遮光层、及基板形成缓冲层，在所述缓冲层上形成非晶硅层，并对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层上方的第一多晶硅段、 及与第一多晶硅段间隔设置的第二多晶硅段；
步骤3、利用光罩对所述第一多晶硅段的中间区域进行P型轻掺杂，得到第一沟道区，之后利用光罩对所述第一多晶硅段的两端进行N型重掺杂，得到位于两端的N型重掺杂区；
步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层，在栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在栅极绝缘层上得到分别对应于所述第一多晶硅段与第二多晶硅段中间区域的第一栅极绝缘层与第二栅极绝缘层，在第二金属层上得到分别位于所述第一、第二栅极绝缘层上方且与所述第一、第二栅极绝缘层对齐的第一栅极与第二栅极；
步骤5、利用第一栅极作为光罩对所述第一多晶硅段上位于第一沟道区与N型重掺杂区之间的区域进行N型轻掺杂，得到N型轻掺杂区，之后利用光罩对所述第二多晶硅段的两端进行P型重掺杂，得到位于两端的P型重掺杂区、及位于两P型重掺杂区之间的第二沟道区；
步骤6、在所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上沉积层间绝缘层，通过光刻制程对所述层间绝缘层进行图形化处理，在所述层间绝缘层上形成对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；
步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层；在所述平坦层上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共电极；
步骤9、在所述公共电极、及平坦层上沉积有机光阻材料，形成钝化保护层；
步骤10、利用光罩对所述钝化保护层、及平坦层进行曝光、显影，得到对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔；
步骤11、在所述钝化保护层上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触；
所述步骤2中，利用激光退火方法对非晶硅层进行结晶化处理；
所述步骤6还包括：对所述层间绝缘层进行去氢和活化处理。
本发明的有益效果：本发明的阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层来代替现有的氮化硅材料的钝化保护层，利用一道光罩对钝化保护层和平坦层进行曝光、显影处理，得到位于第一漏极上方的第三过孔、及位于第二漏极上方的第四过孔，与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。本发明的阵列基板，结构简单，制作成本低，且具有良好的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1-2为现有的阵列基板的制作方法中对平坦层和钝化保护层进行图形化处理的示意图；
图3为本发明的阵列基板的制作方法步骤1的示意图；
图4为本发明的阵列基板的制作方法步骤2的示意图；
图5为本发明的阵列基板的制作方法步骤3的示意图；
图6为本发明的阵列基板的制作方法步骤4的示意图；
图7为本发明的阵列基板的制作方法步骤5的示意图；
图8为本发明的阵列基板的制作方法步骤6的示意图；
图9为本发明的阵列基板的制作方法步骤7的示意图；
图10为本发明的阵列基板的制作方法步骤8的示意图；
图11为本发明的阵列基板的制作方法步骤9的示意图；
图12为本发明的阵列基板的制作方法步骤10的示意图；
图13为本发明的阵列基板的制作方法步骤11的示意图暨本发明的阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图3-13，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、如图3所示，提供一基板10，在所述基板10上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层20。
具体的，所述基板10为透明基板，优选为玻璃基板。
步骤2、如图4所示，在所述遮光层20、及基板10形成缓冲层23，在所述缓冲层23上形成非晶硅层，利用激光退火方法对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层20上方的第一多晶硅段30、及与第一多晶硅段30间隔设置的第二多晶硅段40。
通过将第一多晶硅段30设置于遮光层20上方，从而有效防止光线进入第一多晶硅段30的沟道区中，可以起到降低漏电流、提高TFT器件电学性能的作用。所述第二多晶硅段40的沟道区在阵列基板完成后采用其它遮光材料在阵列基板外侧进行覆盖。
步骤3、如图5所示，利用光罩对所述第一多晶硅段30的中间区域进行P型轻掺杂，得到第一沟道区32，之后利用光罩对所述第一多晶硅段30的两端进行N型重掺杂，得到位于两端的N型重掺杂区31。
步骤4、如图6所示，在所述第一多晶硅段30、第二多晶硅段40、及缓冲层23上沉积栅极绝缘层，在所述栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在所述栅极绝缘层上得到分别对应于所述第一多晶硅段30与第二多晶硅段40中间区域的第一栅极绝缘层53与第二栅极绝缘层54，在第二金属层上得到分别位于所述第一、第二栅极绝缘层53、54上方且与所述第一、第二栅极绝缘层53、54对齐的第一栅极51与第二栅极52。
步骤5、如图7所示，利用第一栅极51为光罩对所述第一多晶硅段30上位于第一沟道区32与N型重掺杂区31之间的区域进行N型轻掺杂，得到N型轻掺杂区33，之后利用光罩对所述第二多晶硅段40的两端进行P型重掺杂，得到位于两端的P型重掺杂区41、及位于两P型重掺杂区41之间的第二沟道区42。
步骤6、如图8所示，在所述第一栅极51、第二栅极52、第一多晶硅段30、第二多晶硅段40、及缓冲层23上沉积层间绝缘层60，通过光刻制程对所述层间绝缘层60进行图形化处理，在所述层间绝缘层60上形成对应于N型重掺杂区31上方的第一过孔67、及对应于P型重掺杂区41上方的第二过孔68；之后对所述层间绝缘层60进行去氢和活化处理。
具体的，通过快速热退火工艺(RTA，Rapid Thermal Annealing)对所述层间绝缘层60进行去氢和活化处理。
步骤7、如图9所示，在所述层间绝缘层60上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极61、第一漏极62、第二源极63、及第二漏极64；所述第一源极61、第一漏极62分别通过第一过孔67与N型重掺杂区31相接触，所述第二源极63、第二漏极64分别通过第二过孔68与P型重掺杂区41相接触。
步骤8、如图10所示，在所述第一源极61、第一漏极62、第二源极63、第二漏极64、及层间绝缘层60上涂布有机光阻材料，形成平坦层70；在所述平坦层70上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共(COM)电极81。
步骤9、如图11所示，在所述公共电极81、及平坦层70上采用蒸镀或喷印的方法沉积有机光阻材料，形成钝化保护层90。
进一步的，所述步骤10还可以包括：对所述钝化保护层90进行紫外光照射处理，使所述钝化保护层90薄化，以增加其透光性。
具体的，所述钝化保护层90的介电常数大约是3～4，与现有的介电常数大约是6～9的氮化硅材料的钝化保护层相比，可以通过降低所述钝化保护层90的膜厚来满足阵列基板的电容需求。
步骤10、如图12所示，利用光罩对所述钝化保护层90、及平坦层70进行曝光、显影，得到对应于第一漏极62上方的第三过孔91、及对应于第二漏极64上方的第四过孔92。
步骤11、如图13所示，在所述钝化保护层90上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极95，所述像素电极95分别通过第三过孔91、第四过孔92与第一漏极62、及第二漏极64相接触。
具体的，所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合。
具体的，所述缓冲层23、第一、第二栅极绝缘层53、54、层间绝缘层60为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述第一透明导电层、第二透明导电层的材料为金属氧化物，所述金属氧化物可以为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
所述P型轻掺杂与P型重掺杂掺入的离子可以为硼(B)离子或镓(Ga)离子；所述N型轻掺杂与N型重掺杂掺入的离子可以为磷(P)离子或砷(As)离子。
所述第一源极61、第一漏极62、第一栅极51与第一多晶硅段30构成 NMOS(Negative channel-Metal-Oxide-Semiconductor，N型金属氧化物半导体)晶体管；所述第二源极63、第二漏极64、第二栅极52与第二多晶硅段40构成PMOS(Positive channel-Metal-Oxide-Semiconductor，P型金属氧化物半导体)晶体管。
上述阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层90来代替现有的氮化硅材料的钝化保护层，之后利用一道光罩对钝化保护层90和平坦层70进行曝光、显影处理，得到位于第一漏极62上方的第三过孔91、及位于第二漏极64上方的第四过孔92，与现有技术的相应制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到了简化工艺流程、以及节约生产成本的目的。
请参阅图13，同时参阅图3-12，本发明还提供一种阵列基板，包括基板10，位于基板10上的遮光层20，位于遮光层20、及基板10上的缓冲层23，位于所述缓冲层23上的第一多晶硅段30与第二多晶硅段40，分别位于第一多晶硅段30与第二多晶硅段40中间区域上方的第一栅极绝缘层53与第二栅极绝缘层54，分别位于所述第一栅极绝缘层53与第二栅极绝缘层54上方且与所述第一、第二栅极绝缘层53、54对齐的第一栅极51与第二栅极52，位于所述第一栅极51、第二栅极52、第一多晶硅段30、第二多晶硅段40、及缓冲层23上的层间绝缘层60，位于层间绝缘层60上的第一源极61、第一漏极62、第二源极63、第二漏极64，位于所述第一源极61、第一漏极62、第二源极63、第二漏极64、及层间绝缘层60上的平坦层70，位于平坦层70上的公共电极81，位于公共电极81、及平坦层70上的钝化保护层90，以及位于钝化保护层90上的像素电极95。
具体的，所述第一多晶硅段30包括对应所述第一栅极绝缘层53下方的第一沟道区32、位于两端的N型重掺杂区31、及位于N型重掺杂区31与第一沟道区32之间的N型轻掺杂区33；所述第二多晶硅段40包括对应所述第二栅极绝缘层54下方的第一沟道区41、及位于两端的P型重掺杂区42；所述N型重掺杂区31与N型轻掺杂区33中掺入的离子可以为磷(P)离子或砷(As)离子；所述P型重掺杂区41及第一沟道区32中掺入的离子可以为硼(B)离子或镓(Ga)离子。
具体的，所述层间绝缘层60上设有对应于N型重掺杂区31上方的第一过孔67、及对应于P型重掺杂区41上方的第二过孔68；所述第一源极61、第一漏极62分别通过第一过孔67与N型重掺杂区31相接触，所述第二源极63、第二漏极64分别通过第二过孔68与P型重掺杂区41相接触；
所述平坦层70与钝化保护层90的材料均为有机光阻，所述钝化保护 层90及平坦层70上设有对应于第一漏极62上方的第三过孔91、及对应于第二漏极64上方的第四过孔92，所述像素电极95分别通过第三过孔91、第四过孔92与第一漏极62、及第二漏极64相接触。
具体的，所述第一源极61、第一漏极62、第一栅极51与第一多晶硅段30构成NMOS晶体管；所述第二源极63、第二漏极64、第二栅极52与第二多晶硅段40构成PMOS晶体管。
具体的，所述第一多晶硅段30对应于遮光层20上方设置，由于遮光层20的覆盖，可以有效防止光线进入第一多晶硅段30的第一沟道区32中，可以起到降低漏电流、提高TFT器件电学性能的作用。所述第二多晶硅段40的第二沟道区42在后续制程中采用其它遮光材料在阵列基板外侧进行覆盖。
具体的，所述基板10为透明基板，优选为玻璃基板。
所述遮光层20、第一栅极51、第二栅极52、、第一源极61、第一漏极62、第二源极63、第二漏极64的材料可以是钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。
所述缓冲层23、第一、第二栅极绝缘层53、54、层间绝缘层60为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
所述公共电极81、及像素电极95的材料为金属氧化物，所述金属氧化物可以为铟锡氧化物、铟锌氧化物、铝锡氧化物、铝锌氧化物、铟锗锌氧化物中的一种或多种。
具体的，所述钝化保护层90的介电常数大约是3～4，可以通过调节所述钝化保护层90的膜厚，从而达成阵列基板的电容需求。
上述阵列基板，通过采用由有机光阻材料制作的钝化保护层90来代替现有的氮化硅材料的钝化保护层，使得钝化保护层90和平坦层70上对应于第一漏极62上方的第三过孔91及对应于第二漏极64上方的第四过孔92可以利用一道光罩进行曝光形成，从而与现有的阵列基板的制程相比，既节省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。
综上所述，本发明提供的一种阵列基板的制作方法及阵列基板。本发明的阵列基板的制作方法，通过采用由有机光阻材料制作的钝化保护层90来代替现有的氮化硅材料的钝化保护层，利用一道光罩对钝化保护层90和平坦层70进行曝光、显影处理，得到位于第一漏极62上方的第三过孔91、及位于第二漏极64上方的第四过孔92，与现有技术的相应制程相比，既节 省了一道光罩，又减少了一道蚀刻制程，从而达到简化工艺流程、以及节约生产成本的目的。本发明的阵列基板，结构简单，制作成本低，且具有良好的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (16)

  1. 一种阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层；
    步骤2、在所述遮光层、及基板形成缓冲层，在所述缓冲层上形成非晶硅层，并对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层上方的第一多晶硅段、及与第一多晶硅段间隔设置的第二多晶硅段；
    步骤3、利用光罩对所述第一多晶硅段的中间区域进行P型轻掺杂，得到第一沟道区，之后利用光罩对所述第一多晶硅段的两端进行N型重掺杂，得到位于两端的N型重掺杂区；
    步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层，在栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在栅极绝缘层上得到分别对应于所述第一多晶硅段与第二多晶硅段中间区域的第一栅极绝缘层与第二栅极绝缘层，在第二金属层上得到分别位于所述第一、第二栅极绝缘层上方且与所述第一、第二栅极绝缘层对齐的第一栅极与第二栅极；
    步骤5、利用第一栅极作为光罩对所述第一多晶硅段上位于第一沟道区与N型重掺杂区之间的区域进行N型轻掺杂，得到N型轻掺杂区，之后利用光罩对所述第二多晶硅段的两端进行P型重掺杂，得到位于两端的P型重掺杂区、及位于两P型重掺杂区之间的第二沟道区；
    步骤6、在所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上沉积层间绝缘层，通过光刻制程对所述层间绝缘层进行图形化处理，在所述层间绝缘层上形成对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；
    步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
    步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层；在所述平坦层上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共电极；
    步骤9、在所述公共电极、及平坦层上沉积有机光阻材料，形成钝化保护层；
    步骤10、利用光罩对所述钝化保护层、及平坦层进行曝光、显影，得到对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔；
    步骤11、在所述钝化保护层上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤2中，利用激光退火方法对非晶硅层进行结晶化处理。
  3. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤6还包括：对所述层间绝缘层进行去氢和活化处理。
  4. 如权利要求3所述的阵列基板的制作方法，其中，通过快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
  5. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤9中，采用蒸镀或喷印的方法沉积有机光阻材料。
  6. 如权利要求1所述的阵列基板的制作方法，其中，所述步骤9还包括：对所述钝化保护层进行紫外光照射处理，使所述钝化保护层薄化，以增加其透光性。
  7. 如权利要求1所述的阵列基板的制作方法，其中，所述平坦层的材料为有机光阻，所述钝化保护层的介电常数为3～4。
  8. 如权利要求1所述的阵列基板的制作方法，其中，所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
  9. 一种阵列基板，包括基板，位于基板上的遮光层，位于遮光层、及基板上的缓冲层，位于所述缓冲层上的第一多晶硅段与第二多晶硅段，分别位于第一多晶硅段与第二多晶硅段中间区域上方的第一栅极绝缘层与第二栅极绝缘层，分别位于所述第一栅极绝缘层与第二栅极绝缘层上方且与所述第一、第二栅极绝缘层对齐的第一栅极与第二栅极，位于所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上的层间绝缘层，位于层间绝缘层上的第一源极、第一漏极、第二源极、第二漏极，位于所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上的平坦层，位于平坦层上的公共电极，位于公共电极、及平坦层上的钝化保护层，以 及位于钝化保护层上的像素电极；
    所述第一多晶硅段包括对应所述第一栅极绝缘层下方的第一沟道区、位于两端的N型重掺杂区、及位于N型重掺杂区与第一沟道区之间的N型轻掺杂区；所述第二多晶硅段包括对应所述第二栅极绝缘层下方的第一沟道区、及位于两端的P型重掺杂区；
    所述层间绝缘层上设有对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
    所述平坦层与钝化保护层的材料均为有机光阻，所述钝化保护层及平坦层上设有对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触。
  10. 如权利要求9所述的阵列基板，其中，所述钝化保护层的介电常数为3～4；所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
  11. 一种阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上沉积第一金属层，对所述第一金属层进行图形化处理，得到遮光层；
    步骤2、在所述遮光层、及基板形成缓冲层，在所述缓冲层上形成非晶硅层，并对非晶硅层进行结晶化处理，从而形成多晶硅层，采用光刻制程对所述多晶硅层进行图形化处理，得到对应于遮光层上方的第一多晶硅段、及与第一多晶硅段间隔设置的第二多晶硅段；
    步骤3、利用光罩对所述第一多晶硅段的中间区域进行P型轻掺杂，得到第一沟道区，之后利用光罩对所述第一多晶硅段的两端进行N型重掺杂，得到位于两端的N型重掺杂区；
    步骤4、在所述第一多晶硅段、第二多晶硅段、及缓冲层上沉积栅极绝缘层，在栅极绝缘层上沉积第二金属层，采用光刻制程对所述栅极绝缘层及第二金属层进行图形化处理，在栅极绝缘层上得到分别对应于所述第一多晶硅段与第二多晶硅段中间区域的第一栅极绝缘层与第二栅极绝缘层，在第二金属层上得到分别位于所述第一、第二栅极绝缘层上方且与所述第 一、第二栅极绝缘层对齐的第一栅极与第二栅极；
    步骤5、利用第一栅极作为光罩对所述第一多晶硅段上位于第一沟道区与N型重掺杂区之间的区域进行N型轻掺杂，得到N型轻掺杂区，之后利用光罩对所述第二多晶硅段的两端进行P型重掺杂，得到位于两端的P型重掺杂区、及位于两P型重掺杂区之间的第二沟道区；
    步骤6、在所述第一栅极、第二栅极、第一多晶硅段、第二多晶硅段、及缓冲层上沉积层间绝缘层，通过光刻制程对所述层间绝缘层进行图形化处理，在所述层间绝缘层上形成对应于N型重掺杂区上方的第一过孔、及对应于P型重掺杂区上方的第二过孔；
    步骤7、在所述层间绝缘层上沉积第三金属层，对所述第三金属层进行图形化处理，得到间隔设置的第一源极、第一漏极、第二源极、及第二漏极；所述第一源极、第一漏极分别通过第一过孔与N型重掺杂区相接触，所述第二源极、第二漏极分别通过第二过孔与P型重掺杂区相接触；
    步骤8、在所述第一源极、第一漏极、第二源极、第二漏极、及层间绝缘层上形成平坦层；在所述平坦层上沉积第一透明导电层，对所述第一透明导电层进行图形化处理，得到公共电极；
    步骤9、在所述公共电极、及平坦层上沉积有机光阻材料，形成钝化保护层；
    步骤10、利用光罩对所述钝化保护层、及平坦层进行曝光、显影，得到对应于第一漏极上方的第三过孔、及对应于第二漏极上方的第四过孔；
    步骤11、在所述钝化保护层上沉积第二透明导电层，对所述第二透明导电层进行图形化处理，得到像素电极，所述像素电极分别通过第三过孔、第四过孔与第一漏极、及第二漏极相接触；
    所述步骤2中，利用激光退火方法对非晶硅层进行结晶化处理；
    所述步骤6还包括：对所述层间绝缘层进行去氢和活化处理。
  12. 如权利要求11所述的阵列基板的制作方法，其中，通过快速热退火工艺对所述层间绝缘层进行去氢和活化处理。
  13. 如权利要求11所述的阵列基板的制作方法，其中，所述步骤9中，采用蒸镀或喷印的方法沉积有机光阻材料。
  14. 如权利要求11所述的阵列基板的制作方法，其中，所述步骤9还包括：对所述钝化保护层进行紫外光照射处理，使所述钝化保护层薄化，以增加其透光性。
  15. 如权利要求11所述的阵列基板的制作方法，其中，所述平坦层的材料为有机光阻，所述钝化保护层的介电常数为3～4。
  16. 如权利要求11所述的阵列基板的制作方法，其中，所述基板为透明基板；所述第一金属层、第二金属层、第三金属层的材料为钼、钛、铝、铜中的一种或多种的堆栈组合；所述缓冲层、第一、第二栅极绝缘层、层间绝缘层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一透明导电层、第二透明导电层的材料为金属氧化物。
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