WO2017147973A1 - 阵列基板的制作方法及制得的阵列基板 - Google Patents

阵列基板的制作方法及制得的阵列基板 Download PDF

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WO2017147973A1
WO2017147973A1 PCT/CN2016/078876 CN2016078876W WO2017147973A1 WO 2017147973 A1 WO2017147973 A1 WO 2017147973A1 CN 2016078876 W CN2016078876 W CN 2016078876W WO 2017147973 A1 WO2017147973 A1 WO 2017147973A1
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layer
hole
passivation layer
disposed
source
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PCT/CN2016/078876
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English (en)
French (fr)
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甘启明
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深圳市华星光电技术有限公司
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Priority to US15/105,581 priority Critical patent/US10211232B2/en
Publication of WO2017147973A1 publication Critical patent/WO2017147973A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/16—Acidic compositions
    • C23F1/18—Acidic compositions for etching copper or alloys thereof
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00—Etching metallic material by chemical means
    • C23F1/10—Etching compositions
    • C23F1/14—Aqueous compositions
    • C23F1/32—Alkaline compositions
    • C23F1/34—Alkaline compositions for etching copper or alloys thereof
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    • G02—OPTICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133357—Planarisation layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
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    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/50—Protective arrangements

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating an array substrate and an array substrate obtained.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • the liquid crystal display panel comprises a CF (Color Filter) substrate, a Thin Film Transistor (TFT) array substrate, a liquid crystal (LC) sandwiched between the color filter substrate and the thin film transistor array substrate, and a sealant.
  • CF Color Filter
  • TFT Thin Film Transistor
  • LC liquid crystal sandwiched between the color filter substrate and the thin film transistor array substrate
  • sealant a sealant.
  • the composition of the box (Sealant).
  • FIG. 1 is a schematic diagram of a method for fabricating an array substrate according to the prior art.
  • the method for fabricating the array substrate includes the following steps:
  • Step 1 providing a base substrate 100, sequentially forming a gate (not shown), a gate insulating layer 200, an active layer (not shown), and a source/drain 300 on the base substrate 100;
  • Step 2 forming a first passivation layer 400 on the source/drain 300 and the gate insulating layer 200, and patterning the first passivation layer 400 to obtain a first passivation layer 400.
  • Step 3 forming a flat layer 500 on the first passivation layer 400, and patterning the flat layer 500 to obtain a second via hole 510 located in the first via hole 410; Annealing treatment;
  • Step 4 forming a common electrode 600 on the flat layer 500;
  • Step 5 forming a second passivation layer 700 on the common electrode 600 and the flat layer 500, and patterning the second passivation layer 700 to obtain a third via 710 located in the second via 510. ;
  • Step 6 forming a pixel electrode 800 on the second passivation layer 700 , and the pixel electrode 800 is in contact with the source/drain 300 via the third via 710 .
  • step 3 of the method for fabricating the above array substrate when the planarization layer 500 is annealed, the photoresist material of the planarization layer 500 located in the first via hole 410 reacts with the metal material of the source/drain electrodes 300 to generate no
  • the conductive complex 550 blocks the conduction of the pixel electrode 800 from the source/drain 300, resulting in the inability of the data signal to be transmitted to the pixel electrode 300, thereby having a fatal effect on the performance of the array substrate.
  • the object of the present invention is to provide a method for fabricating an array substrate, which effectively blocks the contact between the flat layer and the source/drain, prevents the formation of a non-conductive complex in the annealing process of the flat layer, and improves the electrical performance of the array substrate. To achieve signal conduction; reduce the number of masks, reduce process time, and reduce production costs.
  • the present invention provides a method for fabricating an array substrate, comprising the following steps:
  • Step 1 providing a substrate, sequentially forming a gate, a gate insulating layer, an active layer, and a source/drain on the substrate;
  • Step 2 forming a first passivation layer on the source/drain and gate insulating layers, forming a flat layer on the first passivation layer, and performing pattern processing on the flat layer to obtain a source corresponding to the source a first via above the drain;
  • Step 3 depositing a first transparent conductive layer on the flat layer, and patterning the first transparent conductive layer to form a common electrode;
  • Step 4 forming a second passivation layer on the common electrode and the flat layer, the second passivation layer covering the first via hole and contacting the first passivation layer;
  • Step 5 depositing a second transparent conductive layer on the second passivation layer, and patterning the second transparent conductive layer to form a pixel electrode, wherein the pixel electrode passes through the second through hole and the third pass The holes are in contact with the source/drain.
  • the material and film thickness of the first passivation layer and the second passivation layer are the same.
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the second passivation layer
  • the film thickness of the layer is
  • the size of the second through hole and the third through hole is smaller than the size of the first through hole.
  • the first through hole, the second through hole, and the third through hole are all circular holes, the first through hole has a diameter of 7-12 ⁇ m, and the diameters of the second through hole and the third through hole are 3-5 ⁇ m.
  • the present invention also provides an array substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active layer disposed on the gate insulating layer a source/drain provided on the active layer and the gate insulating layer, a first passivation layer disposed on the source/drain, the active layer, and the gate insulating layer, and disposed on the a planarization layer on the first passivation layer, a common electrode disposed on the planarization layer, a second passivation layer disposed on the common electrode and the planarization layer, and a second passivation layer disposed on the second passivation layer Pixel electrode
  • a first through hole corresponding to the source/drain is disposed on the flat layer, and a second through hole is disposed on a portion of the second passivation layer at the bottom of the first through hole, the first The passivation layer is provided with a third via hole penetrating the second via hole, and the pixel electrode is in contact with the source/drain via the second via hole and the third via hole.
  • the material and film thickness of the first passivation layer and the second passivation layer are the same.
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the second passivation layer
  • the film thickness of the layer is
  • the size of the second through hole and the third through hole is smaller than the size of the first through hole.
  • the first through hole, the second through hole, and the third through hole are all circular holes, the first through hole has a diameter of 7-12 ⁇ m, and the diameters of the second through hole and the third through hole are 3-5 ⁇ m.
  • the present invention also provides an array substrate including a substrate, a gate electrode disposed on the substrate, a gate insulating layer disposed on the gate and the substrate, and an active layer disposed on the gate insulating layer a source/drain provided on the active layer and the gate insulating layer, a first passivation layer disposed on the source/drain, the active layer, and the gate insulating layer, and disposed on the a planarization layer on the first passivation layer, a common electrode disposed on the planarization layer, a second passivation layer disposed on the common electrode and the planarization layer, and a second passivation layer disposed on the second passivation layer Pixel electrode
  • a first through hole corresponding to the source/drain is disposed on the flat layer, and a second through hole is disposed on a portion of the second passivation layer at the bottom of the first through hole, the first a third via hole penetrating through the second via hole is disposed on the passivation layer, and the pixel electrode is in contact with the source/drain via the second via hole and the third via hole;
  • the material and film thickness of the first passivation layer and the second passivation layer are the same;
  • the first passivation layer and the second passivation layer are a silicon oxide layer, a silicon nitride layer, or a composite layer formed by superposing a silicon oxide layer and a silicon nitride layer; the first passivation layer and the first passivation layer
  • the film thickness of the second passivation layer is
  • the size of the second through hole and the third through hole is smaller than the size of the first through hole.
  • the present invention provides a method for fabricating an array substrate by sequentially forming a first passivation layer and a flat layer, and then patterning and annealing the flat layer to anneal the flat layer.
  • the first passivation layer is disposed between the flat layer and the source and the drain, so that the reaction does not occur to form a complex, which is beneficial to improving the electrical performance of the array substrate and achieving signal conduction;
  • the invention can also reduce at least one mask, which is beneficial to improving the process effect, shortening the processing time and reducing the production cost.
  • the array substrate prepared by the invention has smooth signal conduction and good electrical performance.
  • FIG. 1 is a schematic view showing a method of fabricating an array substrate of the prior art
  • FIG. 2 is a schematic view showing the first step of the method for fabricating the array substrate of the present invention
  • step 2 is a schematic diagram of step 2 of a method for fabricating an array substrate of the present invention
  • step 3 is a schematic diagram of step 3 of the method for fabricating an array substrate of the present invention.
  • 5-6 is a schematic diagram of step 4 of the method for fabricating the array substrate of the present invention.
  • FIG. 7 is a schematic view showing the step 5 of the method for fabricating the array substrate of the present invention and the structure of the array substrate prepared by the present invention.
  • the present invention provides a method for fabricating an array substrate, including the following steps:
  • Step 1 as shown in FIG. 2, a substrate 10 is provided, and a gate electrode 15, a gate insulating layer 20, an active layer 25, and source/drain electrodes 30 are sequentially formed on the substrate 10.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the gate electrode 15 and the source/drain electrodes 30 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source/drain 30 is preferably copper.
  • the gate insulating layer 20 is a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the active layer 25 is indium gallium zinc oxide (IGZO).
  • Step 2 As shown in FIG. 3, a first passivation layer 40 is formed on the source/drain 30 and the gate insulating layer 20, and a flat layer 50 is formed on the first passivation layer 40.
  • the flat layer 50 is exposed and developed by the cover to pattern the flat layer 50 to obtain a first through hole 51 corresponding to the upper side of the source/drain 30.
  • the material of the flat layer 50 is a positive photoresist.
  • the step 2 further includes: after the first through hole 51 is formed on the flat layer 50, the flat layer 50 is subjected to an annealing treatment to be heat-cured.
  • the flat layer 50 is annealed, since the first passivation layer 40 is not in contact with the flat layer 50 and the source/drain 30, no reaction occurs to form a complex.
  • Step 3 As shown in FIG. 4, a first transparent conductive layer is deposited on the flat layer 50, and the first transparent conductive layer is patterned by a photolithography process to form a common electrode 60.
  • the material of the common electrode 60 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the step 3 further comprises: annealing the common electrode 60 to heat-solidify the transparent conductive metal oxide therein, thereby improving the film structure of the common electrode 60, reducing the sheet resistance, and making the structure more Stable and long lasting.
  • Step 4 as shown in FIG. 5, a second passivation layer 70 is formed on the common electrode 60 and the planarization layer 50, and the second passivation layer 70 covers the first via hole 51 and the first passivation layer. 40 contact;
  • a portion of the second passivation layer 70 located at the bottom of the first via hole 51 is subjected to a lithography process to obtain a second via hole 71 on the second passivation layer 70.
  • the first passivation layer 40 is further etched along the second via hole 71 to obtain a third via hole 41 corresponding to the second via hole 71.
  • the material and film thickness of the first passivation layer 40 and the second passivation layer 70 are the same, which can reduce the undercut issue caused by different materials in the dry etching process.
  • the first passivation layer 40 and the second passivation layer 70 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • Floor a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the film thickness of the first passivation layer 40 and the second passivation layer 70 is the film thickness of the first passivation layer 40 and the second passivation layer 70.
  • the size of the second through hole 71 and the third through hole 41 is smaller than the size of the first through hole 51.
  • the first through hole 51, the second through hole 71, and the third through hole 41 are all circular holes, and the first through hole 51 has a diameter of 7-12 ⁇ m, and the second through hole 71 The diameter of the third through hole 41 is 3-5 ⁇ m.
  • the etching process in the photolithography process of the second passivation layer 70 and the etching process of the first passivation layer 40 are both dry etching processes.
  • the step 4 uses a reticle to realize the opening treatment of the first passivation layer 40 and the second passivation layer 70. Compared with the prior art, the reticle can be saved, the production cost is saved, and the process time is reduced. .
  • Step 5 depositing a second transparent conductive layer on the second passivation layer 70, and patterning the second transparent conductive layer by a photolithography process to form a pixel electrode 80.
  • the pixel electrode 80 is in contact with the source/drain 30 via the second via 71 and the third via 41.
  • the material of the pixel electrode 80 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the step 5 further comprises: annealing the pixel electrode 80 to heat-solidify the transparent conductive metal oxide therein, thereby improving the film structure of the pixel electrode 80, reducing the sheet resistance, and making the structure more Stable and long lasting.
  • the present invention further provides an array substrate, comprising a substrate 10, a gate electrode 15 disposed on the substrate 10, a gate insulating layer 20 disposed on the gate electrode 15 and the substrate 10, and An active layer 25 on the gate insulating layer 20, a source/drain 30 provided on the active layer 25 and the gate insulating layer 20, and the source/drain 30 and the active layer 25 And a first passivation layer 40 on the gate insulating layer 20, a flat layer 50 disposed on the first passivation layer 40, and a common electrode 60 disposed on the flat layer 50, disposed in the common The electrode 60 and the second passivation layer 70 on the flat layer 50 and the pixel electrode 80 provided on the second passivation layer 70.
  • a first via hole 51 corresponding to the source/drain 30 is disposed on the flat layer 50, and a second via hole is disposed on a portion of the second passivation layer 70 at the bottom of the first via hole 51. 71.
  • the first passivation layer 40 is provided with a third through hole 41 penetrating the second through hole 71.
  • the pixel electrode 80 passes through the second through hole 71 and the third through hole 41 and the source/ The drains 30 are in contact.
  • the substrate 10 is a transparent substrate, preferably a glass substrate.
  • the material of the gate electrode 15 and the source/drain electrodes 30 is a stack combination of one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Mo molybdenum
  • Ti titanium
  • Al aluminum
  • Cu copper
  • the material of the source/drain 30 is preferably copper.
  • the gate insulating layer 20 is a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the material of the active layer 25 is indium gallium zinc oxide (IGZO).
  • the material of the flat layer 50 is a positive photoresist.
  • the material of the common electrode 60 and the pixel electrode 80 is a transparent conductive metal oxide such as indium tin oxide (ITO) or the like.
  • the material and film thickness of the first passivation layer 40 and the second passivation layer 70 are the same.
  • the first passivation layer 40 and the second passivation layer 70 are a silicon oxide (SiO x ) layer, a silicon nitride (SiN x ) layer, or a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • SiO x silicon oxide
  • SiN x silicon nitride
  • Floor a composite layer composed of a silicon oxide layer and a silicon nitride layer.
  • the film thickness of the first passivation layer 40 and the second passivation layer 70 is the film thickness of the first passivation layer 40 and the second passivation layer 70.
  • the size of the second through hole 71 and the third through hole 41 is smaller than the size of the first through hole 51.
  • the first through hole 51, the second through hole 71, and the third through hole 41 are all circular holes, and the first through hole 51 has a diameter of 7-12 ⁇ m, and the second through hole 71 The diameter of the third through hole 41 is 3-5 ⁇ m.
  • the present invention provides a method for fabricating an array substrate by sequentially forming a first passivation layer and a flat layer, and then patterning and annealing the flat layer to anneal the flat layer.
  • the first passivation layer is disposed between the flat layer and the source and the drain, so that the reaction does not occur to form a complex, which is beneficial to improving the electrical performance of the array substrate and achieving signal conduction;
  • the invention can also reduce at least one mask, which is beneficial to improving the process effect, shortening the processing time, and reducing the production cost.
  • the array substrate prepared by the invention has smooth signal conduction and good electrical performance.

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Abstract

一种阵列基板的制作方法及制得的阵列基板，通过先依次形成第一钝化层（40）与平坦层（50），之后对平坦层（50）进行图形化处理及退火处理，在对平坦层（50）进行退火处理的过程中，由于平坦层（50）与源漏极（30）之间设有第一钝化层（40），不能够相接触，因此不会发生反应生成络合物，有利于提高阵列基板的电学性能，实现信号导通；与现有的阵列基板的制作方法相比，还可以至少减少一道光罩，有利于提升工艺效果，缩短制程时间，降低生产成本，制得的阵列基板，信号传导畅通，具有良好的电学性能。

Description

阵列基板的制作方法及制得的阵列基板 技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板的制作方法及制得的阵列基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)阵列基板、夹于彩膜基板与薄膜晶体管阵列基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成。
图1为现有的一种阵列基板的制作方法的示意图，该阵列基板的制作方法包括如下步骤：
步骤1、提供一衬底基板100，在所述衬底基板100上依次形成栅极(未图示)、栅极绝缘层200、有源层(未图示)、及源/漏极300；
步骤2、在所述源/漏极300及栅极绝缘层200上形成第一钝化层400，并对该第一钝化层400进行图形化处理，得到位于第一钝化层400上的第一过孔410；
步骤3、在所述第一钝化层400上形成平坦层500，并对该平坦层500进行图形化处理，得到位于第一过孔410中的第二过孔510；之后对平坦层500进行退火处理；
步骤4、在所述平坦层500上形成公共电极600；
步骤5、在所述公共电极600、平坦层500上形成第二钝化层700，并对该第二钝化层700进行图形化处理，得到位于第二过孔510内的第三过孔710；
步骤6、在所述第二钝化层700上形成像素电极800，所述像素电极800经由第三过孔710与源/漏极300相接触。
上述阵列基板的制作方法步骤3中，在对平坦层500进行退火处理时，位于第一过孔410中的平坦层500的光阻材料会与源/漏极300的金属材料发生反应，生成不导电的络合物550，从而阻隔所述像素电极800与源/漏极300的导通，导致数据(Data)信号无法传输至像素电极300，从而对阵列基板的性能造成致命性的影响。
发明内容
本发明的目的在于提供一种阵列基板的制作方法，有效阻隔平坦层与源/漏极的接触，防止在平坦层的退火工艺中产生不导电的络合物，有利于提高阵列基板的电学性能，实现信号导通；同时减少光罩数量，减少制程时间，降低生产成本。
本发明的目的还在于提供一种阵列基板，信号传导畅通，具有良好的电学性能。
为实现上述目的，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、提供一基板，在所述基板上依次形成栅极、栅极绝缘层、有源层、及源/漏极；
步骤2、在所述源/漏极及栅极绝缘层上形成第一钝化层，在所述第一钝化层上形成平坦层，对所述平坦层进行图形化处理，得到对应于源/漏极上方的第一通孔；
步骤3、在所述平坦层上沉积第一透明导电层，并对所述第一透明导电层进行图形化处理，形成公共电极；
步骤4、在所述公共电极、平坦层上形成第二钝化层，所述第二钝化层包覆第一通孔并与第一钝化层相接触；
对所述第二钝化层上位于第一通孔内的部分进行开孔处理，得到位于第二钝化层上的第二通孔，沿所述第二通孔继续对第一钝化层进行蚀刻，得到对应于第二通孔的第三通孔，从而所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸；
步骤5、在所述第二钝化层上沉积第二透明导电层，并对所述第二透明导电层进行图形化处理，形成像素电极，所述像素电极经由第二通孔与第三通孔与源/漏极相接触。
所述第一钝化层与第二钝化层的材质和膜厚相同。
所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
Figure PCTCN2016078876-appb-000001
所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
本发明还提供一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上的公共电极、设于所述公共电极、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
所述平坦层上设有对应于源/漏极上方的第一通孔，所述第二钝化层上位于所述第一通孔底部的部分上设有第二通孔，所述第一钝化层上设有与所述第二通孔相贯通的第三通孔，所述像素电极经由第二通孔与第三通孔与源/漏极相接触。
所述第一钝化层与第二钝化层的材质和膜厚相同。
所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
Figure PCTCN2016078876-appb-000002
所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
本发明还提供一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上的公共电极、设于所述公共电极、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
所述平坦层上设有对应于源/漏极上方的第一通孔，所述第二钝化层上位于所述第一通孔底部的部分上设有第二通孔，所述第一钝化层上设有与所述第二通孔相贯通的第三通孔，所述像素电极经由第二通孔与第三通孔与源/漏极相接触；
其中，所述第一钝化层与第二钝化层的材质和膜厚相同；
其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
Figure PCTCN2016078876-appb-000003
其中，所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
本发明的有益效果：本发明提供的一种阵列基板的制作方法，通过先依次形成第一钝化层与平坦层，之后对平坦层进行图形化处理及退火处理，在对平坦层进行退火处理的过程中，由于平坦层与源漏极之间设有第一钝化层，不能够相接触，因此不会发生反应生成络合物，有利于提高阵列基板的电学性能，实现信号导通；与现有的阵列基板的制作方法相比，本发明还可以至少减少一道光罩，有利于提升工艺效果，缩短制程时间，降低生产成本。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为现有的一种阵列基板的制作方法的示意图；
图2为本发明的阵列基板的制作方法的步骤1的示意图；
图3为本发明的阵列基板的制作方法的步骤2的示意图；
图4为本发明的阵列基板的制作方法的步骤3的示意图；
图5-6为本发明的阵列基板的制作方法的步骤4的示意图；
图7为本发明的阵列基板的制作方法的步骤5的示意图暨本发明制得的阵列基板的结构示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图2-7，本发明提供一种阵列基板的制作方法，包括如下步骤：
步骤1、如图2所示，提供一基板10，在所述基板10上依次形成栅极15、栅极绝缘层20、有源层25、及源/漏极30。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述栅极15、及源/漏极30的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。所述源/漏极30的材料优选为铜。
具体的，所述栅极绝缘层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述有源层25的材料为铟镓锌氧化物(IGZO，indium gallium zinc oxide)。
步骤2、如图3所示，在所述源/漏极30及栅极绝缘层20上形成第一钝化层40，在所述第一钝化层40上形成平坦层50，采用一道光罩对所述平坦层50进行曝光、显影，以对所述平坦层50进行图形化处理，得到对应于源/漏极30上方的第一通孔51。
具体的，所述平坦层50的材料为正性光阻。
具体的，所述步骤2还包括：在所述平坦层50上形成第一通孔51后，对所述平坦层50进行退火(anneal)处理，使其加热固化。在对平坦层50进行退火处理时，由于平坦层50与源/漏极30之间设有第一钝化层40不能够相接触，因此不会发生反应生成络合物。
步骤3、如图4所示，在所述平坦层50上沉积第一透明导电层，并采用一道光刻制程对所述第一透明导电层进行图形化处理，形成公共电极60。
具体的，所述公共电极60的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述步骤3还包括：对所述公共电极60进行退火处理，使其中的透明导电金属氧化物加热固化结晶，从而改善公共电极60的膜质结构，降低方块电阻，使其结构更稳定，寿命更长。
步骤4、如图5所示，在所述公共电极60、平坦层50上形成第二钝化层70，所述第二钝化层70包覆第一通孔51并与第一钝化层40相接触；
如图6所示，采用一道光刻制程对所述第二钝化层70上位于第一通孔51底部的部分进行开孔处理，得到位于第二钝化层70上的第二通孔71，沿所述第二通孔71继续对第一钝化层40进行蚀刻，得到对应于第二通孔71的第三通孔41。
具体的，所述第一钝化层40与第二钝化层70的材质和膜厚相同，这样可以减少不同材质在干蚀刻过程中带来的底切问题(under cut issue)。
具体的，所述第一钝化层40与第二钝化层70为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
优选的，所述第一钝化层40与第二钝化层70的膜厚为
Figure PCTCN2016078876-appb-000004
具体的，所述第二通孔71与第三通孔41的尺寸小于所述第一通孔51的尺寸。
优选的，所述第一通孔51、第二通孔71、及第三通孔41均为圆形孔，所述第一通孔51的直径为7-12μm，所述第二通孔71与第三通孔41的直径为3-5μm。
具体的，所述步骤4中，所述第二钝化层70的光刻制程中的蚀刻制程与所述第一钝化层40的蚀刻制程均为干蚀刻制程。所述步骤4采用一道光罩来实现所述第一钝化层40与第二钝化层70的开孔处理，与现有技术相比，可节约一道光罩，节约生产成本，降低制程时间。
步骤5、如图7所示，在所述第二钝化层70上沉积第二透明导电层，并采用一道光刻制程对所述第二透明导电层进行图形化处理，形成像素电极80，所述像素电极80经由第二通孔71与第三通孔41与源/漏极30相接触。
具体的，所述像素电极80的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述步骤5还包括：对所述像素电极80进行退火处理，使其中的透明导电金属氧化物加热固化结晶，从而改善像素电极80的膜质结构，降低方块电阻，使其结构更稳定，寿命更长。
请参阅图7，本发明还提供一种阵列基板，包括基板10、设于所述基板10上的栅极15、设于所述栅极15及基板10上的栅极绝缘层20、设于所述栅极绝缘层20上的有源层25、设于所述有源层25及栅极绝缘层20上的源/漏极30、设于所述源/漏极30、有源层25、及栅极绝缘层20上的第一钝化层40、设于所述第一钝化层40上的平坦层50、设于所述平坦层50上的公共电极60、设于所述公共电极60、及平坦层50上的第二钝化层70、及设于所述第二钝化层70上的像素电极80。
所述平坦层50上设有对应于源/漏极30上方的第一通孔51，所述第二钝化层70上位于所述第一通孔51底部的部分上设有第二通孔71，所述第一钝化层40上设有与所述第二通孔71相贯通的第三通孔41，所述像素电极80经由第二通孔71与第三通孔41与源/漏极30相接触。
具体的，所述基板10为透明基板，优选为玻璃基板。
具体的，所述栅极15、及源/漏极30的材料为钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种的堆栈组合。所述源/漏极30的材料优选为铜。
具体的，所述栅极绝缘层20为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
具体的，所述有源层25的材料为铟镓锌氧化物(IGZO，indium gallium zinc oxide)。
具体的，所述平坦层50的材料为正性光阻。
具体的，所述公共电极60、及像素电极80的材料为透明导电金属氧化物，如氧化铟锡(ITO)等。
优选的，所述第一钝化层40与第二钝化层70的材质和膜厚相同。
具体的，所述第一钝化层40与第二钝化层70为氧化硅(SiOx)层、氮化硅(SiNx)层、或者由氧化硅层与氮化硅层叠加构成的复合层。
优选的，所述第一钝化层40与第二钝化层70的膜厚为
Figure PCTCN2016078876-appb-000005
具体的，所述第二通孔71与第三通孔41的尺寸小于所述第一通孔51的尺寸。
优选的，所述第一通孔51、第二通孔71、及第三通孔41均为圆形孔，所述第一通孔51的直径为7-12μm，所述第二通孔71与第三通孔41的直径为3-5μm。
综上所述，本发明提供的一种阵列基板的制作方法，通过先依次形成第一钝化层与平坦层，之后对平坦层进行图形化处理及退火处理，在对平坦层进行退火处理的过程中，由于平坦层与源漏极之间设有第一钝化层，不能够相接触，因此不会发生反应生成络合物，有利于提高阵列基板的电学性能，实现信号导通；与现有的阵列基板的制作方法相比，本发明还可以至少减少一道光罩，有利于提升工艺效果，缩短制程时间，降低生产成本。本发明制得的阵列基板，信号传导畅通，具有良好的电学性能。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (12)

  1. 一种阵列基板的制作方法，包括如下步骤：
    步骤1、提供一基板，在所述基板上依次形成栅极、栅极绝缘层、有源层、及源/漏极；
    步骤2、在所述源/漏极及栅极绝缘层上形成第一钝化层，在所述第一钝化层上形成平坦层，对所述平坦层进行图形化处理，得到对应于源/漏极上方的第一通孔；
    步骤3、在所述平坦层上沉积第一透明导电层，并对所述第一透明导电层进行图形化处理，形成公共电极；
    步骤4、在所述公共电极、平坦层上形成第二钝化层，所述第二钝化层包覆第一通孔并与第一钝化层相接触；
    对所述第二钝化层上位于第一通孔底部的部分进行开孔处理，得到位于第二钝化层上的第二通孔，沿所述第二通孔继续对第一钝化层进行蚀刻，得到对应于第二通孔的第三通孔；
    步骤5、在所述第二钝化层上沉积第二透明导电层，并对所述第二透明导电层进行图形化处理，形成像素电极，所述像素电极经由第二通孔与第三通孔与源/漏极相接触。
  2. 如权利要求1所述的阵列基板的制作方法，其中，所述第一钝化层与第二钝化层的材质和膜厚相同。
  3. 如权利要求2所述的阵列基板的制作方法，其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
    Figure PCTCN2016078876-appb-100001
  4. 如权利要求1所述的阵列基板的制作方法，其中，所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
  5. 如权利要求4所述的阵列基板的制作方法，其中，所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
  6. 一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上的公共电极、设于所述公共电极、及平坦层上的第二钝化层、及设于所述第二 钝化层上的像素电极；
    所述平坦层上设有对应于源/漏极上方的第一通孔，所述第二钝化层上位于所述第一通孔底部的部分上设有第二通孔，所述第一钝化层上设有与所述第二通孔相贯通的第三通孔，所述像素电极经由第二通孔与第三通孔与源/漏极相接触。
  7. 如权利要求6所述的阵列基板，其中，所述第一钝化层与第二钝化层的材质和膜厚相同。
  8. 如权利要求7所述的阵列基板，其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
    Figure PCTCN2016078876-appb-100002
  9. 如权利要求7所述的阵列基板，其中，所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
  10. 如权利要求9所述的阵列基板，其中，所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
  11. 一种阵列基板，包括基板、设于所述基板上的栅极、设于所述栅极及基板上的栅极绝缘层、设于所述栅极绝缘层上的有源层、设于所述有源层及栅极绝缘层上的源/漏极、设于所述源/漏极、有源层、及栅极绝缘层上的第一钝化层、设于所述第一钝化层上的平坦层、设于所述平坦层上的公共电极、设于所述公共电极、及平坦层上的第二钝化层、及设于所述第二钝化层上的像素电极；
    所述平坦层上设有对应于源/漏极上方的第一通孔，所述第二钝化层上位于所述第一通孔底部的部分上设有第二通孔，所述第一钝化层上设有与所述第二通孔相贯通的第三通孔，所述像素电极经由第二通孔与第三通孔与源/漏极相接触；
    其中，所述第一钝化层与第二钝化层的材质和膜厚相同；
    其中，所述第一钝化层与第二钝化层为氧化硅层、氮化硅层、或者由氧化硅层与氮化硅层叠加构成的复合层；所述第一钝化层与第二钝化层的膜厚为
    Figure PCTCN2016078876-appb-100003
    其中，所述第二通孔与第三通孔的尺寸小于所述第一通孔的尺寸。
  12. 如权利要求11所述的阵列基板，其中，所述第一通孔、第二通孔、及第三通孔均为圆形孔，所述第一通孔的直径为7-12μm，所述第二通孔与第三通孔的直径为3-5μm。
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