WO2017201791A1 - Tft基板的制作方法及tft基板 - Google Patents

Tft基板的制作方法及tft基板 Download PDF

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Publication number
WO2017201791A1
WO2017201791A1 PCT/CN2016/086849 CN2016086849W WO2017201791A1 WO 2017201791 A1 WO2017201791 A1 WO 2017201791A1 CN 2016086849 W CN2016086849 W CN 2016086849W WO 2017201791 A1 WO2017201791 A1 WO 2017201791A1
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Prior art keywords
gate
active layer
substrate
layer
drain
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PCT/CN2016/086849
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English (en)
French (fr)
Inventor
周志超
夏慧
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深圳市华星光电技术有限公司
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Priority to US15/115,914 priority Critical patent/US10297692B2/en
Publication of WO2017201791A1 publication Critical patent/WO2017201791A1/zh

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Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method for fabricating a TFT substrate and a TFT substrate.
  • LCDs liquid crystal displays
  • Various consumer electronic products such as digital assistants, digital cameras, notebook computers, and desktop computers have become mainstream in display devices.
  • liquid crystal display devices which include a liquid crystal display panel and a backlight module.
  • the working principle of the liquid crystal display panel is to place liquid crystal molecules in two parallel glass substrates. There are many vertical and horizontal small wires between the two glass substrates, and the liquid crystal molecules are controlled to change direction by energizing or not, and the light of the backlight module is changed. Refracted to produce a picture.
  • a liquid crystal display panel comprises a CF (Color Filter) substrate, a thin film transistor (TFT) substrate, and a liquid crystal (LC, Liquid Crystal) and a sealant interposed between the color filter substrate and the thin film transistor substrate.
  • the composition of the frame generally includes: an Array process (film, yellow light, etching and stripping), a middle cell process (a TFT substrate and a CF substrate), and a rear stage. Module assembly process (drive IC and printed circuit board is pressed).
  • the front Array process mainly forms a TFT substrate to control the movement of liquid crystal molecules; the middle Cell process mainly adds liquid crystal between the TFT substrate and the CF substrate; the rear module assembly process is mainly to drive the IC to press and print the circuit.
  • the integration of the plates drives the liquid crystal molecules to rotate and display images.
  • the current TFT substrate often adopts a single gate structure, and the carrier structure of the TFT substrate with a single gate structure changes after a long period of operation, which is embodied in the threshold voltage.
  • a positive or negative offset occurs with the extension of the working time, thereby affecting the switching characteristics of the TFT.
  • An object of the present invention is to provide a method for fabricating a TFT substrate, which can effectively prevent variations in threshold voltage of a TFT, improve contact interface between a gate insulating layer and an active layer, and improve switching of the TFT. characteristic.
  • Another object of the present invention is to provide a TFT substrate which can effectively prevent variations in the threshold voltage of the TFT, improve the contact interface between the gate insulating layer and the active layer, and improve the switching characteristics of the TFT.
  • the present invention first provides a method for fabricating a TFT substrate, comprising the following steps:
  • Step 1 providing a substrate, forming a data line on the substrate, and a source connected to the data line;
  • Step 2 forming an active layer, the active layer is at least partially located on the source;
  • Step 3 forming a gate insulating layer on the active layer, the source, and the substrate, patterning the gate insulating layer, and forming a corresponding on the gate insulating layer a first through hole of the source layer;
  • Step 4 forming a first gate, a second gate, and a drain, wherein the first gate and the second gate are both located on the gate insulating layer, and respectively correspond to both sides of the active layer
  • the drain is at least partially located in the first via hole and connected to the active layer through the first via hole;
  • Step 5 forming a passivation layer on the drain, the first gate, the second gate, and the gate insulating layer, patterning the passivation layer, and forming a corresponding on the passivation layer a second via hole at the drain;
  • Step 6 Form a pixel electrode, the pixel electrode being at least partially located in the second via hole and connected to the drain through the second via hole.
  • the step 1 includes: depositing a first metal layer on the substrate by using a physical vapor deposition method, and patterning the first metal layer by a photolithography process to obtain a data line and connecting to the data line.
  • the lithography process includes a photoresist, exposure, development, and wet etching process;
  • the step 2 includes: depositing a semiconductor layer on the substrate substrate, the data line, and the source by a chemical or physical vapor deposition method, and patterning the semiconductor layer by a photolithography process to obtain a corresponding source An active layer above the pole; the lithography process includes a photoresist, exposure, development, and etching process;
  • the material of the data line and the source includes one or more of molybdenum, titanium, aluminum, and copper;
  • the material of the active layer is amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor.
  • the step 3 includes: depositing a first insulating layer on the active layer, the source, the data line, and the substrate by using a chemical vapor deposition method, and patterning the first insulating layer by using a photolithography process After processing, a first via hole corresponding to the active layer is obtained to form a gate insulating layer; the photolithography process includes a photoresist, exposure, development, and dry etching process;
  • the material of the gate insulating layer includes one or more of silicon oxide and silicon nitride.
  • the step 4 includes: depositing a second metal layer on the gate insulating layer by using a physical vapor deposition method, and patterning the second metal layer by a photolithography process to obtain a drain and a first gate. And a second gate; the photolithography process includes a photoresist, exposure, development, and wet etching process;
  • the material of the drain and the first and second gates includes one or more of molybdenum, titanium, aluminum, and copper.
  • the present invention also provides an array substrate, comprising: a substrate substrate, a source disposed on the substrate, and an active layer, a gate insulating layer, and a first gate disposed above the source; a second gate, a drain, a passivation layer, and a pixel electrode, wherein
  • a first via hole is formed in the gate insulating layer, and the drain is at least partially located in the first via hole and connected to the active layer through the first via hole;
  • the gate insulating layer a first gate and a second gate are disposed between the passivation layer, and the first gate and the second gate are disposed on two sides of the active layer;
  • a second via hole is formed in the passivation layer, and the pixel electrode is connected to the drain through the second via hole.
  • a data line is disposed on the base substrate, and the data line is connected to the source and disposed in the same layer as the source.
  • the first via is located above the active layer, and the orthographic projection of the drain on the substrate completely covers the orthographic projection of the active layer on the substrate.
  • the positions of the first gate and the second gate in the vertical direction at least partially overlap with the position of the active layer in the vertical direction.
  • the second via is located above the drain, and the orthographic projection of the pixel electrode on the substrate substantially covers the orthographic projection of the drain and the active layer on the substrate.
  • the first gate and the second gate have the same shape and size, the same position in the vertical direction, and the same distance from the active layer in the horizontal direction.
  • the present invention also provides an array substrate, comprising: a substrate substrate, a source disposed on the substrate, and an active layer, a gate insulating layer, and a first gate disposed above the source; a second gate, a drain, a passivation layer, and a pixel electrode, wherein
  • a first via hole is formed in the gate insulating layer, and the drain is at least partially located in the first via hole and connected to the active layer through the first via hole;
  • the gate insulating layer a first gate and a second gate are disposed between the passivation layer, and the first gate and the second gate are disposed on two sides of the active layer;
  • a second via hole is formed in the passivation layer, and the pixel electrode is connected to the drain through the second via hole;
  • the base substrate is provided with a data line, and the data line is connected to the source and is disposed in the same layer as the source;
  • first via is located above the active layer, and the orthographic projection of the drain on the substrate completely covers the orthographic projection of the active layer on the substrate.
  • the TFT substrate provided by the present invention adopts a double gate structure, and the double gate is symmetrically distributed on both sides of the active layer, which can effectively prevent the threshold voltage variation of the TFT and improve the switching characteristics of the TFT.
  • the gate insulating layer is directly grown on the active layer by first forming the active layer, thereby improving the contact interface between the gate insulating layer and the active layer, and further improving the switching characteristics of the TFT.
  • the TFT substrate provided by the present invention is different from the conventional TFT substrate of the bottom gate or the top gate structure, so that the gate is located between the source and the pixel electrode in the vertical direction, and the double gate structure symmetrical to the active layer is adopted.
  • the TFT threshold voltage can be effectively prevented from changing, and the switching characteristics of the TFT can be improved.
  • the contact interface between the gate insulating layer and the active layer is improved, and the switching characteristics of the TFT are further improved.
  • FIG. 1 is a flow chart showing a method of fabricating a TFT substrate of the present invention
  • FIGS. 2A-2B are schematic views showing a step 1 of a method of fabricating a TFT substrate of the present invention
  • FIG. 2C is a top plan view of FIG. 2B;
  • 3A-3B are schematic views showing a step 2 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 3C is a top plan view of FIG. 3B;
  • 4A-4B are schematic views showing a step 3 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 4C is a top plan view of FIG. 4B;
  • 5A-5B are schematic views showing a step 4 of a method of fabricating a TFT substrate of the present invention.
  • Figure 5C is a top plan view of Figure 5B;
  • 6A-6B are schematic views showing a step 5 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 6C is a top plan view of FIG. 6B;
  • FIGS. 7A-7B are schematic views showing a step 6 of a method of fabricating a TFT substrate of the present invention.
  • FIG. 7C is a top plan view of FIG. 7B.
  • the present invention provides a method for fabricating a TFT substrate, including the following steps:
  • Step 1 as shown in FIGS. 2A-2C, a substrate 10 is provided on which a data line 21 and a source 22 connected to the data line 21 are formed.
  • the step 1 includes: depositing a first metal layer 15 on the base substrate 10 by using a physical vapor deposition method (PVD), and performing the photolithography process on the first metal layer 15 After the patterning process, the data line 21 and the source 22 connected to the data line 21 are obtained; the photolithography process includes a photoresist, exposure, development, and wet etching process.
  • PVD physical vapor deposition method
  • the material of the data line 21 and the source 22 includes one or more of molybdenum (Mo), titanium (Ti), aluminum (Al), and copper (Cu).
  • Step 2 As shown in FIGS. 3A-3C, an active layer 30 is formed, the active layer 30 being at least partially located on the source 22.
  • the step 2 includes: depositing a semiconductor layer 25 on the base substrate 10, the data line 21, and the source 22 by using a chemical vapor deposition (CVD) method or a physical vapor deposition method.
  • the lithography process performs patterning on the semiconductor layer 25 to obtain an active layer 30 corresponding to the source 22; the lithography process includes a photoresist, exposure, development, and etching process.
  • the material of the active layer 30 is amorphous silicon, polycrystalline silicon, or a metal oxide semiconductor.
  • the metal oxide semiconductor may be Indium Gallium Zinc Oxide (IGZO).
  • the semiconductor layer 25 is deposited by a chemical vapor deposition method, and the etching process in the photolithography process is a dry etching process.
  • the semiconductor layer 25 is deposited by a physical vapor deposition process, and the etching process in the photolithography process is a wet etching process.
  • Step 3 as shown in FIGS. 4A-4C, a gate insulating layer 40 is formed on the active layer 30, the source 22, the data line 21, and the base substrate 10, and the gate insulating layer 40 is patterned.
  • a first via hole 41 corresponding to the active layer 30 is formed on the gate insulating layer 40.
  • the step 3 includes: depositing a first insulating layer 35 on the active layer 30, the source 22, the data line 21, and the base substrate 10 by using a chemical vapor deposition method, using a photolithography process
  • the first insulating layer 35 is patterned to obtain a first via hole 41 corresponding to the active layer 30 to form a gate insulating layer 40;
  • the photolithography process includes photoresist, exposure, development, and Dry etching process.
  • the material of the gate insulating layer 40 includes one or more of silicon oxide (SiO x ) and silicon nitride (SiN x ).
  • Step 4 as shown in FIGS. 5A-5C, forming a first gate 52, a second gate 53, and a drain 51.
  • the first gate 52 and the second gate 53 are both located on the gate insulating layer 40.
  • the drain electrode 51 is at least partially located in the first through hole 41 and connected to the active layer 30 through the first through hole 41.
  • the positions of the first gate 52 and the second gate 53 in the vertical direction at least partially overlap with the position of the active layer 30 in the vertical direction.
  • the positions of the first gate 52 and the second gate 53 in the vertical direction completely overlap with the positions of the active layer 30 in the vertical direction.
  • the first gate 52 and the second gate 53 have the same shape and size, the same position in the vertical direction, and the same distance from the active layer 30 in the horizontal direction.
  • the orthographic projection of the drain 51 on the substrate substrate 10 completely covers the orthographic projection of the active layer 30 on the substrate substrate 10.
  • the step 4 includes: depositing a second metal layer 45 on the gate insulating layer 40 by using a physical vapor deposition method, and patterning the second metal layer 45 by using a photolithography process to obtain a leak.
  • the lithography process includes photoresisting, exposure, development, and wet etching processes.
  • the material of the drain 51 and the first and second gate electrodes 52, 53 includes one or more of molybdenum, titanium, aluminum, and copper.
  • Step 5 as shown in FIGS. 6A-6C, a passivation layer 60 is formed on the drain 51, the first gate 52, the second gate 53, and the gate insulating layer 40, and the passivation layer 60 is formed.
  • a patterning process is performed to form a second via 61 corresponding to the upper side of the drain 51 on the passivation layer 60.
  • the step 5 includes: depositing a second insulating layer 55 on the drain 51, the first gate 52, the second gate 53, and the gate insulating layer 40 by using a chemical vapor deposition method, using a light
  • the second insulating layer 55 is patterned to obtain a second via hole 61 corresponding to the drain 51 to form a passivation layer 60.
  • the lithography process includes photoresisting, exposure, development, and dry etching processes.
  • the material of the passivation layer 60 includes one or more of silicon oxide and silicon nitride.
  • Step 6 as shown in FIGS. 7A-7C, a pixel electrode 70 is formed.
  • the pixel electrode 70 is at least partially located in the second via hole 61 and connected to the drain electrode 51 through the second via hole 61.
  • the orthographic projection of the pixel electrode 70 on the substrate 10 completely covers the orthographic projection of the drain 51 and the active layer 30 on the substrate 10.
  • the step 6 includes: depositing a conductive layer 65 on the passivation layer 60 by a physical vapor deposition method, and patterning the conductive layer 65 by a photolithography process to obtain a pixel electrode 70.
  • the lithography process includes photoresisting, exposure, development, and wet etching processes.
  • the material of the pixel electrode 70 is a metal or a conductive metal oxide
  • the metal includes one or more of molybdenum, titanium, aluminum, and copper
  • the conductive metal oxide is preferably indium tin oxide (Indium). Tin Qxide, ITO).
  • the method for fabricating the TFT substrate adopts a double gate structure, and the double gate is symmetrically distributed on both sides of the active layer, so that when a voltage is applied to the active layer by the double gate, the electric field distribution in the active layer is uniform and can be effective.
  • the contact interface further enhances the switching characteristics of the TFT.
  • the present invention further provides a TFT substrate, including: a substrate substrate 10, a source 22 disposed on the substrate substrate 10, and an active layer disposed above the source electrode 22. a gate insulating layer 40, a first gate 52, a second gate 53, a drain 51, a passivation layer 60, and a pixel electrode 70, wherein
  • a first through hole 41 is defined in the gate insulating layer 40, and the drain 51 is at least partially located in the first through hole 41 and connected to the active layer 30 through the first through hole 41;
  • a first gate 52 and a second gate 53 are disposed between the gate insulating layer 40 and the passivation layer 60, and the first gate 52 and the second gate 53 are disposed on the active layer. 30 sides;
  • a second via hole 61 is formed in the passivation layer 60, and the pixel electrode 70 is connected to the drain electrode 51 through the second via hole 61.
  • the base substrate 10 is provided with a data line 21 connected to the source 22 and disposed in the same layer as the source 22 .
  • the first through hole 41 is located above the active layer 30, and the orthographic projection of the drain 51 on the base substrate 10 completely covers the orthographic projection of the active layer 30 on the base substrate 10. .
  • a position of the first gate 52 and the second gate 53 in a vertical direction at least partially overlaps a position of the active layer 30 in a vertical direction.
  • the positions of the first gate 52 and the second gate 53 in the vertical direction completely overlap with the positions of the active layer 30 in the vertical direction.
  • the second through hole 51 is located above the drain 51, and the orthographic projection of the pixel electrode 70 on the base substrate 10 completely covers the drain 51 and the active layer 30 on the base substrate 10. Orthographic projection.
  • the shape and size of the first gate 52 and the second gate 53 are the same, in the vertical direction
  • the upward positions are the same, and the distance from the active layer 30 is the same in the horizontal direction.
  • the material of the data line 21 and the source 22 includes one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the active layer 30 is amorphous silicon or polycrystalline silicon.
  • the material of the gate insulating layer 40 includes one or more of silicon oxide and silicon nitride.
  • the material of the drain 51 and the first and second gates 53 includes one or more of molybdenum, titanium, aluminum, and copper.
  • the material of the passivation layer 60 includes one or more of silicon oxide and silicon nitride.
  • the material of the pixel electrode 70 is a metal or a conductive metal oxide
  • the metal includes one or more of molybdenum, titanium, aluminum, and copper
  • the conductive metal oxide is preferably indium tin oxide.
  • the TFT substrate is different from the conventional TFT substrate of the bottom gate or top gate structure such that the gate is located between the source and the pixel electrode in the vertical direction, and a double gate structure is employed, and the double gate is active
  • the two sides of the layer are symmetrically distributed, so that when a voltage is applied to the active layer by the double gate, the electric field distribution in the active layer is uniform, which can effectively prevent the threshold voltage of the TFT from changing, and improve the switching characteristics of the TFT;
  • the method of fabricating the gate insulating layer is to grow the gate insulating layer on the active layer, thereby improving the contact interface between the gate insulating layer and the active layer, and further improving the switching characteristics of the TFT.
  • the present invention provides a method of fabricating a TFT substrate and a TFT substrate.
  • the method for fabricating the TFT substrate of the present invention adopts a double gate structure, and the double gate is symmetrically distributed on both sides of the active layer, which can effectively prevent the threshold voltage variation of the TFT and improve the switching characteristics of the TFT;
  • the gate insulating layer is directly grown on the active layer, the contact interface between the gate insulating layer and the active layer is improved, and the switching characteristics of the TFT are further improved.
  • the TFT substrate of the present invention is different from the conventional TFT substrate of the bottom gate or top gate structure such that the gate is located between the source and the pixel electrode in the vertical direction, and a double gate structure symmetrical to the active layer is used.
  • the TFT threshold voltage can be effectively prevented from changing, and the switching characteristics of the TFT can be improved.
  • the contact interface between the gate insulating layer and the active layer is improved, and the switching characteristics of the TFT are further improved.

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Abstract

一种TFT基板的制作方法及TFT基板。该TFT基板的制作方法采用双栅极结构，该双栅极在有源层（30）两侧对称分布，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时通过先制作有源层（30）后制作栅极绝缘层（40），使栅极绝缘层（40）直接生长于有源层（30）上，改善了栅极绝缘层（40）与有源层（30）的接触界面，进一步提升TFT的开关特性。该TFT基板区别于底栅或顶栅结构的TFT基板，使栅极（52）、（53）在竖直方向上位于源极（22）和像素电极（70）之间，并且采用对称于有源层（30）的双栅极结构，能防止TFT阈值电压的变动，提升TFT的开关特性，同时改善栅极绝缘层（40）与有源层（30）的接触界面，提升TFT的开关特性。

Description

TFT基板的制作方法及TFT基板 技术领域
本发明涉及显示技术领域，尤其涉及一种TFT基板的制作方法及TFT基板。
背景技术
随着显示技术的发展，液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。
现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板及背光模组(backlight module)。液晶显示面板的工作原理是在两片平行的玻璃基板当中放置液晶分子，两片玻璃基板中间有许多垂直和水平的细小电线，通过通电与否来控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
通常液晶显示面板由彩膜(CF，Color Filter)基板、薄膜晶体管(TFT，Thin Film Transistor)基板、及夹设于彩膜基板与薄膜晶体管基板之间的液晶(LC，Liquid Crystal)及密封胶框(Sealant)组成，其成型工艺一般包括：前段阵列(Array)制程(薄膜、黄光、蚀刻及剥膜)、中段成盒(Cell)制程(TFT基板与CF基板贴合)、及后段模组组装制程(驱动IC与印刷电路板压合)。其中，前段Array制程主要是形成TFT基板，以便于控制液晶分子的运动；中段Cell制程主要是在TFT基板与CF基板之间添加液晶；后段模组组装制程主要是驱动IC压合与印刷电路板的整合，进而驱动液晶分子转动，显示图像。
在液晶显示面板工业中，目前的TFT基板常采用单一栅极结构，而单一栅极结构的TFT基板在较长时间的工作后其载流子运输特性会发生变化，具体体现在其阈值电压会随工作时间的延长而发生正向偏移或是负向偏移，从而影响TFT的开关特性。
发明内容
本发明的目的在于提供一种TFT基板的制作方法，能有效防止TFT阈值电压的变动，并改善栅极绝缘层与有源层的接触界面，提升TFT的开关 特性。
本发明的目的还在于提供一种TFT基板，能有效防止TFT阈值电压的变动，并改善栅极绝缘层与有源层的接触界面，提升TFT的开关特性。
为实现上述目的，本发明首先提供一种TFT基板的制作方法，包括如下步骤：
步骤1、提供一衬底基板，在所述衬底基板上形成数据线、及与数据线相连的源极；
步骤2、形成有源层，所述有源层至少部分位于所述源极上；
步骤3、在所述有源层、源极、及衬底基板上形成栅极绝缘层，对所述栅极绝缘层进行图形化处理，在所述栅极绝缘层上形成对应于所述有源层的第一通孔；
步骤4、形成第一栅极、第二栅极、及漏极，所述第一栅极、及第二栅极均位于栅极绝缘层上，且分别对应于所述有源层的两侧，所述漏极至少部分位于所述第一通孔内并通过第一通孔与所述有源层相连；
步骤5、在所述漏极、第一栅极、第二栅极、及栅极绝缘层上形成钝化层，对所述钝化层进行图形化处理，在所述钝化层上形成对应于漏极的第二通孔；
步骤6、形成像素电极，所述像素电极至少部分位于所述第二通孔内并通过第二通孔与漏极相连。
所述步骤1包括：采用物理气相沉积方法在所述衬底基板上沉积第一金属层，采用一道光刻制程对所述第一金属层进行图形化处理后得到数据线、及与数据线相连的源极；所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程；
所述步骤2包括：采用化学或物理气相沉积方法在所述衬底基板、数据线、及源极上沉积半导体层，采用一道光刻制程对所述半导体层进行图形化处理后得到对应于源极上方的有源层；所述光刻制程包括涂光阻、曝光、显影、及蚀刻制程；
所述数据线、及源极的材料包括钼、钛、铝、铜中的一种或多种；
所述有源层的材料为非晶硅、多晶硅、或金属氧化物半导体。
所述步骤3包括：采用化学气相沉积方法在所述有源层、源极、数据线、及衬底基板上沉积第一绝缘层，采用一道光刻制程对所述第一绝缘层进行图形化处理后得到对应于有源层的第一通孔，形成栅极绝缘层；所述光刻制程包括涂光阻、曝光、显影、及干蚀刻制程；
所述栅极绝缘层的材料包括氧化硅、氮化硅中的一种或多种。
所述步骤4包括：采用物理气相沉积方法在所述栅极绝缘层上沉积第二金属层，采用一道光刻制程对所述第二金属层进行图形化处理后得到漏极、第一栅极、及第二栅极；所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程；
所述漏极、及第一、第二栅极的材料包括钼、钛、铝、铜中的一种或多种。
本发明还提供一种阵列基板，包括：衬底基板、设于所述衬底基板上的源极、以及设于所述源极上方的有源层、栅极绝缘层、第一栅极、第二栅极、漏极、钝化层和像素电极，其中，
所述栅极绝缘层上开设有第一通孔，所述漏极至少部分位于所述第一通孔内并通过所述第一通孔与所述有源层相连；所述栅极绝缘层与所述钝化层之间设置有第一栅极和第二栅极，所述第一栅极和第二栅极分设于所述有源层两侧；
所述钝化层上开设有第二通孔，所述像素电极通过所述第二通孔与漏极相连。
所述衬底基板上设有数据线，所述数据线与所述源极相连并与所述源极同层设置。
所述第一通孔位于所述有源层上方，所述漏极在衬底基板上的正投影完全覆盖所述有源层在衬底基板上的正投影。
所述第一栅极和所述第二栅极在竖直方向上的位置与所述有源层在竖直方向上的位置至少部分重叠。
所述第二通孔位于所述漏极上方，所述像素电极在衬底基板上的正投影完全覆盖所述漏极与有源层在衬底基板上的正投影。
所述第一栅极和第二栅极的形状、尺寸相同，在竖直方向上的位置相同，在水平方向上与有源层的间隔距离相同。
本发明还提供一种阵列基板，包括：衬底基板、设于所述衬底基板上的源极、以及设于所述源极上方的有源层、栅极绝缘层、第一栅极、第二栅极、漏极、钝化层和像素电极，其中，
所述栅极绝缘层上开设有第一通孔，所述漏极至少部分位于所述第一通孔内并通过所述第一通孔与所述有源层相连；所述栅极绝缘层与所述钝化层之间设置有第一栅极和第二栅极，所述第一栅极和第二栅极分设于所述有源层两侧；
所述钝化层上开设有第二通孔，所述像素电极通过所述第二通孔与漏极相连；
其中，所述衬底基板上设有数据线，所述数据线与所述源极相连并与所述源极同层设置；
其中，所述第一通孔位于所述有源层上方，所述漏极在衬底基板上的正投影完全覆盖所述有源层在衬底基板上的正投影。
本发明的有益效果：本发明提供的TFT基板的制作方法，采用双栅极结构，所述双栅极在有源层两侧对称分布，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时通过先制作有源层后制作栅极绝缘层，使栅极绝缘层直接生长于有源层上，改善了栅极绝缘层与有源层的接触界面，进一步提升TFT的开关特性。本发明提供的TFT基板，区别于传统的底栅或顶栅结构的TFT基板，使栅极在竖直方向上位于源极和像素电极之间，并且采用对称于有源层的双栅极结构，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时改善了栅极绝缘层与有源层的接触界面，进一步提升TFT的开关特性。
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为本发明的TFT基板的制作方法的流程图；
图2A-2B为本发明的TFT基板的制作方法的步骤1的示意图；
图2C为图2B的俯视示意图；
图3A-3B为本发明的TFT基板的制作方法的步骤2的示意图；
图3C为图3B的俯视示意图；
图4A-4B为本发明的TFT基板的制作方法的步骤3的示意图；
图4C为图4B的俯视示意图；
图5A-5B为本发明的TFT基板的制作方法的步骤4的示意图；
图5C为图5B的俯视示意图；
图6A-6B为本发明的TFT基板的制作方法的步骤5的示意图；
图6C为图6B的俯视示意图；
图7A-7B为本发明的TFT基板的制作方法的步骤6的示意图；
图7C为图7B的俯视示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种TFT基板的制作方法，包括如下步骤：
步骤1、如图2A-2C所示，提供一衬底基板10，在所述衬底基板10上形成数据线21、及与数据线21相连的源极22。
具体的，所述步骤1包括：采用物理气相沉积方法(Physical Vapor Deposition，PVD)在所述衬底基板10上沉积第一金属层15，采用一道光刻制程对所述第一金属层15进行图形化处理后得到数据线21、及与数据线21相连的源极22；所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程。
具体的，所述数据线21、及源极22的材料包括钼(Mo)、钛(Ti)、铝(Al)、铜(Cu)中的一种或多种。
步骤2、如图3A-3C所示，形成有源层30，所述有源层30至少部分位于所述源极22上。
具体的，所述步骤2包括：采用化学气相沉积方法(Chemical Vapor Deposition，CVD)或物理气相沉积方法在所述衬底基板10、数据线21、及源极22上沉积半导体层25，采用一道光刻制程对所述半导体层25进行图形化处理后得到对应于源极22上方的有源层30；所述光刻制程包括涂光阻、曝光、显影、及蚀刻制程。
具体的，所述有源层30的材料为非晶硅、多晶硅、或金属氧化物半导体。优选的，所述金属氧化物半导体可以为铟镓锌氧化物(Indium Gallium Zinc Oxide,IGZO)。
所述有源层30的材料为非晶硅或多晶硅时，采用化学气相沉积方法沉积半导体层25，所述光刻制程中的蚀刻制程为干蚀刻制程。
所述有源层30的材料为金属氧化物半导体时，采用物理气相沉积方法沉积半导体层25，所述光刻制程中的蚀刻制程为湿蚀刻制程。
步骤3、如图4A-4C所示，在所述有源层30、源极22、数据线21、及衬底基板10上形成栅极绝缘层40，对所述栅极绝缘层40进行图形化处理，在所述栅极绝缘层40上形成对应于所述有源层30的第一通孔41。
具体的，所述步骤3包括：采用化学气相沉积方法在所述有源层30、源极22、数据线21、及衬底基板10上沉积第一绝缘层35，采用一道光刻制程对所述第一绝缘层35进行图形化处理后得到对应于有源层30的第一通孔41，形成栅极绝缘层40；所述光刻制程包括涂光阻、曝光、显影、及 干蚀刻制程。
具体的，所述栅极绝缘层40的材料包括氧化硅(SiOx)、氮化硅(SiNx)中的一种或多种。
步骤4、如图5A-5C所示，形成第一栅极52、第二栅极53、及漏极51，所述第一栅极52、及第二栅极53均位于栅极绝缘层40上，且分别对应于所述有源层30的两侧，所述漏极51至少部分位于所述第一通孔41内并通过第一通孔41与所述有源层30相连。
具体的，所述第一栅极52和第二栅极53在竖直方向上的位置与所述有源层30在竖直方向上的位置至少部分重叠。
优选的，所述第一栅极52与第二栅极53在竖直方向上的位置与所述有源层30在竖直方向上的位置完全重叠。
优选的，所述第一栅极52、第二栅极53的形状、尺寸相同，在竖直方向上的位置相同，在水平方向上与有源层30的间隔距离相同。
优选的，所述漏极51在衬底基板10上的正投影完全覆盖所述有源层30在衬底基板10上的正投影。
具体的，所述步骤4包括：采用物理气相沉积方法在所述栅极绝缘层40上沉积第二金属层45，采用一道光刻制程对所述第二金属层45进行图形化处理后得到漏极51、第一栅极52、及第二栅极53。所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程。
具体的，所述漏极51、及第一、第二栅极52、53的材料包括钼、钛、铝、铜中的一种或多种。
步骤5、如图6A-6C所示，在所述漏极51、第一栅极52、第二栅极53、及栅极绝缘层40上形成钝化层60，对所述钝化层60进行图形化处理，在所述钝化层60上形成对应于漏极51上方的第二通孔61。
具体的，所述步骤5包括：采用化学气相沉积方法在所述漏极51、第一栅极52、第二栅极53、及栅极绝缘层40上沉积第二绝缘层55，采用一道光刻制程对所述第二绝缘层55进行图形化处理后得到对应于漏极51的第二通孔61，形成钝化层60。所述光刻制程包括涂光阻、曝光、显影、及干蚀刻制程。
具体的，所述钝化层60的材料包括氧化硅、氮化硅中的一种或多种。
步骤6、如图7A-7C所示，形成像素电极70，所述像素电极70至少部分位于所述第二通孔61内并通过第二通孔61与漏极51相连。
具体的，所述像素电极70在衬底基板10上的正投影完全覆盖所述漏极51与有源层30在衬底基板10上的正投影。
至此，完成TFT基板的制作。
具体的，所述步骤6包括：采用物理气相沉积方法在所述钝化层60上沉积导电层65，采用一道光刻制程对所述导电层65进行图形化处理后得到像素电极70。所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程。
具体的，所述像素电极70的材料为金属或导电金属氧化物，所述金属包括钼、钛、铝、铜中的一种或多种，所述导电金属氧化物优选为氧化铟锡(Indium Tin Qxide，ITO)。
上述TFT基板的制作方法，采用双栅极结构，所述双栅极在有源层两侧对称分布，使得双栅极对有源层施加电压时，有源层内的电场分布均匀，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时通过先制作有源层后制作栅极绝缘层，使栅极绝缘层直接生长于有源层上，改善了栅极绝缘层与有源层的接触界面，进一步提升TFT的开关特性。
请参阅图7B-7C，本发明还提供一种TFT基板，包括：衬底基板10、设于所述衬底基板10上的源极22、以及设于所述源极22上方的有源层30、栅极绝缘层40、第一栅极52、第二栅极53、漏极51、钝化层60和像素电极70，其中，
所述栅极绝缘层40上开设有第一通孔41，所述漏极51至少部分位于所述第一通孔41内并通过所述第一通孔41与所述有源层30相连；所述栅极绝缘层40与所述钝化层60之间设置有第一栅极52和第二栅极53，所述第一栅极52和第二栅极53分设于所述有源层30两侧；
所述钝化层60上开设有第二通孔61，所述像素电极70通过所述第二通孔61与漏极51相连。
具体的，所述衬底基板10上设有数据线21，所述数据线21与所述源极22相连并与所述源极22同层设置。
具体的，所述第一通孔41位于所述有源层30上方，所述漏极51在衬底基板10上的正投影完全覆盖所述有源层30在衬底基板10上的正投影。
具体的，所述第一栅极52和所述第二栅极53在竖直方向上的位置与所述有源层30在竖直方向上的位置至少部分重叠。
优选的，所述第一栅极52和所述第二栅极53在竖直方向上的位置与所述有源层30在竖直方向上的位置完全重叠。
具体的，所述第二通孔51位于所述漏极51上方，所述像素电极70在衬底基板10上的正投影完全覆盖所述漏极51与有源层30在衬底基板10上的正投影。
优选的，所述第一栅极52、第二栅极53的形状、尺寸相同，在竖直方 向上的位置相同，在水平方向上与有源层30的间隔距离相同。
具体的，所述数据线21、及源极22的材料包括钼、钛、铝、铜中的一种或多种。
具体的，所述有源层30的材料为非晶硅或多晶硅。
具体的，所述栅极绝缘层40的材料包括氧化硅、氮化硅中的一种或多种。
具体的，所述漏极51、及第一、第二栅极53的材料包括钼、钛、铝、铜中的一种或多种。
具体的，所述钝化层60的材料包括氧化硅、氮化硅中的一种或多种。
具体的，所述像素电极70的材料为金属或导电金属氧化物，所述金属包括钼、钛、铝、铜中的一种或多种，所述导电金属氧化物优选为氧化铟锡。
上述TFT基板，区别于传统的底栅或顶栅结构的TFT基板，使栅极在竖直方向上位于源极和像素电极之间，并且采用双栅极结构，所述双栅极在有源层两侧对称分布，使得双栅极对有源层施加电压时，有源层内的电场分布均匀，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时通过先制作有源层后制作栅极绝缘层的方法，使栅极绝缘层生长于有源层上，改善了栅极绝缘层与有源层的接触界面，进一步提升TFT的开关特性。
综上所述，本发明提供一种TFT基板的制作方法及TFT基板。本发明的TFT基板的制作方法，采用双栅极结构，所述双栅极在有源层两侧对称分布，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时通过先制作有源层后制作栅极绝缘层，使栅极绝缘层直接生长于有源层上，改善了栅极绝缘层与有源层的接触界面，进一步提升TFT的开关特性。本发明的TFT基板，区别于传统的底栅或顶栅结构的TFT基板，使栅极在竖直方向上位于源极和像素电极之间，并且采用对称于有源层的双栅极结构，能有效防止TFT阈值电压的变动，提升TFT的开关特性；同时改善了栅极绝缘层与有源层的接触界面，进一步提升TFT的开关特性。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种TFT基板的制作方法，包括如下步骤：
    步骤1、提供一衬底基板，在所述衬底基板上形成数据线、及与数据线相连的源极；
    步骤2、形成有源层，所述有源层至少部分位于所述源极上；
    步骤3、在所述有源层、源极、数据线、及衬底基板上形成栅极绝缘层，对所述栅极绝缘层进行图形化处理，在所述栅极绝缘层上形成对应于所述有源层的第一通孔；
    步骤4、形成第一栅极、第二栅极、及漏极，所述第一栅极、及第二栅极均位于栅极绝缘层上，且分别对应于所述有源层的两侧，所述漏极至少部分位于所述第一通孔内并通过第一通孔与所述有源层相连；
    步骤5、在所述漏极、第一栅极、第二栅极、及栅极绝缘层上形成钝化层，对所述钝化层进行图形化处理，在所述钝化层上形成对应于漏极的第二通孔；
    步骤6、形成像素电极，所述像素电极至少部分位于所述第二通孔内并通过第二通孔与漏极相连。
  2. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤1包括：采用物理气相沉积方法在所述衬底基板上沉积第一金属层，采用一道光刻制程对所述第一金属层进行图形化处理后得到数据线、及与数据线相连的源极；所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程；
    所述步骤2包括：采用化学或物理气相沉积方法在所述衬底基板、数据线、及源极上沉积半导体层，采用一道光刻制程对所述半导体层进行图形化处理后得到对应于源极上方的有源层；所述光刻制程包括涂光阻、曝光、显影、及蚀刻制程；
    所述数据线、及源极的材料包括钼、钛、铝、铜中的一种或多种；
    所述有源层的材料为非晶硅、多晶硅、或金属氧化物半导体。
  3. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤3包括：采用化学气相沉积方法在所述有源层、源极、数据线、及衬底基板上沉积第一绝缘层，采用一道光刻制程对所述第一绝缘层进行图形化处理后得到对应于有源层的第一通孔，形成栅极绝缘层；所述光刻制程包括涂光阻、曝光、显影、及干蚀刻制程；
    所述栅极绝缘层的材料包括氧化硅、氮化硅中的一种或多种。
  4. 如权利要求1所述的TFT基板的制作方法，其中，所述步骤4包括：采用物理气相沉积方法在所述栅极绝缘层上沉积第二金属层，采用一道光刻制程对所述第二金属层进行图形化处理后得到漏极、第一栅极、及第二栅极；所述光刻制程包括涂光阻、曝光、显影、及湿蚀刻制程；
    所述漏极、及第一、第二栅极的材料包括钼、钛、铝、铜中的一种或多种。
  5. 一种阵列基板，包括：衬底基板、设于所述衬底基板上的源极、以及设于所述源极上方的有源层、栅极绝缘层、第一栅极、第二栅极、漏极、钝化层和像素电极，其中，
    所述栅极绝缘层上开设有第一通孔，所述漏极至少部分位于所述第一通孔内并通过所述第一通孔与所述有源层相连；所述栅极绝缘层与所述钝化层之间设置有第一栅极和第二栅极，所述第一栅极和第二栅极分设于所述有源层两侧；
    所述钝化层上开设有第二通孔，所述像素电极通过所述第二通孔与漏极相连。
  6. 如权利要求5所述的阵列基板，其中，所述衬底基板上设有数据线，所述数据线与所述源极相连并与所述源极同层设置。
  7. 如权利要求5所述的阵列基板，其中，所述第一通孔位于所述有源层上方，所述漏极在衬底基板上的正投影完全覆盖所述有源层在衬底基板上的正投影。
  8. 如权利要求5所述的阵列基板，其中，所述第一栅极和第二栅极在竖直方向上的位置与所述有源层在竖直方向上的位置至少部分重叠。
  9. 如权利要求5所述的阵列基板，其中，所述第二通孔位于所述漏极上方，所述像素电极在衬底基板上的正投影完全覆盖所述漏极与有源层在衬底基板上的正投影。
  10. 如权利要求8所述的TFT基板，其中，所述第一栅极和所述第二栅极的形状、尺寸相同，在竖直方向上的位置相同，在水平方向上与有源层的间隔距离相同。
  11. 一种阵列基板，包括：衬底基板、设于所述衬底基板上的源极、以及设于所述源极上方的有源层、栅极绝缘层、第一栅极、第二栅极、漏极、钝化层和像素电极，其中，
    所述栅极绝缘层上开设有第一通孔，所述漏极至少部分位于所述第一通孔内并通过所述第一通孔与所述有源层相连；所述栅极绝缘层与所述钝化层之间设置有第一栅极和第二栅极，所述第一栅极和第二栅极分设于所 述有源层两侧；
    所述钝化层上开设有第二通孔，所述像素电极通过所述第二通孔与漏极相连；
    其中，所述衬底基板上设有数据线，所述数据线与所述源极相连并与所述源极同层设置；
    其中，所述第一通孔位于所述有源层上方，所述漏极在衬底基板上的正投影完全覆盖所述有源层在衬底基板上的正投影。
  12. 如权利要求11所述的阵列基板，其中，所述第一栅极和第二栅极在竖直方向上的位置与所述有源层在竖直方向上的位置至少部分重叠。
  13. 如权利要求11所述的阵列基板，其中，所述第二通孔位于所述漏极上方，所述像素电极在衬底基板上的正投影完全覆盖所述漏极与有源层在衬底基板上的正投影。
  14. 如权利要求12所述的TFT基板，其中，所述第一栅极和所述第二栅极的形状、尺寸相同，在竖直方向上的位置相同，在水平方向上与有源层的间隔距离相同。
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Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106169485B (zh) * 2016-08-31 2019-06-14 深圳市华星光电技术有限公司 Tft阵列基板及其制作方法、显示装置
CN106571398B (zh) * 2016-10-17 2019-12-31 深圳市华星光电技术有限公司 一种薄膜晶体管及其制造方法、液晶面板
CN108987484A (zh) * 2018-07-27 2018-12-11 京东方科技集团股份有限公司 一种薄膜晶体管的制备方法和薄膜晶体管
TWI699753B (zh) * 2019-05-21 2020-07-21 友達光電股份有限公司 主動元件基板及其驅動方法
CN110265484B (zh) * 2019-06-26 2022-08-09 京东方科技集团股份有限公司 薄膜晶体管、阵列基板、显示装置
US11839071B2 (en) * 2021-07-22 2023-12-05 Taiwan Semiconductor Manufacturing Company Limited Vertical access transistors and methods for forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404321A (zh) * 2008-10-31 2009-04-08 中国科学院微电子研究所 一种垂直沟道有机场效应晶体管及其制备方法
US20110101355A1 (en) * 2009-10-30 2011-05-05 Semiconductor Energy Laboratory Co., Ltd. Non-linear element, display device, and electronic device

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4240424B2 (ja) * 1998-10-23 2009-03-18 エルジー ディスプレイ カンパニー リミテッド エッチング剤及びこれを用いた電子機器用基板の製造方法
KR101117948B1 (ko) * 2005-11-15 2012-02-15 가부시키가이샤 한도오따이 에네루기 켄큐쇼 액정 디스플레이 장치 제조 방법
US8106400B2 (en) * 2008-10-24 2012-01-31 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
CN102386236B (zh) * 2008-10-24 2016-02-10 株式会社半导体能源研究所 半导体器件和用于制造该半导体器件的方法
CN102668095B (zh) * 2009-10-30 2016-08-03 株式会社半导体能源研究所 晶体管
KR102117506B1 (ko) * 2009-12-04 2020-06-01 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 그 제조 방법
WO2014136636A1 (ja) * 2013-03-06 2014-09-12 住友化学株式会社 薄膜トランジスタ
CN103311310A (zh) * 2013-05-13 2013-09-18 北京京东方光电科技有限公司 一种薄膜晶体管及其制备方法、阵列基板
CN103489828B (zh) * 2013-09-30 2015-07-01 深圳市华星光电技术有限公司 薄膜晶体管阵列基板的制造方法
TWI624874B (zh) * 2014-12-03 2018-05-21 鴻海精密工業股份有限公司 一種垂直型電晶體及其製作方法
CN105047608B (zh) * 2015-08-26 2018-04-03 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置
US10782580B2 (en) * 2016-04-29 2020-09-22 Samsung Display Co., Ltd. Array substrate, liquid crystal display device having the same, and method for manufacturing array substrate

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101404321A (zh) * 2008-10-31 2009-04-08 中国科学院微电子研究所 一种垂直沟道有机场效应晶体管及其制备方法
US20110101355A1 (en) * 2009-10-30 2011-05-05 Semiconductor Energy Laboratory Co., Ltd. Non-linear element, display device, and electronic device

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