WO2015000255A1 - 阵列基板、显示装置及阵列基板的制造方法 - Google Patents
阵列基板、显示装置及阵列基板的制造方法 Download PDFInfo
- Publication number
- WO2015000255A1 WO2015000255A1 PCT/CN2013/088384 CN2013088384W WO2015000255A1 WO 2015000255 A1 WO2015000255 A1 WO 2015000255A1 CN 2013088384 W CN2013088384 W CN 2013088384W WO 2015000255 A1 WO2015000255 A1 WO 2015000255A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- gate
- via hole
- array substrate
- substrate
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 50
- 239000011347 resin Substances 0.000 claims abstract description 43
- 229920005989 resin Polymers 0.000 claims abstract description 43
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 45
- 238000000059 patterning Methods 0.000 claims description 30
- 239000010408 film Substances 0.000 claims description 27
- 239000000463 material Substances 0.000 claims description 23
- 239000011149 active material Substances 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 85
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 239000011241 protective layer Substances 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000002834 transmittance Methods 0.000 description 3
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- MGRWKWACZDFZJT-UHFFFAOYSA-N molybdenum tungsten Chemical compound [Mo].[W] MGRWKWACZDFZJT-UHFFFAOYSA-N 0.000 description 1
- 229910052755 nonmetal Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Definitions
- Embodiments of the present invention relate to an array substrate, a display device, and a method of fabricating an array substrate. Background technique
- TFT-LCD Thin Film Transistor Liquid Crystal Display
- TFT-LCD display modes mainly include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, IPS (In-Plane-Switching) mode, and AD-SDS (ADvanced).
- TN Transmission Nematic
- VA Very Alignment
- IPS In-Plane-Switching
- AD-SDS ADvanced
- Super Dimension Switch advanced super-dimensional field conversion technology, cartridge ADS
- the resin passivation layer has the characteristics of flat surface and low dielectric constant, in the actual production of the TFT-LCD array substrate, a resin passivation layer is usually introduced to further increase the aperture ratio and display brightness of the TFT-LCD product, and reduce The signal delay of TFT-LCD products ultimately improves the competitiveness of the product.
- the array substrate includes: a set of gate scan lines and a set of data scan lines, defined by the set of gate scan lines and a set of data scan lines. Pixel cells arranged in an array.
- each layer of the array substrate is formed by a patterning process, and each patterning process usually includes processes such as masking, exposure, development, etching, and stripping.
- An object of the present invention is to provide an array substrate, a display device, and a method for manufacturing an array substrate, which can effectively reduce the manufacturing cost of the array substrate, greatly shorten the manufacturing process, and further improve the yield of the product.
- An embodiment of the present invention provides an array substrate, including: a substrate substrate and a plurality of pixel units on a substrate of the substrate, each of the pixel units including a thin film transistor unit, wherein
- the thin film transistor unit includes: a gate electrode on the substrate of the substrate, a gate insulating layer above the gate, an active layer above the gate insulating layer and opposite to the gate position, An ohmic layer over the active layer, a source and a drain over the ohmic layer, and a resin passivation layer over the source and drain and covering the substrate.
- Another embodiment of the present invention provides a display device comprising the array substrate of the foregoing technical solution.
- a further embodiment of the present invention provides a method of fabricating an array substrate, including:
- a resin passivation layer over the source drain metal, the metal lead, and the data scan line and covering the substrate, forming a second via, a third via, and a fourth via of the resin passivation layer by a patterning process, a second via corresponding to a position at which a drain is to be formed, the third via corresponding to a position of the metal lead, and a position at which a channel is formed between the fourth via and the source and the drain Corresponding;
- the resin passivation layer directly covers the source and drain metal, after the pattern of the source and drain electrodes is formed in the manufacturing process of the array substrate, the fabrication of the channel protective layer is omitted. .
- the invention effectively reduces the manufacturing cost of the array substrate, greatly shortens the manufacturing process, effectively improves the display brightness of the TFT-LCD product, and improves the yield of the product.
- FIG. 1 is a schematic cross-sectional view of a pixel unit of an embodiment of an array substrate according to the present invention (taking the ADS mode as an example);
- FIG. 2 is a schematic cross-sectional view of a pixel unit after forming a gate according to an embodiment of the method of the present invention
- FIG. 3 is a schematic cross-sectional view showing a pixel unit after forming an active layer and an ohmic layer according to an embodiment of the method of the present invention
- FIG. 4 is a cross-sectional structural view showing a pixel unit after forming a first via hole of a gate insulating layer according to an embodiment of the method of the present invention
- FIG. 5 is a schematic cross-sectional view of a pixel unit after forming a source and drain metal according to an embodiment of the method of the present invention
- FIG. 6 is a schematic top plan view of a pixel unit after forming a source/drain metal according to an embodiment of the method of the present invention
- FIG. 7 is a schematic cross-sectional view showing a pixel unit after forming a resin passivation layer according to an embodiment of the method of the present invention.
- FIG. 8 is a schematic top plan view of a pixel unit after forming a resin passivation layer according to an embodiment of the method of the present invention
- FIG. 9 is a cross-sectional view showing a structure of a pixel unit after forming a transparent conductive metal film according to an embodiment of the method of the present invention.
- FIG. 10 is a schematic cross-sectional view showing a pixel unit after forming a source, a drain, and a first transparent electrode according to an embodiment of the method of the present invention
- FIG. 11 is a top plan view showing a pixel unit after forming a source, a drain, and a first transparent electrode according to an embodiment of the method;
- FIG. 12 is a schematic cross-sectional view showing a pixel unit after forming a second passivation layer according to an embodiment of the method of the present invention. detailed description
- One of the objects of the present invention is to provide an array substrate, a display device, and a method of fabricating the array substrate.
- the resin passivation layer of the array substrate directly covers the source and drain metal, in the manufacturing process of the array substrate After the pattern of the source and drain electrodes is formed, the fabrication of the channel protective layer is omitted.
- the invention can effectively reduce the manufacturing cost of the array substrate, greatly shorten the manufacturing process, and effectively improve the manufacturing process.
- the array substrate provided by the embodiment of the present invention includes a substrate substrate 1 and a plurality of pixel units located on the substrate 1 (in the figure, a cross section of one pixel unit is taken as an example).
- the array substrate also includes a GOA unit.
- Each of the pixel units includes a thin film transistor unit.
- the GOA unit includes: a first gate 2a (ie, a lead gate gate, hereinafter referred to as a first gate) located on the substrate 1 of the substrate, a gate insulating layer 3 overlying the first gate 2a and covering the substrate, and A metal lead 6c located above the gate insulating layer 3.
- a first gate 2a ie, a lead gate gate, hereinafter referred to as a first gate
- a gate insulating layer 3 overlying the first gate 2a and covering the substrate
- a metal lead 6c located above the gate insulating layer 3.
- the thin film transistor unit includes: a second gate 2b (ie, a gate of a thin film transistor, hereinafter referred to as a second gate) located above the substrate 1 and located above the gate insulating layer 3 and at the position of the second gate 2b
- a second gate 2b ie, a gate of a thin film transistor, hereinafter referred to as a second gate
- the opposite active layer 4 the ohmic layer 5 over the active layer 4, the source 6a and the drain 6b above the ohmic layer 5, and the resin blunt over the source 6a and the drain 6b and covering the substrate Layer 8.
- the GOA unit is located in a signal guiding area around the substrate.
- One pixel unit including a thin film transistor unit is schematically illustrated in the drawing and is adjacent to the GOA unit, however, not all of the pixel units are adjacent to the GOA unit.
- the substrate substrate 1 may be a glass substrate, a plastic substrate or a substrate of other materials.
- the material of the first gate 2a, the second gate 2b, the source 6a, the drain 6b and the metal lead 6c may be a single layer film of aluminum (A1), phase (Mo) or molybdenum-tungsten alloy (MoW).
- the material of the gate insulating layer 3 may be silicon nitride.
- the material of the active layer 4 is amorphous silicon (a-Si).
- the material of the ohmic layer 5 is a doped semiconductor (n + a-Si).
- the first gate 2a and the second gate 2b are located in the same layer.
- the array substrate further includes: a first transparent electrode 9 located on the resin passivation layer 8 , a second passivation layer 10 located above the first transparent electrode 9 and covering the substrate, A second transparent electrode 11 above the second passivation layer 10 and having a slit structure.
- the material of the first transparent electrode 9 and the second transparent electrode 11 may be indium tin oxide or the like.
- the second passivation layer 10 may be an inorganic insulating film such as silicon nitride or the like, or an organic insulating film such as a photosensitive resin material or a non-photosensitive resin material.
- the material of the resin passivation layer 8 is preferably a photosensitive resin material.
- the resin passivation layer 8 is in direct contact with the source 6a and the drain 6b.
- the second passivation layer 10 is in direct contact with the active layer.
- the present invention reduces the array substrate.
- the cost of production has greatly reduced the manufacturing process.
- the material of the channel protective layer is usually an inorganic insulating film such as silicon nitride
- the transmittance of the silicon nitride channel protective layer is 90% for visible light
- the transmittance of the resin passivation layer is 95%.
- the array substrate according to the embodiment of the invention further improves the display brightness of the TFT-LCD product, improves the yield of the product, and effectively reduces the power consumption of the TFT-LCD product.
- the embodiment of the invention provides an array substrate in the ADS mode, which can improve the picture quality of the TFT-LCD product, and has high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, no squeezing.
- the embodiment of the invention further provides a display device comprising any one of the above array substrates.
- the display device may be any product or component having a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, and the like.
- Step 301 forming a gate metal film on the substrate 1 and forming a first gate 2a, a second gate 2b, and a gate scan line connected to the second gate 2b by a patterning process (not shown) Out) the graphics.
- a patterning process not shown
- the patterning process usually includes the steps of substrate cleaning, film formation, photoresist coating, exposure, development, etching, photoresist stripping, etc.; the metal layer is usually formed by physical vapor deposition (for example, magnetron sputtering).
- the pattern is formed by wet etching, and the film is formed by chemical vapor deposition for the non-metal layer, and the pattern is formed by dry etching. The following steps are the same and will not be described again.
- Step 302 Forming a gate insulating layer 3, an active material layer and an ohmic material layer covering the substrate on the substrate on which the step 301 is completed, and forming the active layer 4 and the ohmic layer 5 by a patterning process.
- the cross-sectional structure of one pixel unit after forming the active layer 4 and the ohmic layer 5 is shown in Fig. 3.
- a gate insulating layer 3, an active material layer and an ohmic material layer are sequentially formed over the patterns of the first gate 2a, the second gate 2b and the gate scan line;
- the active layer 4 and the ohmic layer 5 are formed by a semi-transmissive film patterning process.
- the material of the active material layer is amorphous silicon (a-Si), and the material of the ohmic layer 5 is a doped semiconductor (n+ a-Si).
- Step 303 Form a first via hole H1 of the gate insulating layer 3 at a position corresponding to the first gate electrode 2a on the substrate on which the step 302 is completed by a patterning process.
- the cross-sectional structure of one pixel unit after forming the first via hole HI of the gate insulating layer 3 is shown in FIG.
- Step 304 Form a data line metal film covering the substrate on the substrate on which the step 303 is completed, and form a pattern of the source and drain metal, a pattern of the metal lead 6c, and a pattern of a data scan line (not shown) by a patterning process.
- the structure of one pixel unit after forming the source/drain metal is shown in Figs. 5 and 6.
- the source 6a and the drain 6b are not formed, that is, the channel between the source 6a and the drain 6b is not formed, and the source and drain metal at this time temporarily functions as a channel protective layer, effectively protecting the channel.
- the TFT characteristics of the channel are not formed, that is, the channel between the source 6a and the drain 6b is not formed, and the source and drain metal at this time temporarily functions as a channel protective layer, effectively protecting the channel.
- Step 305 Forming a resin passivation layer 8 covering the substrate on the substrate of the completion step 304, forming a second via hole H2, a third via hole H3, and a fourth via hole H4 of the resin passivation layer 8 by a patterning process.
- the structure of one pixel unit after forming the resin passivation layer 8 is shown in Figs. 7 and 8.
- the second via hole H2 corresponds to a position where a drain is to be formed
- the third via hole H3 is located in a signal guiding region of the substrate
- the third via hole H3 corresponds to a position of the metal lead 6c
- the fourth The via hole H4 corresponds to a position at which a channel is to be formed between the source 6a and the drain 6b.
- the material of the channel protective layer is usually made of silicon nitride material. Since the lateral etching rate of the silicon nitride material and the resin material are different, once the silicon nitride channel is under the resin passivation layer 8 The lateral etch rate of the layer is fast, which causes poor via chamfering at the channel.
- the source 6a and the drain 6b are not formed in step 305, and the active layer 4 at the channel is covered by the source and drain metal, thereby preventing the active layer at the channel from being blunt by the resin. The influence of the layer effectively solves the problem of poor chamfering when the fourth via hole H4 is formed in this step, and improves the yield of the product.
- Step 306 forming a transparent conductive metal film covering the substrate on the substrate on which step 305 is completed, and forming a source electrode 6a, a drain electrode 6b, a fifth via hole H5 of the ohmic layer 5, and a first transparent electrode 9 by a patterning process.
- the fifth via hole H5 corresponds to the position of the fourth via hole H4 of the resin passivation layer 8.
- the material of the transparent conductive metal film may be indium tin oxide or the like.
- the transparent conductive metal film forming the cover substrate in this step exposes the photoresist 12 to form the source 6a, the drain 6b, and the fifth via hole H5 of the ohmic layer 5 by a semi-transmissive film patterning process.
- the fifth via hole H5 corresponds to the position of the fourth via hole H4;
- the first transparent electrode 9 is formed by a gray tone mask patterning process.
- the structure of the one pixel unit after forming the source 6a, the drain 6b and the first transparent electrode 9 is shown in Figs. 10 and 11 .
- the first transparent electrode 9 is connected to the metal layer where the drain 6b is to be formed through the second via hole H2.
- Step 307 Form a second passivation layer 10 covering the substrate on the substrate on which the step 306 is completed, and form a sixth via hole H6 of the second passivation layer 10 in the signal guiding region of the substrate by a patterning process.
- the cross-sectional structure of one pixel unit after forming the second passivation layer 10 is shown in Fig. 12.
- Step 308 forming a transparent conductive metal film covering the substrate on the substrate of the step 307, and forming a second transparent electrode 11 having a slit structure by a patterning process.
- a cross-sectional structure of a pixel unit forming an array substrate of an embodiment of the present invention is shown in Fig. 1.
- the resin passivation layer 8 is in direct contact with the source 6a and the drain 6b; and the second passivation layer 10 is in direct contact with the active layer.
- the manufacturing method of the array substrate of the embodiment of the invention eliminates the fabrication of the channel protection layer, reduces the manufacturing cost, and reduces the production process, thereby greatly improving the yield of the product.
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/386,651 US9543324B2 (en) | 2013-07-03 | 2013-12-03 | Array substrate, display device and manufacturing method of the array substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201310277079.8A CN103383945B (zh) | 2013-07-03 | 2013-07-03 | 一种阵列基板、显示装置及阵列基板的制造方法 |
CN201310277079.8 | 2013-07-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2015000255A1 true WO2015000255A1 (zh) | 2015-01-08 |
Family
ID=49491697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2013/088384 WO2015000255A1 (zh) | 2013-07-03 | 2013-12-03 | 阵列基板、显示装置及阵列基板的制造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9543324B2 (zh) |
CN (1) | CN103383945B (zh) |
WO (1) | WO2015000255A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3261125A1 (en) * | 2016-06-23 | 2017-12-27 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103383945B (zh) | 2013-07-03 | 2015-10-14 | 北京京东方光电科技有限公司 | 一种阵列基板、显示装置及阵列基板的制造方法 |
CN104576526B (zh) * | 2013-12-19 | 2018-07-17 | 北京京东方光电科技有限公司 | 一种阵列基板及其制备方法和显示装置 |
CN104183607A (zh) * | 2014-08-14 | 2014-12-03 | 深圳市华星光电技术有限公司 | 阵列基板及其制造方法、显示装置 |
CN104299942A (zh) | 2014-09-12 | 2015-01-21 | 京东方科技集团股份有限公司 | 过孔制作方法、阵列基板制作方法及阵列基板、显示装置 |
CN104617040A (zh) | 2015-02-05 | 2015-05-13 | 京东方科技集团股份有限公司 | 一种阵列基板的制作方法、显示基板及显示装置 |
CN104576659A (zh) * | 2015-02-09 | 2015-04-29 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示装置 |
CN105070723B (zh) * | 2015-07-16 | 2018-12-28 | 深圳市华星光电技术有限公司 | 一种阵列基板的制作方法及阵列基板 |
KR102148491B1 (ko) | 2015-12-14 | 2020-08-26 | 엘지디스플레이 주식회사 | 박막트랜지스터 기판 |
CN105810692A (zh) * | 2016-04-18 | 2016-07-27 | 京东方科技集团股份有限公司 | 阵列基板、显示面板、显示装置及阵列基板制作方法 |
JP2018054719A (ja) * | 2016-09-27 | 2018-04-05 | 株式会社ジャパンディスプレイ | 半導体装置および表示装置 |
CN106449667B (zh) * | 2016-12-21 | 2017-12-22 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法、显示装置 |
CN106990632A (zh) * | 2017-04-14 | 2017-07-28 | 京东方科技集团股份有限公司 | 阵列基板及显示装置 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283428A (ja) * | 1992-04-03 | 1993-10-29 | Sharp Corp | 薄膜トランジスタ及びその製造方法 |
JP2001075126A (ja) * | 1999-07-06 | 2001-03-23 | Matsushita Electric Ind Co Ltd | 液晶画像表示装置と画像表示装置用半導体装置の製造方法 |
CN101640220A (zh) * | 2008-07-31 | 2010-02-03 | 株式会社半导体能源研究所 | 半导体装置及其制造方法 |
CN103383945A (zh) * | 2013-07-03 | 2013-11-06 | 北京京东方光电科技有限公司 | 一种阵列基板、显示装置及阵列基板的制造方法 |
CN203312296U (zh) * | 2013-07-03 | 2013-11-27 | 北京京东方光电科技有限公司 | 一种阵列基板及显示装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH09292633A (ja) * | 1996-02-27 | 1997-11-11 | Canon Inc | カラー液晶表示装置の製造方法 |
KR100475637B1 (ko) * | 2002-12-20 | 2005-03-10 | 엘지.필립스 엘시디 주식회사 | 반사형 액정표시장치 및 그의 제조방법 |
JP2007142388A (ja) * | 2005-11-17 | 2007-06-07 | Samsung Electronics Co Ltd | 薄膜トランジスタ表示板及びその製造方法 |
JP4245036B2 (ja) * | 2006-10-31 | 2009-03-25 | エプソンイメージングデバイス株式会社 | 液晶表示装置 |
TW200910590A (en) * | 2007-08-24 | 2009-03-01 | Au Optronics Corp | Method for manufacturing pixel structure |
TWI408812B (zh) * | 2007-12-10 | 2013-09-11 | Au Optronics Corp | 畫素結構的製作方法 |
TWI372282B (en) * | 2008-08-25 | 2012-09-11 | Au Optronics Corp | Liquid crystal display panel and manufacturing method thereof |
CN203312295U (zh) | 2013-07-02 | 2013-11-27 | 京东方科技集团股份有限公司 | 一种裸眼3d功能面板的信号基板及显示设备 |
-
2013
- 2013-07-03 CN CN201310277079.8A patent/CN103383945B/zh active Active
- 2013-12-03 US US14/386,651 patent/US9543324B2/en active Active
- 2013-12-03 WO PCT/CN2013/088384 patent/WO2015000255A1/zh active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05283428A (ja) * | 1992-04-03 | 1993-10-29 | Sharp Corp | 薄膜トランジスタ及びその製造方法 |
JP2001075126A (ja) * | 1999-07-06 | 2001-03-23 | Matsushita Electric Ind Co Ltd | 液晶画像表示装置と画像表示装置用半導体装置の製造方法 |
CN101640220A (zh) * | 2008-07-31 | 2010-02-03 | 株式会社半导体能源研究所 | 半导体装置及其制造方法 |
CN103383945A (zh) * | 2013-07-03 | 2013-11-06 | 北京京东方光电科技有限公司 | 一种阵列基板、显示装置及阵列基板的制造方法 |
CN203312296U (zh) * | 2013-07-03 | 2013-11-27 | 北京京东方光电科技有限公司 | 一种阵列基板及显示装置 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP3261125A1 (en) * | 2016-06-23 | 2017-12-27 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
CN107546231A (zh) * | 2016-06-23 | 2018-01-05 | 三星显示有限公司 | 薄膜晶体管阵列面板 |
US10217771B2 (en) | 2016-06-23 | 2019-02-26 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
US10396101B2 (en) | 2016-06-23 | 2019-08-27 | Samsung Display Co., Ltd. | Thin film transistor array panel and manufacturing method thereof |
CN107546231B (zh) * | 2016-06-23 | 2023-08-04 | 三星显示有限公司 | 薄膜晶体管阵列面板 |
Also Published As
Publication number | Publication date |
---|---|
US9543324B2 (en) | 2017-01-10 |
CN103383945B (zh) | 2015-10-14 |
US20160211277A1 (en) | 2016-07-21 |
CN103383945A (zh) | 2013-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO2015000255A1 (zh) | 阵列基板、显示装置及阵列基板的制造方法 | |
US9716110B2 (en) | Array substrate, method for manufacturing the same, and display device | |
EP2711769B1 (en) | Array substrate, display panel and method of manufacturing the array substrate | |
US9859304B2 (en) | Manufacturing method of array substrate, array substrate and display device | |
US9613986B2 (en) | Array substrate and its manufacturing method, display device | |
US8895334B2 (en) | Thin film transistor array substrate and method for manufacturing the same and electronic device | |
KR101900170B1 (ko) | 어레이 기판의 제조 방법, 어레이 기판 및 디스플레이 디바이스 | |
US20170307921A1 (en) | Thin Film Transistor Array Substrate, Manufacturing Method Therefor, and Display Device | |
EP3187929A1 (en) | Array substrate and manufacturing method therefor, and display apparatus | |
US9305945B2 (en) | TFT array substrate, manufacturing method of the same and display device | |
WO2017140058A1 (zh) | 阵列基板及其制作方法、显示面板及显示装置 | |
WO2014166181A1 (zh) | 薄膜晶体管及其制造方法、阵列基板及其制造方法、显示装置 | |
US8551822B2 (en) | Method for manufacturing array substrate | |
US20180350840A1 (en) | Array substrate, display panel, and display apparatus | |
WO2015192595A1 (zh) | 阵列基板及其制备方法、显示装置 | |
US9281325B2 (en) | Array substrate, manufacturing method thereof and display device | |
US20140132905A1 (en) | Array substrate and manufacture method of the same, liquid crystal display panel, and display device | |
US20160181278A1 (en) | Array substrate, method for manufacturing the same, and display device | |
US9690146B2 (en) | Array substrate, its manufacturing method, and display device | |
US8263447B2 (en) | Pixel structure and manufacturing method thereof and display panel | |
US20200203391A1 (en) | Array Substrate, Display Device, Thin Film Transistor, and Method for Manufacturing Array Substrate | |
US9261744B2 (en) | Array substrate, fabricating method thereof and display device | |
JP2012242839A (ja) | アレイ基板及びその製造方法 | |
US20070243673A1 (en) | Thin-film transistor array for lcd and the method for manufacturing the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 14386651 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 13888591 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
32PN | Ep: public notification in the ep bulletin as address of the adressee cannot be established |
Free format text: NOTING OF LOSS OF RIGHTS PURSUANT TO RULE 112(1) EPC (EPO FORM 1205A DATED 15/06/2016) |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 13888591 Country of ref document: EP Kind code of ref document: A1 |