CN106449667B - 阵列基板及其制作方法、显示装置 - Google Patents

阵列基板及其制作方法、显示装置 Download PDF

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CN106449667B
CN106449667B CN201611189759.4A CN201611189759A CN106449667B CN 106449667 B CN106449667 B CN 106449667B CN 201611189759 A CN201611189759 A CN 201611189759A CN 106449667 B CN106449667 B CN 106449667B
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film transistor
tft
thin film
layer
active layer
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CN106449667A (zh
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王谦
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chongqing BOE Optoelectronics Technology Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Abstract

本发明提供了一种阵列基板及其制作方法、显示装置，属于显示技术领域。其中，所述阵列基板包括显示区域和GOA区域，所述制作方法包括：利用金属氧化物半导体材料制作所述显示区域的第一薄膜晶体管的有源层；利用非金属氧化物的半导体材料制作所述GOA区域的第二薄膜晶体管的有源层。本发明的技术方案能够使得高分辨率显示装置应用GOA技术。

Description

阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，特别是指一种阵列基板及其制作方法、显示装置。
背景技术
目前，随着显示技术的发展，为了提升产品竞争力，显示产品的分辨率越来越高，显示产品的分辨率可以达到4K、甚至8K；同时，为了节省显示产品的成本，GOA(Gate Driveron Array)技术得到了广泛的应用，GOA技术即阵列基板行驱动技术，是利用薄膜晶体管(Thin Film Transistor)制程将栅极扫描驱动电路制作在薄膜晶体管阵列基板上，以实现逐行扫描的驱动方式，具有降低生产成本和实现面板窄边框设计的优点，为多种显示产品所使用。
由于显示产品的分辨率很高，显示产品像素的行数可以达到几千，导致每行像素的充电时间很短，在薄膜晶体管的有源层采用a-Si时，由于a-Si的迁移率比较低，所以很难保证显示产品的充电率满足要求；金属氧化物半导体的迁移率远远高于a-Si，可以轻松满足高分辨率显示产品的充电率要求，但是在采用金属氧化物半导体作为薄膜晶体管的有源层时，在长时间偏压作用下，薄膜晶体管的阈值电压Vth漂移严重，使得薄膜晶体管的特性发生变化，GOA单元将不能实现正常的扫描功能，综上所述，现有的高分辨显示产品无法应用GOA技术。
发明内容
本发明要解决的技术问题是提供一种阵列基板及其制作方法、显示装置，能够使得高分辨率显示装置应用GOA技术。
为解决上述技术问题，本发明的实施例提供技术方案如下：
一方面，提供一种阵列基板的制作方法，所述阵列基板包括显示区域和GOA区域，所述制作方法包括：
利用金属氧化物半导体材料制作所述显示区域的第一薄膜晶体管的有源层；
利用非金属氧化物的半导体材料制作所述GOA区域的第二薄膜晶体管的有源层。
进一步地，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
形成栅绝缘层；
在所述栅绝缘层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在所述栅绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
进一步地，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
形成栅绝缘层；
在所述栅绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在所述栅绝缘层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
进一步地，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层；
在所述缓冲层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在所述缓冲层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
形成栅绝缘层；
在所述栅绝缘层上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
进一步地，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层；
在所述缓冲层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在所述缓冲层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
形成栅绝缘层；
在所述栅绝缘层上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
进一步地，所述非金属氧化物的半导体材料采用多晶硅或非晶硅；
所述金属氧化物半导体材料采用IGZO、IZO、ZnON、CuO或SnO。
本发明实施例还提供了一种阵列基板，采用如上所述的制作方法制作得到，所述阵列基板包括显示区域和GOA区域，所述显示区域的第一薄膜晶体管的有源层采用金属氧化物半导体材料，所述GOA区域的第二薄膜晶体管的有源层采用非金属氧化物的半导体材料。
进一步地，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板上的所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
栅绝缘层；
位于所述栅绝缘层上的所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层；
所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
进一步地，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板上的缓冲层；
位于所述缓冲层上的所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层；
所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
栅绝缘层；
位于所述栅绝缘层上的所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
本发明实施例还提供了一种显示装置，包括如上所述的阵列基板。
本发明的实施例具有以下有益效果：
上述方案中，阵列基板的显示区域的薄膜晶体管的有源层和GOA区域的薄膜晶体管的有源层采用不同的材料制成，阵列基板的显示区域的薄膜晶体管的有源层采用金属氧化物半导体材料制成，这样当显示产品的分辨率很高时，由于金属氧化物半导体材料的迁移率比较高，也能够满足高分辨率显示产品的充电率要求；阵列基板的GOA区域的薄膜晶体管的有源层采用非金属氧化物的半导体材料制成，这样能够防止薄膜晶体管在长期偏压作用下Vth漂移，保证薄膜晶体管的特性不会发生变化，保证GOA单元正常的扫描功能。通过本发明的技术方案，能够使得高分辨率显示装置应用GOA技术。
附图说明
图1为本发明实施例阵列基板的结构示意图；
图2为本发明实施例在衬底基板上形成第一薄膜晶体管和第二薄膜晶体管的栅电极后的示意图；
图3为本发明实施例形成栅绝缘层后的示意图；
图4为本发明实施例先在衬底基板上形成第一薄膜晶体管的有源层的示意图；
图5为本发明实施例后在衬底基板上形成第二薄膜晶体管的有源层的示意图；
图6为本发明实施例先在衬底基板上形成第二薄膜晶体管的有源层的示意图。
附图标记
1 衬底基板 2 显示区域的薄膜晶体管的栅电极 3 栅绝缘层
4 显示区域的薄膜晶体管的有源层 5 显示区域的薄膜晶体管的漏电极
6 显示区域的薄膜晶体管的源电极 7 GOA区域的薄膜晶体管的栅电极
8 GOA区域的薄膜晶体管的有源层 9 GOA区域的薄膜晶体管的漏电极
10 GOA区域的薄膜晶体管的源电极
具体实施方式
为使本发明的实施例要解决的技术问题、技术方案和优点更加清楚，下面将结合附图及具体实施例进行详细描述。
本发明的实施例针对现有技术中高分辨显示产品无法应用GOA技术的问题，提供一种阵列基板及其制作方法、显示装置，能够使得高分辨率显示装置应用GOA技术。
实施例一
本实施例提供一种阵列基板的制作方法，所述阵列基板包括显示区域和GOA区域，所述制作方法包括：
利用金属氧化物半导体材料制作所述显示区域的第一薄膜晶体管的有源层；
利用非金属氧化物的半导体材料制作所述GOA区域的第二薄膜晶体管的有源层。
本实施例中，阵列基板的显示区域的薄膜晶体管的有源层和GOA区域的薄膜晶体管的有源层采用不同的材料制成，阵列基板的显示区域的薄膜晶体管的有源层采用金属氧化物半导体材料制成，这样当显示产品的分辨率很高时，由于金属氧化物半导体材料的迁移率比较高，也能够满足高分辨率显示产品的充电率要求；阵列基板的GOA区域的薄膜晶体管的有源层采用非金属氧化物的半导体材料制成，这样能够防止薄膜晶体管在长期偏压作用下Vth漂移，保证薄膜晶体管的特性不会发生变化，保证GOA单元正常的扫描功能。通过本发明的技术方案，能够使得高分辨率显示装置应用GOA技术。
具体实施例中，在制作底栅型的阵列基板中，可以先形成显示区域的薄膜晶体管的有源层，再形成GOA区域的薄膜晶体管的有源层。所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
形成栅绝缘层；
在所述栅绝缘层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在所述栅绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
具体实施例中，在制作底栅型的阵列基板中，可以先形成GOA区域的薄膜晶体管的有源层，再形成显示区域的薄膜晶体管的有源层。所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
形成栅绝缘层；
在所述栅绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在所述栅绝缘层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
具体实施例中，在制作顶栅型的阵列基板中，可以先形成GOA区域的薄膜晶体管的有源层，再形成显示区域的薄膜晶体管的有源层。所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层；
在所述缓冲层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在所述缓冲层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
形成栅绝缘层；
在所述栅绝缘层上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
具体实施例中，在制作顶栅型的阵列基板中，可以先形成显示区域的薄膜晶体管的有源层，再形成GOA区域的薄膜晶体管的有源层。所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层；
在所述缓冲层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在所述缓冲层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
形成栅绝缘层；
在所述栅绝缘层上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
进一步地，所述非金属氧化物的半导体材料具体可以采用多晶硅或非晶硅；所述金属氧化物半导体材料具体可以采用IGZO、IZO、ZnON、CuO或SnO。
实施例二
下面以制作底栅型的阵列基板为例，结合附图对本发明的阵列基板的制作方法进行进一步介绍：
本实施例的阵列基板的制作方法具体包括以下步骤：
步骤1、如图2所示，提供一衬底基板1，在衬底基板1上形成显示区域的薄膜晶体管的栅电极2、GOA区域的薄膜晶体管的栅电极7和栅线的图形；
其中，衬底基板可为玻璃基板或石英基板。具体地，可以采用溅射或热蒸发的方法在衬底基板1上沉积厚度约为的栅金属层，栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于栅线和栅电极的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成显示区域的薄膜晶体管的栅电极2、GOA区域的薄膜晶体管的栅电极7和栅线的图形。
步骤2、如图3所示，在完成步骤1的衬底基板1上形成栅绝缘层3；
具体地，可以采用等离子体增强化学气相沉积(PECVD)方法在完成步骤1的衬底基板1上沉积厚度为的栅绝缘层3，栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
步骤3、如图4所示，在栅绝缘层3上沉积金属氧化物的半导体层，对金属氧化物的半导体层进行构图形成显示区域的薄膜晶体管的有源层4；
具体地，在栅绝缘层3上沉积一层金属氧化物的半导体材料，金属氧化物半导体材料具体可以采用IGZO、IZO、ZnON、CuO或SnO。在金属氧化物的半导体材料上涂覆一层光刻胶，采用半色调或灰色调掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶完全保留区域，其中，光刻胶完全保留区域对应于显示区域的薄膜晶体管的有源层4所在区域，光刻胶未保留区域对应于显示区域的薄膜晶体管的有源层4的图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶完全保留区域的光刻胶厚度保持不变，通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的金属氧化物的半导体材料，形成显示区域的薄膜晶体管的有源层4的图形，剥离剩余的光刻胶。
步骤4、如图5所示，在栅绝缘层3上沉积非金属氧化物半导体层，对非金属氧化物半导体层进行构图形成GOA区域的薄膜晶体管的有源层8；
具体地，在栅绝缘层3上沉积一层非金属氧化物的半导体材料，非金属氧化物的半导体材料具体可以采用多晶硅或非晶硅。在非金属氧化物的半导体材料上涂覆一层光刻胶，采用半色调或灰色调掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶完全保留区域，其中，光刻胶完全保留区域对应于GOA区域的薄膜晶体管的有源层8所在区域，光刻胶未保留区域对应于GOA区域的薄膜晶体管的有源层8的图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶完全保留区域的光刻胶厚度保持不变，通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的非金属氧化物的半导体材料，形成GOA区域的薄膜晶体管的有源层8的图形，剥离剩余的光刻胶。
步骤5、如图1所示，在经过步骤4的衬底基板1上形成显示区域的薄膜晶体管的源电极5、漏电极6、GOA区域的薄膜晶体管的源电极9、漏电极10和数据线。
具体地，可以在完成步骤4的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的源漏金属层，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源电极、漏电极和数据线的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层，剥离剩余的光刻胶，形成显示区域的薄膜晶体管的源电极5、漏电极6、GOA区域的薄膜晶体管的源电极9、漏电极10和数据线。
经过上述步骤即可在衬底基板上制作完成显示区域的薄膜晶体管和GOA区域的薄膜晶体管，之后可以在形成有显示区域的薄膜晶体管和GOA区域的薄膜晶体管的衬底基板上形成钝化层和像素电极，即可制作得到阵列基板。
实施例三
下面以制作底栅型的阵列基板为例，结合附图对本发明的阵列基板的制作方法进行进一步介绍：
本实施例的阵列基板的制作方法具体包括以下步骤：
步骤1、如图2所示，提供一衬底基板1，在衬底基板1上形成显示区域的薄膜晶体管的栅电极2、GOA区域的薄膜晶体管的栅电极7和栅线的图形；
其中，衬底基板可为玻璃基板或石英基板。具体地，可以采用溅射或热蒸发的方法在衬底基板1上沉积厚度约为的栅金属层，栅金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金，栅金属层可以为单层结构或者多层结构，多层结构比如Cu\Mo,Ti\Cu\Ti，Mo\Al\Mo等。在栅金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于栅线和栅电极的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的栅金属薄膜，剥离剩余的光刻胶，形成显示区域的薄膜晶体管的栅电极2、GOA区域的薄膜晶体管的栅电极7和栅线的图形。
步骤2、如图3所示，在完成步骤1的衬底基板1上形成栅绝缘层3；
具体地，可以采用等离子体增强化学气相沉积(PECVD)方法在完成步骤1的衬底基板1上沉积厚度为的栅绝缘层3，栅绝缘层3可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体是SiH4、NH3、N2或SiH2Cl2、NH3、N2。
步骤3、如图6所示，在栅绝缘层3上沉积非金属氧化物半导体层，对非金属氧化物半导体层进行构图形成GOA区域的薄膜晶体管的有源层8；
具体地，在栅绝缘层3上沉积一层非金属氧化物的半导体材料，非金属氧化物的半导体材料具体可以采用多晶硅或非晶硅。在非金属氧化物的半导体材料上涂覆一层光刻胶，采用半色调或灰色调掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶完全保留区域，其中，光刻胶完全保留区域对应于GOA区域的薄膜晶体管的有源层8所在区域，光刻胶未保留区域对应于GOA区域的薄膜晶体管的有源层8的图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶完全保留区域的光刻胶厚度保持不变，通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的非金属氧化物的半导体材料，形成GOA区域的薄膜晶体管的有源层8的图形，剥离剩余的光刻胶。
步骤4、如图5所示，在栅绝缘层3上沉积金属氧化物的半导体层，对金属氧化物的半导体层进行构图形成显示区域的薄膜晶体管的有源层4；
具体地，在栅绝缘层3上沉积一层金属氧化物的半导体材料，金属氧化物半导体材料具体可以采用IGZO、IZO、ZnON、CuO或SnO。在金属氧化物的半导体材料上涂覆一层光刻胶，采用半色调或灰色调掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶完全保留区域，其中，光刻胶完全保留区域对应于显示区域的薄膜晶体管的有源层4所在区域，光刻胶未保留区域对应于显示区域的薄膜晶体管的有源层4的图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶完全保留区域的光刻胶厚度保持不变，通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的金属氧化物的半导体材料，形成显示区域的薄膜晶体管的有源层4的图形，剥离剩余的光刻胶。
步骤5、如图1所示，在经过步骤4的衬底基板1上形成显示区域的薄膜晶体管的源电极5、漏电极6、GOA区域的薄膜晶体管的源电极9、漏电极10和数据线。
具体地，可以在完成步骤4的衬底基板1上采用磁控溅射、热蒸发或其它成膜方法沉积一层厚度约为的源漏金属层，源漏金属层可以是Cu，Al，Ag，Mo，Cr，Nd，Ni，Mn，Ti，Ta，W等金属以及这些金属的合金。源漏金属层可以是单层结构或者多层结构，多层结构比如Cu\Mo，Ti\Cu\Ti，Mo\Al\Mo等。在源漏金属层上涂覆一层光刻胶，采用掩膜板对光刻胶进行曝光，使光刻胶形成光刻胶未保留区域和光刻胶保留区域，其中，光刻胶保留区域对应于源电极、漏电极和数据线的图形所在区域，光刻胶未保留区域对应于上述图形以外的区域；进行显影处理，光刻胶未保留区域的光刻胶被完全去除，光刻胶保留区域的光刻胶厚度保持不变；通过刻蚀工艺完全刻蚀掉光刻胶未保留区域的源漏金属层，剥离剩余的光刻胶，形成显示区域的薄膜晶体管的源电极5、漏电极6、GOA区域的薄膜晶体管的源电极9、漏电极10和数据线。
经过上述步骤即可在衬底基板上制作完成显示区域的薄膜晶体管和GOA区域的薄膜晶体管，之后可以在形成有显示区域的薄膜晶体管和GOA区域的薄膜晶体管的衬底基板上形成钝化层和像素电极，即可制作得到阵列基板。
实施例四
本实施例提供了一种阵列基板，采用如上所述的制作方法制作得到，所述阵列基板包括显示区域和GOA区域，所述显示区域的第一薄膜晶体管的有源层采用金属氧化物半导体材料，所述GOA区域的第二薄膜晶体管的有源层采用非金属氧化物的半导体材料。
本实施例中，阵列基板的显示区域的薄膜晶体管的有源层和GOA区域的薄膜晶体管的有源层采用不同的材料制成，阵列基板的显示区域的薄膜晶体管的有源层采用金属氧化物半导体材料制成，这样当显示产品的分辨率很高时，由于金属氧化物半导体材料的迁移率比较高，也能够满足高分辨率显示产品的充电率要求；阵列基板的GOA区域的薄膜晶体管的有源层采用非金属氧化物的半导体材料制成，这样能够防止薄膜晶体管在长期偏压作用下Vth漂移，保证薄膜晶体管的特性不会发生变化，保证GOA单元正常的扫描功能。通过本发明的技术方案，能够使得高分辨率显示装置应用GOA技术。
进一步地，在阵列基板为底栅型的阵列基板时，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板上的所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
栅绝缘层；
位于所述栅绝缘层上的所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层；
所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
进一步地，在阵列基板为顶栅型的阵列基板时，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板上的缓冲层；
位于所述缓冲层上的所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层；
所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
栅绝缘层；
位于所述栅绝缘层上的所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
实施例五
本实施例提供了一种显示装置，包括如上所述的阵列基板。所述显示装置可以为：液晶电视、液晶显示器、数码相框、手机、平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性电路板、印刷电路板和背板。
本实施例中，显示装置的显示区域的薄膜晶体管的有源层和GOA区域的薄膜晶体管的有源层采用不同的材料制成，阵列基板的显示区域的薄膜晶体管的有源层采用金属氧化物半导体材料制成，这样当显示产品的分辨率很高时，由于金属氧化物半导体材料的迁移率比较高，也能够满足高分辨率显示产品的充电率要求；阵列基板的GOA区域的薄膜晶体管的有源层采用非金属氧化物的半导体材料制成，这样能够防止薄膜晶体管在长期偏压作用下Vth漂移，保证薄膜晶体管的特性不会发生变化，保证GOA单元正常的扫描功能。通过本发明的技术方案，能够使得高分辨率显示装置应用GOA技术。
以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (10)

1.一种阵列基板的制作方法，所述阵列基板包括显示区域和GOA区域，其特征在于，所述制作方法包括：
利用金属氧化物半导体材料制作所述显示区域的第一薄膜晶体管的有源层；
利用非金属氧化物的半导体材料制作所述GOA区域的第二薄膜晶体管的有源层。
2.根据权利要求1所述的阵列基板的制作方法，其特征在于，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
形成栅绝缘层；
在所述栅绝缘层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在所述栅绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
3.根据权利要求1所述的阵列基板的制作方法，其特征在于，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
形成栅绝缘层；
在所述栅绝缘层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在所述栅绝缘层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
4.根据权利要求1所述的阵列基板的制作方法，其特征在于，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层；
在所述缓冲层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在所述缓冲层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
形成栅绝缘层；
在所述栅绝缘层上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
5.根据权利要求1所述的阵列基板的制作方法，其特征在于，所述阵列基板的制作方法具体包括：
提供一衬底基板；
在所述衬底基板上沉积缓冲层；
在所述缓冲层上沉积金属氧化物半导体层，对所述金属氧化物半导体层进行构图形成所述第一薄膜晶体管的有源层；
在所述缓冲层上沉积非金属氧化物的半导体层，对所述非金属氧化物的半导体层进行构图形成所述第二薄膜晶体管的有源层；
在形成有所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层的衬底基板上沉积源漏金属层，对所述源漏金属层进行构图形成所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
形成栅绝缘层；
在所述栅绝缘层上沉积栅金属层，对所述栅金属层进行构图形成所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
6.根据权利要求1-5中任一项所述的阵列基板的制作方法，其特征在于，所述非金属氧化物的半导体材料采用多晶硅或非晶硅；
所述金属氧化物半导体材料采用IGZO、IZO、ZnON、CuO或SnO。
7.一种阵列基板，其特征在于，采用如权利要求1-6中任一项所述的制作方法制作得到，所述阵列基板包括显示区域和GOA区域，所述显示区域的第一薄膜晶体管的有源层采用金属氧化物半导体材料，所述GOA区域的第二薄膜晶体管的有源层采用非金属氧化物的半导体材料。
8.根据权利要求7所述的阵列基板，其特征在于，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板上的所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极；
栅绝缘层；
位于所述栅绝缘层上的所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层；
所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极。
9.根据权利要求7所述的阵列基板，其特征在于，所述阵列基板具体包括：
衬底基板；
位于所述衬底基板上的缓冲层；
位于所述缓冲层上的所述第一薄膜晶体管的有源层和所述第二薄膜晶体管的有源层；
所述第一薄膜晶体管的源电极、漏电极和所述第二薄膜晶体管的源电极、漏电极；
栅绝缘层；
位于所述栅绝缘层上的所述第一薄膜晶体管的栅电极和所述第二薄膜晶体管的栅电极。
10.一种显示装置，其特征在于，包括如权利要求7-9中任一项所述的阵列基板。
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