CN103018990A - 一种阵列基板和其制备方法、及液晶显示装置 - Google Patents
一种阵列基板和其制备方法、及液晶显示装置 Download PDFInfo
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Abstract
本发明实施例提供一种阵列基板和其制备方法、及液晶显示装置,阵列基板包括:栅绝缘层;金属氧化物半导体形成的阻挡层图案和有源半导体层图案位于栅绝缘层之上;半导体保护层覆盖所述阻挡层图案、有源半导体层图案和栅绝缘层,且在阻挡层图案和有源半导体层图案上的相应位置处形成有过孔;在各个过孔处设置有金属Cu制作而成的数据线、源电极和漏电极。采用金属Cu制作数据线、源电极和漏电极,采用金属氧化物半导体作为金属Cu的阻挡层,在形成薄膜晶体管的过程中防止了金属Cu向栅绝缘层等层中进行扩散。
Description
技术领域
本发明涉及液晶显示技术,特别是指一种阵列基板和其制备方法、及液晶显示装置。
背景技术
薄膜晶体管液晶显示器(TFT-LCD,Thin Film Transistor Liquid CrystalDisplay)具有体积小、功耗低、无辐射等特点。随着TFT-LCD尺寸的不断增大、分辨率的不断提高,采用了更高频率的驱动电路以提高显示质量,导致大尺寸、高分辨率TFT-LCD的图像信号的延迟更为严重。TFT-LCD信号的延迟主要由T=RC决定,R为信号电阻,C为相关电容。现在一般采用化学性质稳定、电阻率较高的Ta、Cr、Mo等金属或是其合金作为金属电极的材料制作TFT-LCD的栅极、栅极扫描线和数据线。随着TFT-LCD尺寸和分辨率地提高,栅极扫描线长度也随着增大,信号延迟时间也随之增大,信号延迟增加到一定的程度,一些像素得不到充分的充电,造成亮度不均匀,使TFT-LCD的对比度下降,严重地影响了图像的显示质量。
随着液晶显示器尺寸地增大,需要不断提高驱动电路的频率。非晶硅薄膜晶体管的迁移率在0.5左右,但液晶显示器超过80英寸,驱动频率为120Hz时需要1cm2/V.S以上的迁移率。
金属氧化物TFT(非晶IGZO)迁移率高、均一性好、透明且制作工艺简单,能够满足大尺寸液晶显示器和有源有机电致发光的需求,以及满足大尺寸,高刷新频率LCD及OLED高迁移率的需求。若采用金属Cu制作薄膜晶体管的漏源电极,金属Cu扩散到半导体层、栅绝缘层和钝化层中会严重影响TFT的性能,因此在沉积金属Cu薄膜之前需要先沉积阻挡层。
现有技术存在如下问题:采用非晶IGZO制作TFT时,一般在非晶IGZO(半导体层)上面设置阻挡层,避免在形成金属Cu的源漏电极时破坏非晶IGZO,但这会增加一次构图工艺,并且在湿法刻蚀金属Cu时,由于金属Cu的刻蚀速率与阻挡层的刻蚀速率相差很大,刻蚀后阻挡层会残留一部分,在其上再沉积其他的薄膜会出现覆盖性差。
发明内容
本发明要解决的技术问题是提供一种阵列基板和其制备方法,以及液晶显示装置,解决现有技术中,采用金属Cu制作薄膜晶体管的漏源电极,金属Cu会扩散到半导体层、栅绝缘层和钝化层中影响TFT的性能的缺陷。
为解决上述技术问题,本发明的实施例提供一种阵列基板,包括:栅绝缘层;金属氧化物半导体形成的阻挡层图案和有源半导体层图案位于栅绝缘层之上;半导体保护层覆盖所述阻挡层图案、有源半导体层图案和栅绝缘层,且在阻挡层图案和有源半导体层图案上的相应位置处形成有过孔;在各个过孔处设置有金属Cu制作而成的数据线、源电极和漏电极。
所述的阵列基板中,所述半导体保护层覆盖所述阻挡层图案、有源半导体层图案和栅绝缘层包括:半导体保护层在非过孔位置处则形成于栅绝缘层上。
所述的阵列基板中,所述栅绝缘层包括两层:第一层为氮化硅,第二层为氧化硅,第二层直接与有源半导体层图案或者半导体保护层接触。
所述的阵列基板中,所述半导体保护层覆盖阻挡层图案、有源半导体层图案和栅绝缘层,且在阻挡层图案和有源半导体层图案上的相应位置处形成有过孔包括:第一过孔是数据线与源电极连接过孔;第二过孔是源电极过孔;第三过孔是漏电极过孔。
所述的阵列基板中,采用透明导电材料形成数据线与源电极连接线,所述数据线与源电极连接线在第一过孔处连接了数据线和源电极。
所述的阵列基板中,采用透明导电材料在第二过孔处形成薄膜,覆盖第二过孔处的源电极。
所述的阵列基板中,采用透明导电材料在第三过孔处形成薄膜,覆盖第三过孔处的漏电极。
所述的阵列基板中,所述半导体保护层包括两层:第一层为氮化硅,第二层为氧化物;所述氧化物是金属氧化物,或者硅的氧化物;第一层直接与有源半导体层图案接触。
一种阵列基板的制备方法,包括:通过一次构图工艺形成栅极和栅极扫描线;通过一次构图工艺形成金属氧化物半导体的阻挡层图案和有源半导体层图案;通过一次构图工艺形成半导体保护层的过孔;通过一次构图工艺形成金属Cu的数据线、源电极和漏电极的图案;通过一次构图工艺形成数据线与源电极连接线,以及透明像素电极。
所述的阵列基板的制备方法中,通过一次构图工艺形成半导体保护层的过孔,包括:所述过孔形成在阻挡层图案层和有源半导体层图案上的相应位置处。
所述的阵列基板的制备方法中,所述过孔包括:第一过孔是数据线与源电极连接过孔;第二过孔是源电极过孔;第三过孔是漏电极过孔。
所述的阵列基板的制备方法中,通过一次构图工艺形成数据线与源电极连接线,以及透明像素电极包括:采用透明导电材料形成数据线与源电极连接线,所述数据线与源电极连接线在第一过孔处连接了数据线和源电极。
一种液晶显示装置,包括上述的阵列基板。
本发明的上述技术方案的有益效果如下:采用金属Cu制作数据线、源电极和漏电极,采用金属氧化物半导体作为金属Cu的阻挡层,在形成薄膜晶体管的过程中防止了金属Cu向栅绝缘层等层中进行扩散。
附图说明
图1表示一种TFT结构的结构示意图;
图2表示通过一次构图工艺形成栅极和栅极扫描线的截面图;
图3表示通过一次构图工艺形成栅极和栅极扫描线的平面图;
图4表示通过一次构图工艺形成有源半导体层图案的截面图;
图5表示通过一次构图工艺形成有源半导体层图案的平面图;
图6表示通过一次构图工艺形成半导体保护层的截面图;
图7表示通过一次构图工艺形成半导体保护层的平面图;
图8表示通过一次构图工艺形成数据线、源电极和漏电极的截面图;
图9表示通过一次构图工艺形成数据线、源电极和漏电极的平面图;
图10表示通过一次构图工艺形成透明像素电极,数据线与源电极连接线的截面图;
图11表示通过一次构图工艺形成透明像素电极,数据线与源电极连接线的平面图;
图12表示数据线与源电极连接线部分覆盖数据线的示意图;
1 玻璃基板
2 栅极
3 栅绝缘层
4 有源半导体层图案
5 半导体保护层
6 源电极
7 漏电极
8 透明像素电极
9 数据线与源电极连接线
10 数据线与源电极连接过孔
11 阻挡层图案
12 数据线
13 栅极扫描线。
具体实施方式
为使本发明要解决的技术问题、技术方案和优点更加清楚,下面将结合附图及具体实施例进行详细描述。
本发明采用了低电阻的金属Cu制作源电极6和漏电极7、栅极扫描线13和数据线12,以改善阵列基板中的金属Cu布线的情形。
本发明实施例提供一种阵列基板,如图1和图10所示,包括:
栅绝缘层3;
金属氧化物半导体制备的Cu的阻挡层图案11和有源半导体层图案4位于栅绝缘层3之上;
半导体保护层5覆盖Cu的阻挡层图案11和有源半导体层图案4层和栅绝缘层3,且在阻挡层图案层11和有源半导体层图案层4上的相应位置处形成有过孔;
在各个过孔处设置有金属Cu制作而成的数据线12、源电极6和漏电极7。
应用所提供的技术,采用金属Cu制作数据线12、源电极6和漏电极7,采用金属氧化物半导体作为金属Cu的阻挡层,在形成薄膜晶体管的过程中防止了金属Cu向栅绝缘层3等层中进行扩散。
在一个优选实施例中,半导体保护层5覆盖阻挡层图案11、有源半导体层图案4和栅绝缘层3包括:所述半导体保护层5在非过孔位置处则形成于栅绝缘层上3。
在一个优选实施例中,栅绝缘层3包括两层:第一层为氮化硅(SiNx),第二层为氧化硅(SiOx),第二层直接与有源半导体层图案4或者半导体保护层5接触。
在一个优选实施例中,半导体保护层5覆盖阻挡层图案11、有源半导体层图案4和栅绝缘层3,且在阻挡层图案11和有源半导体层图案4上的相应位置处形成有过孔包括:
第一过孔是数据线与源电极连接过孔10;
第二过孔是源电极过孔;
第三过孔是漏电极过孔。
每一个过孔位置处均作为了金属Cu与金属氧化物半导体的接触区域。
在一个优选实施例中,采用透明导电材料形成数据线与源电极连接线9,所述数据线与源电极连接线9在第一过孔处连接了数据线12和源电极6。
如图11所示,透明导电材料覆盖全部的数据线12,或者,如图12所示,部分覆盖数据线12。透明导电材料具体是氧化铟锡(ITO)或者铟锌氧化物(IZO)。
在一个优选实施例中,采用透明导电材料在第二过孔处形成薄膜,覆盖第二过孔处的源电极6。透明导电材料具体是ITO或者IZO。
在一个优选实施例中,采用透明导电材料在第三过孔处形成薄膜,覆盖第三过孔处的漏电极7。透明导电材料具体是ITO或者IZO。
在一个优选实施例中,半导体保护层5包括两层:
第一层为氮化硅,第二层为氧化物;氧化物是金属氧化物,或者硅的氧化物;第一层直接与有源半导体层图案4接触。
半导体保护层5包括两层,第一层为氮化硅,第二层为氧化物,氧化物可以使金属氧化物的绝缘体如Al2O3,也可以是硅的氧化物,如氧化硅或者氮氧化硅,半导体保护层5的作用在于刻蚀源电极6和漏电极7的过程中,防止有源半导体层图案4被刻蚀掉。
应用实施例提供的技术,在制作阵列基板的场景中,采用金属氧化物半导体制作金属Cu的阻挡层图案11和有源半导体层图案4,以及采用金属Cu制作数据线12、栅极扫描线13、源电极6和漏电极7,具体包括如下步骤:
步骤1,在玻璃基板1或者石英基板上,采用溅射或热蒸发方式沉积厚度的栅金属膜,栅金属膜选用Cr、W、Cu、Ti、Ta、Mo等金属或合金,或者选用由多层金属组成的复合栅金属。
第一次构图工艺形成:栅极2和栅极扫描线13,图2、图3所示分别是这一次构图工艺后的阵列基板的截面图和平面图。
为提高TFT的性能,栅绝缘层3包括两层:第一层为SiNx,第二层为SiOx,第二层直接与有源半导体图案层4和半导体保护层5接触。
步骤3,在栅绝缘层3之上通过溅射方法连续沉积厚度为的半导体层4,具体采用非晶IGZO、HIZO、IZO、a-InZnO、a-InZnO、ZnO:F、In2O3:Sn、In2O3:Mo、Cd2SnO4、ZnO:Al、TiO2:Nb、Cd-Sn-O或者其他金属氧化物;
第二次构图工艺形成:阻挡层图案11和有源半导体层图案4,如图4、图5所示分别是这一次构图工艺后的阵列基板的截面图和平面图。
阻挡层图案11,起到了阻挡层的功能,增加了相关电极的金属Cu薄膜的附着力,并且又能够阻止金属Cu离子扩散到栅绝缘层3等相关层中。
步骤4,在阵列基板上以PECVD方法沉积厚度的半导体保护层5,半导体保护层5可以使用Al2O3或者双层的阻挡结构,双层的阻挡结构中,第一层为氮化硅,第二层为氧化物,氧化物可以是金属氧化物的绝缘体如Al2O3,也可以是硅的氧化物,如氧化硅或者氮氧化硅。
半导体保护层5选用氧化物、氮化物或者氧氮化合物;硅的氧化物对应的反应气体可以为SiH4,N2O,氮化物或者氧氮化合物对应气体是SiH4,NH3,N2或SiH2Cl2,NH3,N2。
第三次构图工艺形成:第一过孔、第二过孔和第三过孔。
第一过孔是数据线与源电极连接过孔10;
第二过孔是源电极过孔;
第三过孔是漏电极过孔。
截面图和平面图分别如图6、图7所示,每一个过孔处,均是金属Cu与金属氧化物半导体的接触区域。
步骤5,在阵列基板上通过溅射或热蒸发的方法沉积上厚度 源漏金属层,具体采用了金属Cu。
第四次构图工艺形成:数据线12、源电极6和漏电极7的图案,其截面图和平面图分别如图8、图9所示。
第五次构图工艺形成:透明像素电极8,数据线与源电极连接线9,其截面图如图10所示,透明像素电极8采用的ITO或者IZO可以覆盖整个漏电极7,以减少漏电极7与透明像素电极8之间的接触不良,保证了漏电极7和透明像素电极8充分接触,还可以保护形成漏电极7的金属Cu薄膜;透明像素电极8采用的ITO或者IZO也可以部分覆盖整个漏电极7。
如图11所示,数据线与源电极连接线9采用透明导电材料(具体是ITO或者IZO)形成,并且覆盖全部的数据线12,或者如图12所示,数据线与源电极连接线9也可以部分覆盖数据线12。
本发明实施例提供一种制作阵列基板的方法,使用金属Cu制作数据线12、源电极6和漏电极7,采用金属氧化物半导体制备Cu的阻挡层图案11,方法包括:
通过一次构图工艺形成栅极6和栅极扫描线13;
通过一次构图工艺形成金属氧化物半导体的阻挡层图案11和有源半导体层图案4;
通过一次构图工艺形成半导体保护层5的过孔;
通过一次构图工艺形成金属Cu的数据线12、源电极6和漏电极7的图案;
通过一次构图工艺形成数据线与源电极连接线9,以及透明像素电极8。
应用实施例提供的技术,在制作阵列基板的场景中,方法的步骤包括:
在第一次构图工艺中形成栅电极6和栅极扫描线13;
在第二次构图工艺中形成Cu的阻挡层图案11和有源半导体层图案4;
在第三次构图工艺中形成半导体保护层5的过孔,且过孔形成在阻挡层图案11和有源半导体层图案4上的相应位置处;在半导体保护层5中形成Cu与阻挡层图案11和有源半导体层图案4的金属氧化物半导体的接触区域,包括第一过孔-数据线的接触区、第二过孔-源电极接触区和第三过孔-漏电极接触区,半导体保护层5此时成为了有源半导体层图案4的保护层,提高金属氧化物TFT的稳定性;
在第四次构图工艺中,形成金属Cu的数据线12、源电极6和漏电极7的图案;
在第五次构图工艺中,形成数据线与源电极连接线9和透明像素电极8。采用透明导电材料形成数据线与源电极连接线9,数据线与源电极连接线9在第一过孔处连接了数据线12和源电极6。透明导电材料(具体是ITO或者IZO)可以全部覆盖金属Cu薄膜,这样保证了漏电极7和透明像素电极8充分接触,还可以保护金属Cu薄膜;透明导电材料也可以全部覆盖金属Cu薄膜,例如数据线与源电极连接线9也可以部分覆盖金属Cu薄膜。
构图工艺包括涂覆光刻胶、曝光、显影、刻蚀、剥离等工艺流程,构图工艺最终在薄膜上形成图形。
在构图工艺过程中,由于采用了金属氧化物半导体制作的阻挡层图案11作为金属Cu的阻挡层,在形成薄膜晶体管的过程中防止了金属Cu向栅绝缘层3等层中进行扩散,并且,采用了半导体保护层5保护有源半导体层图案4,半导体保护层5的作用在于刻蚀源电极6和漏电极7的过程中,防止有源半导体层图案4被刻蚀掉。
本发明实施例提供一种液晶显示装置,包括阵列基板,阵列基板包括:
栅绝缘层3;
金属氧化物半导体制备的Cu的阻挡层图案11和有源半导体层图案4位于栅绝缘层3之上;
半导体保护层5覆盖Cu的阻挡层图案11和有源半导体层图案4层和栅绝缘层3,且在阻挡层图案层11和有源半导体层图案层4上的相应位置处形成有过孔;
在各个过孔处设置有金属Cu制作而成的数据线12、源电极6和漏电极7。
采用本方案之后的优势是:采用金属Cu制作数据线12、源电极6和漏电极7,采用金属氧化物半导体作为金属Cu的阻挡层图案11,在形成薄膜晶体管的过程中防止了金属Cu向栅绝缘层3、有源半导体层图案4等层中进行扩散;由于金属氧化物TFT(非晶IGZO)迁移率高、均一性好、透明且制作工艺简单,能够满足大尺寸液晶显示器和有源有机电致发光的需求,以及满足大尺寸高刷新频率LCD及OLED对高迁移率的需求。
以上所述是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。
Claims (13)
1.一种阵列基板,其特征在于,包括:
栅绝缘层;
金属氧化物半导体形成的阻挡层图案和有源半导体层图案位于栅绝缘层之上;
半导体保护层覆盖所述阻挡层图案、有源半导体层图案和栅绝缘层,且在阻挡层图案和有源半导体层图案上的相应位置处形成有过孔;
在各个过孔处设置有金属Cu制作而成的数据线、源电极和漏电极。
2.根据权利要求1所述的阵列基板,其特征在于,所述半导体保护层覆盖所述阻挡层图案、有源半导体层图案和栅绝缘层包括:
所述半导体保护层在非过孔位置处则形成于栅绝缘层上。
3.根据权利要求1所述的阵列基板,其特征在于,所述栅绝缘层包括两层:第一层为氮化硅,第二层为氧化硅,第二层直接与有源半导体层图案或者半导体保护层接触。
4.根据权利要求1所述的阵列基板,其特征在于,所述半导体保护层覆盖阻挡层图案、有源半导体层图案和栅绝缘层,且在阻挡层图案和有源半导体层图案上的相应位置处形成有过孔包括:
第一过孔是数据线与源电极连接过孔;
第二过孔是源电极过孔;
第三过孔是漏电极过孔。
5.根据权利要求4所述的阵列基板,其特征在于,采用透明导电材料形成数据线与源电极连接线,所述数据线与源电极连接线在第一过孔处连接了数据线和源电极。
6.根据权利要求1所述的阵列基板,其特征在于,
采用透明导电材料在第二过孔处形成薄膜,覆盖第二过孔处的源电极。
7.根据权利要求1所述的阵列基板,其特征在于,
采用透明导电材料在第三过孔处形成薄膜,覆盖第三过孔处的漏电极。
8.根据权利要求1所述的阵列基板,其特征在于,
所述半导体保护层包括两层:
第一层为氮化硅,第二层为氧化物;所述氧化物是金属氧化物,或者硅的氧化物;
第一层直接与有源半导体层图案接触。
9.一种阵列基板的制备方法,其特征在于,
通过一次构图工艺形成栅极和栅极扫描线;
通过一次构图工艺形成金属氧化物半导体的阻挡层图案和有源半导体层图案;
通过一次构图工艺形成半导体保护层的过孔;
通过一次构图工艺形成金属Cu的数据线、源电极和漏电极的图案;
通过一次构图工艺形成数据线与源电极连接线,以及透明像素电极。
10.如权利要求9所述的阵列基板的制备方法,其特征在于,通过一次构图工艺形成半导体保护层的过孔,包括:
所述过孔形成在阻挡层图案层和有源半导体层图案上的相应位置处。
11.如权利要求10所述的阵列基板的制备方法,其特征在于,所述过孔包括:
第一过孔是数据线与源电极连接过孔;
第二过孔是源电极过孔;
第三过孔是漏电极过孔。
12.如权利要求9所述的阵列基板的制备方法,其特征在于,通过一次构图工艺形成数据线与源电极连接线,以及透明像素电极包括:
采用透明导电材料形成数据线与源电极连接线,所述数据线与源电极连接线在第一过孔处连接了数据线和源电极。
13.一种液晶显示装置,其特征在于,包括权利要求1~8所述的阵列基板。
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CN105931985A (zh) * | 2016-05-13 | 2016-09-07 | 京东方科技集团股份有限公司 | 阵列基板及其制作方法、显示装置 |
CN105932024A (zh) * | 2016-05-05 | 2016-09-07 | 京东方科技集团股份有限公司 | 阵列基板及其制造方法和显示装置 |
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US9632382B2 (en) | 2017-04-25 |
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EP2743984A2 (en) | 2014-06-18 |
US20140168556A1 (en) | 2014-06-19 |
EP2743984B1 (en) | 2020-05-06 |
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