CN103745954B - 显示装置、阵列基板及其制造方法 - Google Patents

显示装置、阵列基板及其制造方法 Download PDF

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CN103745954B
CN103745954B CN201410003682.1A CN201410003682A CN103745954B CN 103745954 B CN103745954 B CN 103745954B CN 201410003682 A CN201410003682 A CN 201410003682A CN 103745954 B CN103745954 B CN 103745954B
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layer
thin film
gate insulating
insulating layer
film transistor
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CN103745954A (zh
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袁广才
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to US14/422,321 priority patent/US9812541B2/en
Priority to PCT/CN2014/074032 priority patent/WO2015100859A1/zh
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Abstract

本发明涉及显示技术领域，尤其涉及一种显示装置、阵列基板及其制作方法。该阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管和像素电极，具体包括如下步骤：在基板上形成缓冲层的步骤；在完成上述步骤的基板上，沉积有源层薄膜、源漏金属薄膜和透明电极层，通过一次构图工艺形成所述第一薄膜晶体管中有源层和源漏电极的以及像素电极的图形。本发明提供一种显示装置、阵列基板及其制作方法，通过对阵列基板制作工艺流程的调整，可大大缩短薄膜晶体管的制作周期，同时由于经历比较少的工艺步骤，可以很好的提高薄膜晶体管的特性，使得薄膜晶体管的阈值电压不会发生较大的漂移，同时可提高产品的良率，而且使器件的稳定和可靠性更加适合于长时间的使用。

Description

显示装置、阵列基板及其制造方法
技术领域
本发明涉及显示技术领域，尤其涉及一种显示装置、阵列基板及其制作方法。
背景技术
近年来，显示技术得到快速的发展，如薄膜晶体管技术由原来的a-Si（非晶硅）薄膜晶体管发展到现在的LTPS（低温多晶硅）薄膜晶体管、MILC（金属诱导横向晶化）薄膜晶体管、Oxide（氧化物）薄膜晶体管等。而发光技术也由原来的LCD（液晶显示器）、PDP（等离子显示屏）发展为现在的OLED（有机发光二极管）、AMOLED（主动式矩阵有机发光二极管）等。有机发光显示器是新一代的显示器件，与液晶显示器相比，具有很多优点，如：自发光，响应速度快，宽视角等等，可以用于柔性显示，透明显示，3D（三维立体）显示等。但无论液晶显示还是有机发光显示，都需要为每一个像素配备用于控制该像素的开关—薄膜晶体管，通过驱动电路，可以独立控制每一个像素，而不会对其他像素造成串扰等影响。
目前广泛应用的Oxide薄膜晶体管采用氧化物半导体作为有源层，具有迁移率大、开态电流高、开关特性更优、均匀性更好的特点，可以适用于需要快速响应和较大电流的应用，如高频、高分辨率、大尺寸的显示器以及有机发光显示器等。
现有技术中Oxide薄膜晶体管制作过程通常需要6次mask（曝光），分别用于形成栅线及栅极，栅极绝缘层、有源层，刻蚀阻挡层，源漏极，钝化层及过孔。研究表明，通过六次mask曝光工艺导致器件性能不稳定、制作周期较长，并且导致制作成本相应增加。
发明内容
（一）要解决的技术问题
本发明要解决的技术问题是：提供一种能够有效降低成本、简化工艺、提高薄膜晶体管的稳定性显示装置、阵列基板及其制作方法。
（二）技术方案
为解决上述问题，本发明公开了如下的技术方案：
本发明一方面提供一种所述阵列基板包括第一薄膜晶体管和像素电极，其特征在于，包括如下步骤：
在基板上形成缓冲层的步骤；在完成上述步骤的基板上，沉积半导体材料、源漏金属材料和透明电极层，通过一次构图工艺形成所述第一薄膜晶体管中有源层和源漏电极的以及像素电极的图形。
优选地，所述阵列基板还包括第二薄膜晶体管，在所述缓冲层上所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极以及像素电极的图形通过一次构图工艺形成。
优选地，在形成有源层和源漏电极以及像素电极的图形之后还包括：
在基板上形成栅绝缘层的图形，形成过孔；
在栅绝缘层上形成第一薄膜晶体管和第二薄膜晶体管的栅极以及栅线的图形。
优选地，在在栅极及栅线上形成栅极保护层。
优选地，所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极层以及像素电极层通过一次构图工艺形成具体包括：
沉积半导体薄膜、源漏金属薄膜和透明电极薄膜；
涂覆光刻胶；
采用双色调掩膜工艺进行曝光显影，其中，第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域、数据线和电源线区域、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域、以及像素电极区域为光刻胶完全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域为光刻胶部分保留区域；
形成上述区域之外区域为光刻胶完全去除区域；
通过第一次刻蚀工艺，去除光刻胶完全去除区域对应的透明电极薄膜、源漏金属层以及有源层薄膜，
通过灰化工艺除去所述部分保留区域对应的光刻胶，形成第一沟道区域和第二沟道区域；
通过第二次刻蚀工艺，去除光刻胶部分保留区域对应的像素电极层和源漏金属层；
剥离剩余光刻胶层，形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域的图案、数据线和电源线区域的图案、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域的图案以及像素电极的图案。
优选地，在栅绝缘层上形成第一薄膜晶体管和第二薄膜晶体管的栅极以及栅线的图形具体包括：
沉积栅金属层，通过构图工艺形成第一薄膜晶体管和第二薄膜晶体管的栅极以及栅线，刻除位于像素电极区域上方的栅极。
优选地，所述栅绝缘层经过退火工艺处理。
优选地，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
优选地，所述有源层包括本征半导体层和/或掺杂半导体层，其中，本征半导体层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnON材料中的一种或多种，掺杂半导体层采用非晶硅、多晶硅、微晶硅材料中的一种或多种。
优选地，有源层采用氧化物半导体材料时，对氧化物半导体进行不同气氛的等离子体处理。
优选地，有源层采用氧化物半导体材料时，在氮气、氧气或空气条件下，对氧化物半导体层进行退火处理，所述退火温度为200～500℃，退火环境为空气、氧气或氮气。
再一方面，本发明还提供一种上述的制造方法制备的阵列基板，包括基板，所述基板上设有缓冲层、有源层、源漏电极、像素电极、栅绝缘层、栅极层；所述源漏电极和像素电极直接接触。
优选地，所述栅极层包括第一薄膜晶体管的第一栅极和第二薄膜晶体管的第二栅极；
所述有源层包括第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二有源层；
所述源漏电极层包括第一薄膜晶体管的第一源极、第一漏极以及第二薄膜晶体管的第二源极、第二漏极。
优选地，所述栅绝缘层经过退火工艺处理。
优选地，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者，
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者，
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
优选地，所述有源层包括本征半导体层和/或掺杂半导体层，其中，本征半导体层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnON材料中的一种或多种，掺杂半导体层采用非晶硅、多晶硅、微 晶硅材料中的一种或多种。
再一方面，本发明还提供一种显示装置，包括上述的阵列基板。(三)有益效果
本发明提供一种显示装置、阵列基板及其制作方法，通过对阵列基板制作工艺流程的调整，可大大缩短薄膜晶体管的制作周期，同时由于经历比较少的工艺步骤，可以很好的提高薄膜晶体管的特性，使得薄膜晶体管的阈值电压不会发生较大的漂移，同时可提高产品的良率，而且使器件的稳定和可靠性更加适合于长时间的使用。
附图说明
图1本发明实施例阵列基板制作方法流程图；
图2～10为本发明实施例沿图11中B-B和A-A剖视的阵列基板制作方法分解图；
图11为本发明实施例阵列基板结构平面示意图；
图12为图11阵列基板的等效电路图。
具体实施方式
下面结合附图及实施例对本发明进行详细说明如下。
本发明实施例提供一种阵列基板的制作方法，该阵列基板包括第一薄膜晶体管和像素电极，包括如下步骤：
在基板上形成缓冲层的步骤；在完成上述步骤的基板上，沉积半导体材料、源漏金属材料和透明电极层，通过一次构图工艺形成所述第一薄膜晶体管中有源层和源漏电极的以及像素电极的图形。
将有源层、源漏电极和像素电极采用一次构图工艺完成，可大大缩短薄膜晶体管的制作周期，同时由于经历比较少的工艺步骤，可以很好的提高薄膜晶体管的特性，使得薄膜晶体管的阈值电压不会发生较大的漂移，同时可提高产品的良率，而且使器件的稳定和可靠性更加适合于长时间的使用。
通过该制作方法制作出的阵列基板适用于顶栅型的LCD显示器件。
另外，本发明还提供一种适用于顶栅型顶发射的OLED结构的阵列基板的制作方法。
实施例一
本实施例以OLED（Organic Light Emitting Diode，有机发光二极管）阵列基板包括两个薄膜晶体管举例说明该阵列基板的制作方法，其中，该阵列基板包括第一薄膜晶体管、第二薄膜晶体管以及像素电极，其中，第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极通过一次构图工艺形成。
具体的，本发明实施例提供一种顶栅极的阵列基板制作方法，本发明所称的构图工艺包括光刻胶涂覆、掩模、曝光、刻蚀和光刻胶剥离等工艺，光刻胶以正性光刻胶为例。
如图1所述，该步骤具体包括：
步骤1、在基板321上形成缓冲层322，该缓冲层322可较好的防止玻璃基板与半导体层直接接触而造成的不良。
步骤2、在完成上述步骤的基板上，沉积有源层薄膜、源漏金属薄膜和透明电极层，通过一次构图工艺形成所述第一薄膜晶体管中有源层和源漏电极的以及像素电极的图形。
其中，该有源层的图形包括本征半导体层的图形和/或掺杂半导体层的图形，本步骤中的附图中以有源层包括本征半导体层的图形和掺杂半导体层的图形为例说明。
具体步骤为：
步骤201、在完成步骤1的基板上沉积本征半导体材料层323、掺杂半导体材料层324（本征半导体层323、掺杂半导体层324合为有源层薄膜）、源漏金属薄膜325和透明电极层326，参考图2。
步骤202，在透明电极层326上涂覆涂覆光刻胶327；
步骤203、采用双色调掩膜工艺进行曝光显影，其中，第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域(见图10中的A区域)、数据线和电源线区域(图未示)、第一薄膜晶体管和第二薄膜晶体管的源漏电极(参见图10中的B区域)以及像素电极区域(见图10中D区域)为光刻胶完全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域(参见图10中的C区域)为光刻胶部分保留区域；
形成上述区域之外区域为光刻胶完全去除区域；参考图3和图4。步骤204、通过第一次刻蚀工艺，去除光刻胶完全去除区域对应的透明电极层、源漏金属薄膜以及有源层薄膜，即刻蚀至缓冲层322。参考图5。
步骤205、通过灰化工艺除去所述部分保留区域对应的光刻胶，形成第一沟道区域和第二沟道区域；参考图6。
步骤206、通过第二次刻蚀工艺，去除光刻胶部分保留区域对应的像素电极层326和源漏金属薄膜325以及掺杂半导体层324。
需要说明的是，若在实际生产中有源层仅为一层，即不包括掺杂半导体层324，则只需要去除像素电极层326和源漏金属薄膜325即可，参考图7。
步骤207、剥离剩余光刻胶层，形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域的图案、数据线和电源线区域的图案、第一薄膜晶体管和第二薄膜晶体管的源漏电极以及像素电极区域的图形。继续参考图7。
其中，本征半导体层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnON材料中的一种或多种，掺杂半导体层采用非晶硅、多晶硅、微晶硅材料中的一种或多种。
其中，当有源层的图形采用氧化物半导体材料制作时，对氧化物半导体进行不同气氛的等离子体处理，该气氛例如可以为氧气、氩气、一氧化氮、氢气、或可以对氧化物半导体进行表面改性的气体。具体的，例如采用氢等离子体在空气中对半导体材料进行腐蚀处理。
或者，在氮气、氧气或空气条件下，对氧化物半导体层进行退火处理，所述退火温度为200～500℃，退火环境为空气，氧气，氮气、含有1-10%水汽的空气或含有1-10%水汽的氧气。
步骤3、在完成步骤2的基板上形成栅绝缘层328，通过构图工艺形成过孔。参考图8。
其中，该栅绝缘层例如可以为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
另外，可对不同层数的栅绝缘层进行退火工艺处理，具体退火工艺方法包括：在PECVD设备中加入氮气或空气的加热腔室，对第一栅极绝缘层进行脱氢工艺；其中，退火腔室温度为200℃～350℃，退火时间为15min～90min。
步骤4、通过一次构图工艺形成包括第一薄膜晶体管和第二薄膜晶体管的栅极、栅线的图形。
参考图9，在完成步骤3的基板上分别沉积栅金属材料329，通过构图工艺形成第一薄膜晶体管和第二薄膜晶体管的栅极、栅线，在形成栅极的过程中，需要刻除位于像素电极区域上方的栅极，避免该栅极与像素电极发生短路，进而完成阵列基板的主体结构，参考图10。
可选的，为了进一步保护位于顶处的栅电极，可在步骤4的基板上形成栅电极保护层330，该栅电极保护层330通常采用抗腐蚀、抗摩擦的导电薄膜，如ITO，IZO，TZO等薄膜以及与其性质相似的导电薄膜。当然，当栅极金属选用比较耐磨的、坚硬的金属薄膜时，可以省去栅电极保护层330。
其中，上述步骤中涉及到的刻蚀工艺可以为湿法刻蚀、干法刻蚀或干法湿法结合刻蚀。
实施例二
基于实施例一中所采用的阵列基板制作方法，本发明实施例提供一种顶栅型阵列基板，图11为本发明阵列基板实施例的平面图，所反映的是一个像素单元的结构，图12为图11阵列基板的等效电路图，图10为图11中B-B向的剖面图以及A-A向的剖面图。本实施例以OLED（Organic Light Emitting Diode，有机发光二极管）阵列基板为例，该阵列基本的主体结构包括有源层、数据线14、电源线12和栅线11，数据线14和电源线12与栅线11垂直，并与二个相邻的栅线一起限定了像素区域，像素区域内分别形成有作为寻址元件的第一薄膜晶体管（也称开关薄膜晶体管），还包括用于控制有机发光二极管的第二薄膜晶体管（也称驱动薄膜晶体管）和像素电极。
其中，第一薄膜晶体管位于栅线11与数据线14交叉点的位置，第二薄膜晶体管位于栅线11与电源线12交叉点的位置，其中第一薄膜晶体管的第一漏极151做到第二薄膜晶体管栅极所在位置，直接作为第二栅极162。
该阵列基板具体包括基板，所述基板上设有缓冲层、有源层、源漏电极、像素电极层、栅绝缘层和栅电极的图形，该源漏电极层和像素电极层直接接触连接。
其中，有源层包括第一薄膜晶体管的第一有源层171和第二薄膜晶体管的第二有源层172；
所述源漏电极层包括第一薄膜晶体管的第一源极152、第一漏极151以及第二薄膜晶体管的第二源极153、第二漏极154。
其中，栅绝缘层上设有过孔。第一薄膜晶体管的第一漏极151通过过孔与第二薄膜晶体管的第二栅极162连接。
在栅绝缘层上设有栅极层，栅极层包括第一薄膜晶体管的第一栅极161和第二薄膜晶体管的第二栅极162；第一栅极161和第二栅极162、栅线11通过一次构图工艺完成。其中第一栅极161与栅线连接，第二栅极162不与栅线11相连，同时第一栅极161与第二栅极162不相连；
其中，本实施例中的栅金属材料层和源漏金属层采用铜、铜合金、MO、MO-Al-MO合金、MO/Al-Nd/Mo叠成结构、AL、AL合金、MO/Nd/Cu/Ti/Cu合金中的一种或多种。
需要说明的是，薄膜晶体管源极和漏极的名称，因电流的流动方向不同而异，在本发明中为了方便描述，称与像素电极相连接的为漏极。所述沟道区域为源电极和漏电极相对应的空隙区域。
其中，栅绝缘层可以为一层，即第一栅绝缘层，所述栅绝缘层采 用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种。为了保证更好的器件特性，在本实施例中，可以对第一栅极绝缘层进行退火工艺（即第一栅极绝缘层为经过退火工艺处理的绝缘层），来降低栅极绝缘层中氢元素及氢的复合物对氧化物半导体特性的影响。
其中，该栅绝缘层可以为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极，所述第二栅绝缘层贴近有源层。
其中，第一栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种。第一栅绝缘层和/或第二栅绝缘层为经过退火工艺处理的绝缘层。第一栅极绝缘的材料可以很好地遏制栅电极（尤其当采用铜或铜合金时）产生的不良。第二栅极绝缘层的作用是可以很好的实现与氧化物半导体的匹配，达到提高器件性能的作用。由于第二栅极绝缘层的材料多为氧化物绝缘层，其对H+，OH-等基团的防扩散的能力比较差，所以在制作完第一栅极绝缘层时，优选地需要对其进行退火工艺处理，其作用是为了降低第一栅极绝缘层中可能发生断裂扩散的H+，OH-等基团，进而达到了提升器件稳定性的作用。
其中，该栅绝缘层为三层，即包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极，所述第五栅绝缘层贴近有源层，第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间。所述第三栅绝缘层图案采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；第四栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝 薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
本实施例中，第三栅极绝缘层采用氮化硅或氮氧化硅薄膜等无机绝缘材料，由于该材料直接与氧化物半导体层接触时会造成氧化物半导体曾的性能下降，但它却可以较好地遏制与栅极金属（尤其是当采用铜及其合金作为栅极时）接触产生不良现象，因此设置该第一栅极绝缘层紧贴栅极，并远离有源层。将第四栅极绝缘层设置在中间层，由于由氮氧化硅薄膜等无机绝缘材料制成的第四栅极绝缘层自身含有的H+，OH-等基团比较少，同时对H+，OH-等基团具有一定的防渗透能力，可以很好的遏制H+，OH-等基团向氧化物半导体层进行扩散，达到了提高器件稳定性的目的。同时，为了最大程度的提高器件的特性，将第五栅极绝缘层与氧化物半导体紧贴，可以较好地实现与氧化物半导体的匹配，达到提高器件稳定性的作用。
需要说明的是，本实施例中采用两个薄膜晶体管的制作方法同样适用于只有一个薄膜晶体管或多个薄膜晶体管阵列基板的制作方法。
本发明实施例还进一步提供一种显示器件，其包括上述阵列基板。所述显示器件可以为：液晶面板、电子纸、OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上实施方式仅用于说明本发明，而并非对本发明的限制，有关技术领域的普通技术人员，在不脱离本发明的精神和范围的情况下，还可以做出各种变化和变型，因此所有等同的技术方案也属于本发明的范畴，本发明的专利保护范围应由权利要求限定。

Claims (11)

1.一种阵列基板的制作方法，所述阵列基板包括第一薄膜晶体管和像素电极，其特征在于，包括如下步骤：
在基板上形成缓冲层的步骤；在完成上述步骤的基板上，沉积有源层薄膜、源漏金属薄膜和透明电极层，通过一次构图工艺形成所述第一薄膜晶体管中有源层和源漏电极的以及像素电极的图形；
所述阵列基板还包括第二薄膜晶体管，在所述缓冲层上所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极以及像素电极的图形通过一次构图工艺形成；
所述第一薄膜晶体管和第二薄膜晶体管中的有源层和源漏电极层以及像素电极层通过一次构图工艺形成具体包括：
沉积有源层薄膜、源漏金属薄膜和透明电极层；
涂覆光刻胶；
采用双色调掩膜工艺进行曝光显影，其中，第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域、数据线和电源线区域、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域、以及像素电极区域为光刻胶完全保留区域；
第一薄膜晶体管的第一沟道区域和第二薄膜晶体管的第二沟道区域为光刻胶部分保留区域；
形成上述区域之外区域为光刻胶完全去除区域；
通过第一次刻蚀工艺，去除光刻胶完全去除区域对应的透明电极层、源漏金属薄膜以及有源层薄膜，
通过灰化工艺除去所述部分保留区域对应的光刻胶，形成第一沟道区域和第二沟道区域；
通过第二次刻蚀工艺，去除光刻胶部分保留区域对应的像素电极层和源漏金属层；
剥离剩余光刻胶层，形成第一薄膜晶体管漏极与第二薄膜晶体管栅极的连接区域的图案、数据线和电源线区域的图案、第一薄膜晶体管和第二薄膜晶体管的源漏电极区域的图案以及像素电极的图案。
2.如权利要求1所述的阵列基板的制作方法，其特征在于，在形成有源层和源漏电极以及像素电极的图形之后还包括：
在基板上形成栅绝缘层的图形，形成过孔；
在栅绝缘层上形成第一薄膜晶体管和第二薄膜晶体管的栅极以及栅线的图形。
3.如权利要求2所述的阵列基板的制作方法，其特征在于，在在栅极及栅线上形成栅极保护层。
4.如权利要求2所述的阵列基板的制作方法，其特征在于，在栅绝缘层上形成第一薄膜晶体管和第二薄膜晶体管的栅极以及栅线的图形具体包括：
沉积栅金属层，通过构图工艺形成第一薄膜晶体管和第二薄膜晶体管的栅极以及栅线，刻除位于像素电极区域上方的栅极。
5.如权利要求2所述的阵列基板的制作方法，其特征在于，所述栅绝缘层经过退火工艺处理。
6.如权利要求5所述的阵列基板的制作方法，其特征在于，所述栅绝缘层为一层，所述栅绝缘层采用氧化硅薄膜、氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜或氧化钕薄膜、氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；或者
所述栅绝缘层为两层，即包括第一栅绝缘层和第二栅绝缘层，所述第一栅绝缘层贴近栅极层，所述第二栅绝缘层贴近有源层，所述第一栅绝缘层图案采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜、氮氧化钕薄膜、氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第二栅绝缘层采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜中的一种；或者
所述栅绝缘层为三层，包括第三栅绝缘层、第四栅绝缘层和第五栅绝缘层，所述第三栅绝缘层贴近栅极层，所述第五栅绝缘层贴近有源层，所述第四栅绝缘层位于第三栅绝缘层和第五栅绝缘层之间，所述第三栅绝缘层采用氮化硅薄膜、氮化铝薄膜、氮化锆薄膜和氮化钽薄膜中的一种；所述第四栅绝缘层采用氮氧化硅薄膜、氮氧化铝薄膜、氮氧化锆薄膜、氮氧化钽薄膜和氮氧化钕薄膜中的一种；所述第五栅绝缘层图案采用氧化硅薄膜，氧化铝薄膜，氧化钛薄膜、氮氧化硅薄膜、氧化锆薄膜、氧化钽薄膜、钛酸钡薄膜和氧化钕薄膜薄膜中的一种。
7.如权利要求1所述的阵列基板的制作方法，其特征在于，所述有源层包括本征半导体层和/或掺杂半导体层，其中，本征半导体层采用IGZO、ITZO、IZO、Cu2O、GZO、AZO、HfIZO、ZnON材料中的一种或多种，掺杂半导体层采用非晶硅、多晶硅、微晶硅材料中的一种或多种。
8.如权利要求7所述的阵列基板的制作方法，其特征在于，有源层采用氧化物半导体材料时，对氧化物半导体进行不同气氛的等离子体处理。
9.如权利要求7所述的阵列基板的制作方法，其特征在于，有源层采用氧化物半导体材料时，在氮气、氧气或空气条件下，对氧化物半导体层进行退火处理，所述退火温度为200～500℃，退火环境为空气、氧气或氮气。
10.一种利用权利要求1-9任一项所述的制作方法制备的阵列基板，其特征在于，包括基板，所述基板上设有缓冲层、有源层、源漏电极、像素电极、栅绝缘层、栅极层；所述源漏电极和像素电极直接接触；
所述栅极层包括第一薄膜晶体管的第一栅极和第二薄膜晶体管的第二栅极；
所述有源层包括第一薄膜晶体管的第一有源层和第二薄膜晶体管的第二有源层；
所述源漏电极层包括第一薄膜晶体管的第一源极、第一漏极以及第二薄膜晶体管的第二源极、第二漏极；
其中，栅绝缘层上设有过孔，第一薄膜晶体管的第一漏极通过过孔与第二薄膜晶体管的第二栅极连接。
11.一种显示装置，其特征在于，包括如权利要求10所述的阵列基板。
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